Search results for "chip-multiprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
17	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	Dynamic cache clustering for chip multiprocessors.	ICS	2009	DBLP DOI BibTeX RDF	non-uniform cache architecture (nuca), chip multiprocessor (cmp)
17	Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam	Multiband RF-interconnect for reconfigurable network-on-chip communications.	SLIP	2009	DBLP DOI BibTeX RDF	fdma, morfic, rf-interconnect, network-on-chip, reconfigurable, chip multiprocessor
17	Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay	Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.	ISCA	2009	DBLP DOI BibTeX RDF	checkpoint-based architecture, hardware speculation, sst, chip multiprocessor, cmp, instruction-level parallelism, processor architecture, memory-level parallelism
17	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache
17	Yefu Wang, Kai Ma, Xiaorui Wang	Temperature-constrained power control for chip multiprocessors with online model estimation.	ISCA	2009	DBLP DOI BibTeX RDF	power management, chip multiprocessor, feedback control
17	David K. Tam, Reza Azimi, Livio Soares, Michael Stumm	RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations.	ASPLOS	2009	DBLP DOI BibTeX RDF	miss rate curve, performance monitoring unit, shared cache management, chip multiprocessor, dynamic optimization, multicore processor, shared cache, cache management, cache partitioning, hardware performance counters, online optimization
17	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Power dissipation model, Microarchitectural level simulator, Heterogeneus on-chip interconnection network, Chip-multiprocessor, Parallel scientific applications
17	Taeho Kgil, Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Krisztián Flautner, Trevor N. Mudge	PicoServer: Using 3D stacking technology to build energy efficient servers.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	3D stacking technology, Tier-1/2/3 server, Low power, chip multiprocessor, full-system simulation
17	Noel Eisley, Li-Shiuan Peh, Li Shang	Leveraging on-chip networks for data cache migration in chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	network-driven computing, interconnection network, CMP, chip-multiprocessor, migration
17	Tse-Yu Yeh	Low-Power, High-Performance Architecture of the PWRficient Processor Family.	IEEE Micro	2007	DBLP DOI BibTeX RDF	coherent memory system, low power, computer architecture, chip multiprocessor, high-performance, processor
17	Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi	On-Chip Optical Technology in Future Bus-Based Multicore Designs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	optical technology, snoopy bus, chip multiprocessor, on-chip interconnect
17	Xudong Shi 0003, Feiqi Su, Jih-Kwon Peir, Ye Xia 0001, Zhen Yang	Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility.	ISPASS	2007	DBLP DOI BibTeX RDF	multiple cache organization, single-pass simulation, on-chip storage space, on-chip cache capacity, single-pass stack simulation, global stack, shared stack, per-core private stack, single simulation pass, average memory access time, chip-multiprocessor, data replication, data accessibility, abstract model, reuse distances
17	Seunghoon Kim, Robert P. Dick, Russ Joseph	Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	power regulation, multimedia, chip multiprocessor, battery
17	Sebastian Herbert, Diana Marculescu	Analysis of dynamic voltage/frequency scaling in chip-multiprocessors.	ISLPED	2007	DBLP DOI BibTeX RDF	chip-multiprocessor, dynamic voltage/frequency scaling
17	Michela Becchi, Mark A. Franklin, Patrick Crowley	Performance/area efficiency in chip multiprocessors with micro-caches.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	networking workload, chip multiprocessor, cache hierarchies
17	Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar	Speculative thread decomposition through empirical optimization.	PPoPP	2007	DBLP DOI BibTeX RDF	empirical search, chip multiprocessor, decomposition, multi-core, thread-level speculation
17	Kyle J. Nesbit, James Laudon, James E. Smith 0001	Virtual private caches.	ISCA	2007	DBLP DOI BibTeX RDF	quality of service, chip multiprocessor, soft real-time, shared caches, performance isolation
17	Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman	ParallAX: an architecture for real-time physics.	ISCA	2007	DBLP DOI BibTeX RDF	real-time physics, chip multiprocessor, physics based animation, stream processing, interactive entertainment, application specific processor
17	Seung Eun Lee, Nader Bagherzadeh	Increasing the throughput of an adaptive router in network-on-chip (NoC).	CODES+ISSS	2006	DBLP DOI BibTeX RDF	adaptive router, interconnection network, chip-multiprocessor, wormhole routing, network-on-chip (NoC)
17	Noel Eisley, Vassos Soteriou, Li-Shiuan Peh	High-level power analysis for multi-core chips.	CASES	2006	DBLP DOI BibTeX RDF	simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC)
17	Juan del Cuvillo, Weirong Zhu, Guang R. Gao	Landing openMP on cyclops-64: an efficient mapping of openMP to a many-core system-on-a-chip.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	performance evaluation, chip multiprocessor, openMP, system-on-a-chip, run-time system
17	Franz Franchetti, Yevgen Voronenko, Markus Püschel	Tools and techniques for performance - FFT program generation for shared memory: SMP and multicore.	SC	2006	DBLP DOI BibTeX RDF	chip multiprocessor, fast fourier transform, shared memory, multicore, automatic parallelization
17	Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy	Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance.	ASPLOS	2006	DBLP DOI BibTeX RDF	redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy
17	Thomas Y. Yeh, Glenn Reinman	Fast and fair: data-stream quality of service.	CASES	2005	DBLP DOI BibTeX RDF	NUCA, non-uniform access, per thread degradation, cluster, adaptive, cache, distributed, data-stream, partition, embedded, CMP, chip multiprocessor, migration, bandwidth, QOS, phase, memory wall, PDAS
17	Jinson Koppanalil, Eric Rotenberg	A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	slipstream, preexecution, chip multiprocessor, multithreading, Microarchitecture
17	Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar	Min-cut program decomposition for thread-level speculation.	PLDI	2004	DBLP DOI BibTeX RDF	partitioning, chip multiprocessor, thread-level speculation, min-cut, program decomposition
17	Rakesh Kumar 0002, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen	Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures.	IEEE Comput. Archit. Lett.	2003	DBLP DOI BibTeX RDF	chip multiprocessor, low-power architecture
17	Manohar K. Prabhu, Kunle Olukotun	Using thread-level speculation to simplify manual parallelization.	PPoPP	2003	DBLP DOI BibTeX RDF	feedback-driven optimization, manual parallel programming, chip multiprocessor, multithreading, data speculation
17	Mitsuhisa Sato	OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip Multiprocessors.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
17	Kunle Olukotun, Lance Hammond, Mark Willey	Improving the performance of speculatively parallel applications on the Hydra CMP.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF	feedback-driven optimization, performance evaluation, parallel programming, chip multiprocessor, multithreading, data speculation
17	Keizo Saisho, Takeshi Sano, Keniti Iwata, Akira Fukuda	The Architecture of OCMP and its Evaluation.	ISPAN	1997	DBLP DOI BibTeX RDF	on chip multiprocessor, instruction level dispatch, fork-join type parallel processing, evaluation using simulation, shared cache, private cache
17	Zheng Li, Jie Wu, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun	A high-performance low-power nanophotonic on-chip network.	ISLPED	2009	DBLP DOI BibTeX RDF	networks-on-chip, optical communication, silicon photonics
17	Martin Schoeberl	A Time-Triggered Network-on-Chip.	FPL	2007	DBLP DOI BibTeX RDF
17	Tianzhou Chen, Guobing Chen, Hongjun Dai, Qingsong Shi	A function-based on-chip communication design in the heterogeneous multi-core architecture.	MUE	2007	DBLP DOI BibTeX RDF
17	Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk 0001, I. Demirkiran	Compiler-Directed Management of Leakage Power in Software-Managed Memories.	ISVLSI	2006	DBLP DOI BibTeX RDF
17	Ozcan Ozturk 0001, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy	An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors.	ISVLSI	2006	DBLP DOI BibTeX RDF
17	Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie 0001, Narayanan Vijaykrishnan, Mahmut T. Kandemir	Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.	ISCA	2006	DBLP DOI BibTeX RDF
17	Mahmut T. Kandemir, Ozcan Ozturk 0001, Mustafa Karaköy	Dynamic on-chip memory management for chip multiprocessors.	CASES	2004	DBLP DOI BibTeX RDF	chip multiprocessors, optimizing compiler, memory bank
17	Guangyu Chen, Mahmut T. Kandemir, Alok N. Choudhary, Ibrahim Kolcu	Exploiting On-Chip Data Transfers for Improving Performance of Chip-Scale Multiprocessors.	Euro-Par	2003	DBLP DOI BibTeX RDF
16	Rakesh Pandey, Aryabartta Sahu	Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip Multiprocessor with Hybrid Interconnect.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
16	Avishek Choudhury, Biplab K. Sikdar	Modeling Remapping Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space Exploration.	J. Electron. Test.	2020	DBLP DOI BibTeX RDF
16	Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar	P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA.	Wirel. Pers. Commun.	2020	DBLP DOI BibTeX RDF
16	Kaiwei Zou, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001	Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture.	DATE	2019	DBLP DOI BibTeX RDF
16	Andreas G. Andreou, Daniel R. Mendat	Graphical Model Transformation Analysis for Cognitive Computing and Machine Learning on the SpiNNaker Chip Multiprocessor.	DSD	2019	DBLP DOI BibTeX RDF
16	Tomas Figliolia, Andreas G. Andreou	The Conical-Fishbone Clock Tree: A Clock-Distribution Network for a Heterogeneous Chip Multiprocessor AI Chiplet.	DSD	2019	DBLP DOI BibTeX RDF
16	Rakesh Pandey, Aryabartta Sahu	Access-Aware Self-Adaptive Data Mapping onto 3D-Stacked Hybrid DRAM-PCM Based Chip-Multiprocessor.	HPCC/SmartCity/DSS	2019	DBLP DOI BibTeX RDF
16	Avishek Choudhury, Biplab K. Sikdar	Soft Error Resilience in Chip Multiprocessor Cache using a Markov Model Based Re-usability Predictor.	ICCD	2019	DBLP DOI BibTeX RDF
16	Christophe Bobda, Franck Yonga, Martin Gebser, Harold Ishebabi, Torsten Schaub	High-level synthesis of on-chip multiprocessor architectures based on answer set programming.	J. Parallel Distributed Comput.	2018	DBLP DOI BibTeX RDF
16	Huseyin G. Arslan, Yu-Chu Tian, Fenglian Li, Chen Peng 0001, Minrui Fei	Control-theoretic adaptive cache-fair scheduling of chip multiprocessor systems.	Trans. Inst. Meas. Control	2018	DBLP DOI BibTeX RDF
16	Sirine Mnejja, Yassine Aydi, Mohamed Abid	Exploring Hybrid NoC Architecture for Chip Multiprocessor.	ICM	2018	DBLP DOI BibTeX RDF
16	Avishek Choudhury, Biplab K. Sikdar	Modeling & Analysis of Redundancy Based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache.	VLSID	2018	DBLP DOI BibTeX RDF
16	Tórur Biskopstø Strøm, Wolfgang Puffitsch, Martin Schoeberl	Hardware locks for a real-time Java chip multiprocessor.	Concurr. Comput. Pract. Exp.	2017	DBLP DOI BibTeX RDF
16	Zhou Zhao, Ashok Srivastava, Lu Peng 0001, Shaoming Chen, Saraju P. Mohanty	A novel switchable pin method for regulating power in chip-multiprocessor.	Integr.	2017	DBLP DOI BibTeX RDF
16	Jianhua Li 0003, Minming Li, Chun Jason Xue, Yiming Ouyang, Fanfan Shen	Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
16	Shirshendu Das, Hemangee K. Kapoor	Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor.	ISVLSI	2017	DBLP DOI BibTeX RDF
16	Rakesh Pandey, Aryabartta Sahu	Efficient Mapping of Multi-threaded Applications onto 3D Stacked Chip-Multiprocessor.	HPCC/SmartCity/DSS	2017	DBLP DOI BibTeX RDF
16	Vassilios A. Chouliaras, David Stevens, Vincent M. Dwyer	VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
16	Pavlos Maniotis, Savvas Gitzenis, Leandros Tassiulas, Nikos Pleros	An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory.	Opt. Switch. Netw.	2016	DBLP DOI BibTeX RDF
16	Samuel J. Parker, Vassilios A. Chouliaras	An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor.	J. Syst. Archit.	2016	DBLP DOI BibTeX RDF
16	André Rocha, Cláudio Silva 0002, Rasmus Bo Sørensen, Jens Sparsø, Martin Schoeberl	Avionics Applications on a Time-Predictable Chip-Multiprocessor.	PDP	2016	DBLP DOI BibTeX RDF
16	Aryabartta Sahu	Thermal aware scheduling and mapping of multiphase applications onto chip multiprocessor.	DATE	2016	DBLP BibTeX RDF
16	Houman Homayoun	Heterogeneous chip multiprocessor architectures for big data applications.	Conf. Computing Frontiers	2016	DBLP DOI BibTeX RDF
16	Yaobin Wang, Hong An, Zhiqin Liu, Ling Li, Jun Huang 0005	A Flexible Chip Multiprocessor Simulator Dedicated for Thread Level Speculation.	Trustcom/BigDataSE/ISPA	2016	DBLP DOI BibTeX RDF
16	Antoni Roca 0001, Carles Hernández 0001, Mario Lodde, José Flich	Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems.	Comput. Electr. Eng.	2015	DBLP DOI BibTeX RDF
16	Hao Shen, Qinru Qiu	Chip Multiprocessor Performance Modeling for Contention Aware Task Migration and Frequency Scaling.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
16	Tórur Biskopstø Strøm, Martin Schoeberl	Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor.	ISORC	2015	DBLP DOI BibTeX RDF
16	Xinke Chen, Guangfei Zhang, Huandong Wang, Ruiyang Wu, Peng Wu, Longbing Zhang	MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation.	DATE	2015	DBLP BibTeX RDF
16	Eren Unlu, Christophe Moy	Reconfigurable Traffic-Aware Radio Interconnect for a 2048-core Chip Multiprocessor.	DSD	2015	DBLP DOI BibTeX RDF
16	Yanhua Li, Youhui Zhang, Weimin Zheng	Position-aware thread-level speculative parallelization for large-scale chip-multiprocessor.	Conf. Computing Frontiers	2015	DBLP DOI BibTeX RDF
16	Arseniy Vitkovskiy, Vassos Soteriou, Paul V. Gratz	Clotho: Proactive wearout deceleration in Chip-Multiprocessor interconnects.	ICCD	2015	DBLP DOI BibTeX RDF
16	Zhou Zhao, Ashok Srivastava, Lu Peng 0001, Shaoming Chen, Saraju P. Mohanty	Circuit Implementation of Switchable Pins in Chip Multiprocessor.	iNIS	2015	DBLP DOI BibTeX RDF
16	Pavlos Maniotis, Savvas Gitzenis, Leandros Tassiulas, Nikos Pleros	High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures.	SiPhotonics@HiPEAC	2015	DBLP DOI BibTeX RDF
16	Samuel J. Parker	An automated OpenCL FPGA compilation framework targeting a configurable, VLIW chip multiprocessor.		2015	RDF
16	Fang Lu, Huimin Cui, Lei Wang 0004, Lei Liu 0030, Chenggang Wu 0002, Xiaobing Feng 0002, Pen-Chung Yew	Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms.	J. Comput. Sci. Technol.	2014	DBLP DOI BibTeX RDF
16	Ju Hee Choi, Jong Wook Kwak, Chu Shik Jhon	Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
16	Kai Ma, Xiaorui Wang, Yefu Wang	DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
16	Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, Soheil Ghiasi	Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
16	Xiaowen Wu, Jiang Xu 0001, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast, Xuan Wang 0001	SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor.	ACM J. Emerg. Technol. Comput. Syst.	2014	DBLP DOI BibTeX RDF
16	Xianmin Chen, Niraj K. Jha	Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles.	ACM J. Emerg. Technol. Comput. Syst.	2014	DBLP DOI BibTeX RDF
16	V. Karthikeyan V. J. Vijayalakshmi	Control Loop Feedback Mechanism for Generic Array Logic Chip Multiprocessor.	CoRR	2014	DBLP BibTeX RDF
16	Magnus Jahre	Graph-based performance accounting for chip multiprocessor memory systems.	PACT	2014	DBLP DOI BibTeX RDF
16	Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger, Alexander V. Veidenbaum	Dynamic-vector execution on a general purpose EDGE chip multiprocessor.	ICSAMOS	2014	DBLP DOI BibTeX RDF
16	Martti Forsell, Jussi Roivainen	REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor.	ACSSC	2014	DBLP DOI BibTeX RDF
16	Pavlos Maniotis, Savvas Gitzenis, Leandros Tassiulas, Nikos Pleros	A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memory.	OFC	2014	DBLP DOI BibTeX RDF
16	Ashish Venkat, Dean M. Tullsen	Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor.	ISCA	2014	DBLP DOI BibTeX RDF
16	Bhoopendra Kumar, Aryabartta Sahu	Online Scheduling of Applications on 3D Stacked Large Chip Multiprocessor.	PDCAT	2014	DBLP DOI BibTeX RDF
16	Flavius Gruian, Martin Schoeberl	Hardware support for CSP on a Java chip multiprocessor.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
16	Sanghoon Lee 0006, James Tuck 0001	Automatic parallelization of fine-grained metafunctions on a chip multiprocessor.	ACM Trans. Archit. Code Optim.	2013	DBLP DOI BibTeX RDF
16	Ismail Akturk, Ozcan Ozturk 0001	Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design.	J. Electron. Test.	2013	DBLP DOI BibTeX RDF
16	Luis Angel D. Bathen, Yongjin Ahn, Sudeep Pasricha, Nikil D. Dutt	MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining.	ACM Trans. Embed. Comput. Syst.	2013	DBLP DOI BibTeX RDF
16	Jiayin Li, Meikang Qiu, Jianwei Niu 0002, Laurence T. Yang, Yongxin Zhu 0001, Zhong Ming 0001	Thermal-aware task scheduling in 3D chip multiprocessor with real-time constrained workloads.	ACM Trans. Embed. Comput. Syst.	2013	DBLP DOI BibTeX RDF
16	Apan Qasem, Joshua Magee	Improving TLB performance on current chip multiprocessor architectures through demand-driven superpaging.	Softw. Pract. Exp.	2013	DBLP DOI BibTeX RDF
16	Aditya Agrawal, Prabhat Jain, Amin Ansari, Josep Torrellas	Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies.	HPCA	2013	DBLP DOI BibTeX RDF
16	Muhammad Nadeem, HeeJong Park 0001, Zhenmin Li, Morteza Biglari-Abhari, Zoran Salcic	GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems.	ARCS	2013	DBLP DOI BibTeX RDF
16	Tórur Biskopstø Strøm, Wolfgang Puffitsch, Martin Schoeberl	Chip-multiprocessor hardware locks for safety-critical Java.	JTRES	2013	DBLP DOI BibTeX RDF
16	David Kadjo, Hyungjun Kim, Paul Gratz, Jiang Hu, Raid Ayoub	Power gating with block migration in chip-multiprocessor last-level caches.	ICCD	2013	DBLP DOI BibTeX RDF
16	Eustace Painkras	A chip multiprocessor for a large-scale neural simulator.		2013	RDF
16	Hammad Rashid, Clara Novoa, Mark McKenney, Apan Qasem	Efficient parallel solutions to the integral knapsack problem on current chip-multiprocessor systems.	Int. J. Parallel Emergent Distributed Syst.	2012	DBLP DOI BibTeX RDF
16	David Stevens, Vassilios A. Chouliaras, Vicente Azorin-Peris, Jia Zheng, Angelos Echiadis, Sijung Hu	BioThreads: A Novel VLIW-Based Chip Multiprocessor for Accelerating Biomedical Image Processing Applications.	IEEE Trans. Biomed. Circuits Syst.	2012	DBLP DOI BibTeX RDF