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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 526 occurrences of 280 keywords
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Results
Found 503 publication records. Showing 503 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Shirish Bahirat, Sudeep Pasricha |
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 129-136, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
photonic interconnect, network-on-chip, chip multiprocessor |
17 | Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem |
Dynamic cache clustering for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 56-67, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
non-uniform cache architecture (nuca), chip multiprocessor (cmp) |
17 | Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam |
Multiband RF-interconnect for reconfigurable network-on-chip communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 107-108, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fdma, morfic, rf-interconnect, network-on-chip, reconfigurable, chip multiprocessor |
17 | Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay |
Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 484-495, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
checkpoint-based architecture, hardware speculation, sst, chip multiprocessor, cmp, instruction-level parallelism, processor architecture, memory-level parallelism |
17 | Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki |
Reactive NUCA: near-optimal block placement and replication in distributed caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 184-195, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache |
17 | Yefu Wang, Kai Ma, Xiaorui Wang |
Temperature-constrained power control for chip multiprocessors with online model estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 314-324, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
power management, chip multiprocessor, feedback control |
17 | David K. Tam, Reza Azimi, Livio Soares, Michael Stumm |
RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2009, Washington, DC, USA, March 7-11, 2009, pp. 121-132, 2009, ACM, 978-1-60558-406-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
miss rate curve, performance monitoring unit, shared cache management, chip multiprocessor, dynamic optimization, multicore processor, shared cache, cache management, cache partitioning, hardware performance counters, online optimization |
17 | Antonio Flores, Juan L. Aragón, Manuel E. Acacio |
An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 45(3), pp. 341-364, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Power dissipation model, Microarchitectural level simulator, Heterogeneus on-chip interconnection network, Chip-multiprocessor, Parallel scientific applications |
17 | Taeho Kgil, Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Krisztián Flautner, Trevor N. Mudge |
PicoServer: Using 3D stacking technology to build energy efficient servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(4), pp. 16:1-16:34, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
3D stacking technology, Tier-1/2/3 server, Low power, chip multiprocessor, full-system simulation |
17 | Noel Eisley, Li-Shiuan Peh, Li Shang |
Leveraging on-chip networks for data cache migration in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 197-207, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
network-driven computing, interconnection network, CMP, chip-multiprocessor, migration |
17 | Tse-Yu Yeh |
Low-Power, High-Performance Architecture of the PWRficient Processor Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(2), pp. 69-78, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
coherent memory system, low power, computer architecture, chip multiprocessor, high-performance, processor |
17 | Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi |
On-Chip Optical Technology in Future Bus-Based Multicore Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(1), pp. 56-66, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
optical technology, snoopy bus, chip multiprocessor, on-chip interconnect |
17 | Xudong Shi 0003, Feiqi Su, Jih-Kwon Peir, Ye Xia 0001, Zhen Yang |
Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 126-135, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiple cache organization, single-pass simulation, on-chip storage space, on-chip cache capacity, single-pass stack simulation, global stack, shared stack, per-core private stack, single simulation pass, average memory access time, chip-multiprocessor, data replication, data accessibility, abstract model, reuse distances |
17 | Seunghoon Kim, Robert P. Dick, Russ Joseph |
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 105-110, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power regulation, multimedia, chip multiprocessor, battery |
17 | Sebastian Herbert, Diana Marculescu |
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 38-43, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
chip-multiprocessor, dynamic voltage/frequency scaling |
17 | Michela Becchi, Mark A. Franklin, Patrick Crowley |
Performance/area efficiency in chip multiprocessors with micro-caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007, pp. 247-258, 2007, ACM, 978-1-59593-683-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
networking workload, chip multiprocessor, cache hierarchies |
17 | Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar |
Speculative thread decomposition through empirical optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2007, San Jose, California, USA, March 14-17, 2007, pp. 205-214, 2007, ACM, 978-1-59593-602-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
empirical search, chip multiprocessor, decomposition, multi-core, thread-level speculation |
17 | Kyle J. Nesbit, James Laudon, James E. Smith 0001 |
Virtual private caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 57-68, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
quality of service, chip multiprocessor, soft real-time, shared caches, performance isolation |
17 | Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman |
ParallAX: an architecture for real-time physics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 232-243, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
real-time physics, chip multiprocessor, physics based animation, stream processing, interactive entertainment, application specific processor |
17 | Seung Eun Lee, Nader Bagherzadeh |
Increasing the throughput of an adaptive router in network-on-chip (NoC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 82-87, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive router, interconnection network, chip-multiprocessor, wormhole routing, network-on-chip (NoC) |
17 | Noel Eisley, Vassos Soteriou, Li-Shiuan Peh |
High-level power analysis for multi-core chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 389-400, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC) |
17 | Juan del Cuvillo, Weirong Zhu, Guang R. Gao |
Landing openMP on cyclops-64: an efficient mapping of openMP to a many-core system-on-a-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 41-50, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
performance evaluation, chip multiprocessor, openMP, system-on-a-chip, run-time system |
17 | Franz Franchetti, Yevgen Voronenko, Markus Püschel |
Tools and techniques for performance - FFT program generation for shared memory: SMP and multicore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 115, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
chip multiprocessor, fast fourier transform, shared memory, multicore, automatic parallelization |
17 | Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy |
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 83-94, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy |
17 | Thomas Y. Yeh, Glenn Reinman |
Fast and fair: data-stream quality of service. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 237-248, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
NUCA, non-uniform access, per thread degradation, cluster, adaptive, cache, distributed, data-stream, partition, embedded, CMP, chip multiprocessor, migration, bandwidth, QOS, phase, memory wall, PDAS |
17 | Jinson Koppanalil, Eric Rotenberg |
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(4), pp. 399-413, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
slipstream, preexecution, chip multiprocessor, multithreading, Microarchitecture |
17 | Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar |
Min-cut program decomposition for thread-level speculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, Washington, DC, USA, June 9-11, 2004, pp. 59-70, 2004, ACM, 1-58113-807-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
partitioning, chip multiprocessor, thread-level speculation, min-cut, program decomposition |
17 | Rakesh Kumar 0002, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen |
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 2, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
chip multiprocessor, low-power architecture |
17 | Manohar K. Prabhu, Kunle Olukotun |
Using thread-level speculation to simplify manual parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2003, June 11-13, 2003, San Diego, CA, USA, pp. 1-12, 2003, ACM, 1-58113-588-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
feedback-driven optimization, manual parallel programming, chip multiprocessor, multithreading, data speculation |
17 | Mitsuhisa Sato |
OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 109-111, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading |
17 | Kunle Olukotun, Lance Hammond, Mark Willey |
Improving the performance of speculatively parallel applications on the Hydra CMP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 13th international conference on Supercomputing, ICS 1999, Rhodes, Greece, June 20-25, 1999, pp. 21-30, 1999, ACM, 1-58113-164-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
feedback-driven optimization, performance evaluation, parallel programming, chip multiprocessor, multithreading, data speculation |
17 | Keizo Saisho, Takeshi Sano, Keniti Iwata, Akira Fukuda |
The Architecture of OCMP and its Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 71-77, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
on chip multiprocessor, instruction level dispatch, fork-join type parallel processing, evaluation using simulation, shared cache, private cache |
17 | Zheng Li, Jie Wu, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun |
A high-performance low-power nanophotonic on-chip network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 291-294, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
networks-on-chip, optical communication, silicon photonics |
17 | Martin Schoeberl |
A Time-Triggered Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 377-382, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Tianzhou Chen, Guobing Chen, Hongjun Dai, Qingsong Shi |
A function-based on-chip communication design in the heterogeneous multi-core architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MUE ![In: 2007 International Conference on Multimedia and Ubiquitous Engineering (MUE 2007), 26-28 April 2007, Seoul, Korea, pp. 1086-1092, 2007, IEEE Computer Society, 978-0-7695-2777-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk 0001, I. Demirkiran |
Compiler-Directed Management of Leakage Power in Software-Managed Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 450-451, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Ozcan Ozturk 0001, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy |
An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 50-58, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie 0001, Narayanan Vijaykrishnan, Mahmut T. Kandemir |
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA, pp. 130-141, 2006, IEEE Computer Society, 0-7695-2608-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Mahmut T. Kandemir, Ozcan Ozturk 0001, Mustafa Karaköy |
Dynamic on-chip memory management for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 14-23, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
chip multiprocessors, optimizing compiler, memory bank |
17 | Guangyu Chen, Mahmut T. Kandemir, Alok N. Choudhary, Ibrahim Kolcu |
Exploiting On-Chip Data Transfers for Improving Performance of Chip-Scale Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2003. Parallel Processing, 9th International Euro-Par Conference, Klagenfurt, Austria, August 26-29, 2003. Proceedings, pp. 271-278, 2003, Springer, 3-540-40788-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Rakesh Pandey, Aryabartta Sahu |
Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip Multiprocessor with Hybrid Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 9(4), pp. 1945-1959, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Avishek Choudhury, Biplab K. Sikdar |
Modeling Remapping Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 36(1), pp. 59-73, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar |
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 114(4), pp. 3295-3319, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Kaiwei Zou, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001 |
Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, pp. 1172-1177, 2019, IEEE, 978-3-9819263-2-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Andreas G. Andreou, Daniel R. Mendat |
Graphical Model Transformation Analysis for Cognitive Computing and Machine Learning on the SpiNNaker Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 22nd Euromicro Conference on Digital System Design, DSD 2019, Kallithea, Greece, August 28-30, 2019, pp. 299-304, 2019, IEEE, 978-1-7281-2862-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Tomas Figliolia, Andreas G. Andreou |
The Conical-Fishbone Clock Tree: A Clock-Distribution Network for a Heterogeneous Chip Multiprocessor AI Chiplet. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 22nd Euromicro Conference on Digital System Design, DSD 2019, Kallithea, Greece, August 28-30, 2019, pp. 160-165, 2019, IEEE, 978-1-7281-2862-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Rakesh Pandey, Aryabartta Sahu |
Access-Aware Self-Adaptive Data Mapping onto 3D-Stacked Hybrid DRAM-PCM Based Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC/SmartCity/DSS ![In: 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019, Zhangjiajie, China, August 10-12, 2019, pp. 389-396, 2019, IEEE, 978-1-7281-2058-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Avishek Choudhury, Biplab K. Sikdar |
Soft Error Resilience in Chip Multiprocessor Cache using a Markov Model Based Re-usability Predictor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 37th IEEE International Conference on Computer Design, ICCD 2019, Abu Dhabi, United Arab Emirates, November 17-20, 2019, pp. 468-476, 2019, IEEE, 978-1-5386-6648-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Christophe Bobda, Franck Yonga, Martin Gebser, Harold Ishebabi, Torsten Schaub |
High-level synthesis of on-chip multiprocessor architectures based on answer set programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 117, pp. 161-179, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Huseyin G. Arslan, Yu-Chu Tian, Fenglian Li, Chen Peng 0001, Minrui Fei |
Control-theoretic adaptive cache-fair scheduling of chip multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Inst. Meas. Control ![In: Trans. Inst. Meas. Control 40(10), pp. 3095-3104, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Sirine Mnejja, Yassine Aydi, Mohamed Abid |
Exploring Hybrid NoC Architecture for Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 30th International Conference on Microelectronics, ICM 2018, Sousse, Tunisia, December 16-19, 2018, pp. 307-310, 2018, IEEE, 978-1-5386-8167-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Avishek Choudhury, Biplab K. Sikdar |
Modeling & Analysis of Redundancy Based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018, pp. 115-120, 2018, IEEE Computer Society, 978-1-5386-3692-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Tórur Biskopstø Strøm, Wolfgang Puffitsch, Martin Schoeberl |
Hardware locks for a real-time Java chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 29(6), 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Zhou Zhao, Ashok Srivastava, Lu Peng 0001, Shaoming Chen, Saraju P. Mohanty |
A novel switchable pin method for regulating power in chip-multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 58, pp. 329-338, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Jianhua Li 0003, Minming Li, Chun Jason Xue, Yiming Ouyang, Fanfan Shen |
Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(10), pp. 1747-1762, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Shirshendu Das, Hemangee K. Kapoor |
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 182-187, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Rakesh Pandey, Aryabartta Sahu |
Efficient Mapping of Multi-threaded Applications onto 3D Stacked Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC/SmartCity/DSS ![In: 19th IEEE International Conference on High Performance Computing and Communications; 15th IEEE International Conference on Smart City; 3rd IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2017, Bangkok, Thailand, December 18-20, 2017, pp. 324-331, 2017, IEEE Computer Society, 978-1-5386-2588-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Vassilios A. Chouliaras, David Stevens, Vincent M. Dwyer |
VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 47, pp. 466-485, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Pavlos Maniotis, Savvas Gitzenis, Leandros Tassiulas, Nikos Pleros |
An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Opt. Switch. Netw. ![In: Opt. Switch. Netw. 22, pp. 54-68, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Samuel J. Parker, Vassilios A. Chouliaras |
An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 68, pp. 17-37, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | André Rocha, Cláudio Silva 0002, Rasmus Bo Sørensen, Jens Sparsø, Martin Schoeberl |
Avionics Applications on a Time-Predictable Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016, Heraklion, Crete, Greece, February 17-19, 2016, pp. 777-785, 2016, IEEE Computer Society, 978-1-4673-8776-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Aryabartta Sahu |
Thermal aware scheduling and mapping of multiphase applications onto chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pp. 1096-1101, 2016, IEEE, 978-3-9815-3707-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
16 | Houman Homayoun |
Heterogeneous chip multiprocessor architectures for big data applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the ACM International Conference on Computing Frontiers, CF'16, Como, Italy, May 16-19, 2016, pp. 400-405, 2016, ACM, 978-1-4503-4128-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Yaobin Wang, Hong An, Zhiqin Liu, Ling Li, Jun Huang 0005 |
A Flexible Chip Multiprocessor Simulator Dedicated for Thread Level Speculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trustcom/BigDataSE/ISPA ![In: 2016 IEEE Trustcom/BigDataSE/ISPA, Tianjin, China, August 23-26, 2016, pp. 2127-2132, 2016, IEEE, 978-1-5090-3205-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Antoni Roca 0001, Carles Hernández 0001, Mario Lodde, José Flich |
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 45, pp. 374-385, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Hao Shen, Qinru Qiu |
Chip Multiprocessor Performance Modeling for Contention Aware Task Migration and Frequency Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 11(3), pp. 263-277, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Tórur Biskopstø Strøm, Martin Schoeberl |
Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: IEEE 18th International Symposium on Real-Time Distributed Computing, ISORC 2015, Auckland, New Zealand, 13-17 April, 2015, pp. 268-271, 2015, IEEE Computer Society, 978-1-4799-8781-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Xinke Chen, Guangfei Zhang, Huandong Wang, Ruiyang Wu, Peng Wu, Longbing Zhang |
MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 211-216, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
16 | Eren Unlu, Christophe Moy |
Reconfigurable Traffic-Aware Radio Interconnect for a 2048-core Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2015 Euromicro Conference on Digital System Design, DSD 2015, Madeira, Portugal, August 26-28, 2015, pp. 139-145, 2015, IEEE Computer Society, 978-1-4673-8035-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Yanhua Li, Youhui Zhang, Weimin Zheng |
Position-aware thread-level speculative parallelization for large-scale chip-multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 12th ACM International Conference on Computing Frontiers, CF'15, Ischia, Italy, May 18-21, 2015, pp. 21:1-21:8, 2015, ACM, 978-1-4503-3358-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Arseniy Vitkovskiy, Vassos Soteriou, Paul V. Gratz |
Clotho: Proactive wearout deceleration in Chip-Multiprocessor interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 33rd IEEE International Conference on Computer Design, ICCD 2015, New York City, NY, USA, October 18-21, 2015, pp. 117-124, 2015, IEEE Computer Society, 978-1-4673-7166-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Zhou Zhao, Ashok Srivastava, Lu Peng 0001, Shaoming Chen, Saraju P. Mohanty |
Circuit Implementation of Switchable Pins in Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2015, Indore, India, December 21-23, 2015, pp. 89-94, 2015, IEEE, 978-1-4673-9692-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Pavlos Maniotis, Savvas Gitzenis, Leandros Tassiulas, Nikos Pleros |
High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPhotonics@HiPEAC ![In: 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, SiPhotonics@HiPEAC 2015, Amsterdam, Netherlands, January 19, 2015, pp. 1-8, 2015, IEEE Computer Society, 978-1-4799-8093-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Samuel J. Parker |
An automated OpenCL FPGA compilation framework targeting a configurable, VLIW chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2015 |
RDF |
|
16 | Fang Lu, Huimin Cui, Lei Wang 0004, Lei Liu 0030, Chenggang Wu 0002, Xiaobing Feng 0002, Pen-Chung Yew |
Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 29(1), pp. 21-37, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Ju Hee Choi, Jong Wook Kwak, Chu Shik Jhon |
Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 97-D(8), pp. 2166-2169, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Kai Ma, Xiaorui Wang, Yefu Wang |
DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 63(7), pp. 1736-1750, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, Soheil Ghiasi |
Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5), pp. 752-762, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Xiaowen Wu, Jiang Xu 0001, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast, Xuan Wang 0001 |
SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 10(4), pp. 29:1-29:25, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Xianmin Chen, Niraj K. Jha |
Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 11(1), pp. 3:1-3:16, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | V. Karthikeyan V. J. Vijayalakshmi |
Control Loop Feedback Mechanism for Generic Array Logic Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1402.5617, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
16 | Magnus Jahre |
Graph-based performance accounting for chip multiprocessor memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: International Conference on Parallel Architectures and Compilation, PACT '14, Edmonton, AB, Canada, August 24-27, 2014, pp. 473-474, 2014, ACM, 978-1-4503-2809-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger, Alexander V. Veidenbaum |
Dynamic-vector execution on a general purpose EDGE chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2014, Agios Konstantinos, Samos, Greece, July 14-17, 2014, pp. 18-25, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Martti Forsell, Jussi Roivainen |
REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2014, Pacific Grove, CA, USA, November 2-5, 2014, pp. 1709-1713, 2014, IEEE, 978-1-4799-8297-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Pavlos Maniotis, Savvas Gitzenis, Leandros Tassiulas, Nikos Pleros |
A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2014, San Francisco, CA, USA, March 9-13, 2014, pp. 1-3, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Ashish Venkat, Dean M. Tullsen |
Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA, June 14-18, 2014, pp. 121-132, 2014, IEEE Computer Society, 978-1-4799-4396-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Bhoopendra Kumar, Aryabartta Sahu |
Online Scheduling of Applications on 3D Stacked Large Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: 15th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2014, Hong Kong, China, December 9-11, 2014, pp. 166-173, 2014, IEEE Computer Society, 978-1-4799-8334-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Flavius Gruian, Martin Schoeberl |
Hardware support for CSP on a Java chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 37(4-5), pp. 472-481, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Sanghoon Lee 0006, James Tuck 0001 |
Automatic parallelization of fine-grained metafunctions on a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 10(4), pp. 30:1-30:26, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Ismail Akturk, Ozcan Ozturk 0001 |
Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 29(2), pp. 177-184, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Luis Angel D. Bathen, Yongjin Ahn, Sudeep Pasricha, Nikil D. Dutt |
MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 12(1s), pp. 59:1-59:25, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Jiayin Li, Meikang Qiu, Jianwei Niu 0002, Laurence T. Yang, Yongxin Zhu 0001, Zhong Ming 0001 |
Thermal-aware task scheduling in 3D chip multiprocessor with real-time constrained workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 12(2), pp. 24:1-24:22, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Apan Qasem, Joshua Magee |
Improving TLB performance on current chip multiprocessor architectures through demand-driven superpaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Pract. Exp. ![In: Softw. Pract. Exp. 43(6), pp. 705-729, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Aditya Agrawal, Prabhat Jain, Amin Ansari, Josep Torrellas |
Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013, pp. 400-411, 2013, IEEE Computer Society, 978-1-4673-5585-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Nadeem, HeeJong Park 0001, Zhenmin Li, Morteza Biglari-Abhari, Zoran Salcic |
GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2013 - 26th International Conference, Prague, Czech Republic, February 19-22, 2013. Proceedings, pp. 147-158, 2013, Springer, 978-3-642-36423-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Tórur Biskopstø Strøm, Wolfgang Puffitsch, Martin Schoeberl |
Chip-multiprocessor hardware locks for safety-critical Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: The 11th International Workshop on Java Technologies for Real-time and Embedded Systems, JTRES '13, Karlsruhe, Germany, October 9-11, 2013, pp. 38-46, 2013, ACM, 978-1-4503-2166-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | David Kadjo, Hyungjun Kim, Paul Gratz, Jiang Hu, Raid Ayoub |
Power gating with block migration in chip-multiprocessor last-level caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013, pp. 93-99, 2013, IEEE Computer Society, 978-1-4799-2987-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Eustace Painkras |
A chip multiprocessor for a large-scale neural simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2013 |
RDF |
|
16 | Hammad Rashid, Clara Novoa, Mark McKenney, Apan Qasem |
Efficient parallel solutions to the integral knapsack problem on current chip-multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Emergent Distributed Syst. ![In: Int. J. Parallel Emergent Distributed Syst. 27(1), pp. 19-44, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | David Stevens, Vassilios A. Chouliaras, Vicente Azorin-Peris, Jia Zheng, Angelos Echiadis, Sijung Hu |
BioThreads: A Novel VLIW-Based Chip Multiprocessor for Accelerating Biomedical Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 6(3), pp. 257-268, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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