Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
27 | Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari |
Inductive Noise Reduction at the Architectural Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 162-167, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SIMD, superscalar, Clock-gating, Ground Bounce |
27 | Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske |
Low Power Design of FSMs by State Assignment and Disabling Self-Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 323-330, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
FSM synthesis, encoding constraints, low power design, clock gating, state assignment |
27 | Suresh Rajgopal |
Challenges in Low Power Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 329-330, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
power benchmarks, latch power, idle power, active power, clock enabling, max power, thermal power, transient power, low-power, clock gating, microprocessor design, di/dt |
26 | Saravanan Ramamoorthy, Haibo Wang 0005, Sarma B. K. Vrudhula |
A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 123-126, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low power, memory, circuit design, FIFO |
26 | Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita |
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier". ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 649-653, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Wanping Zhang, Ling Zhang, Rui Shi 0003, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng |
Fast power network analysis with multiple clock domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 456-463, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy 0001 |
Tolerance to Small Delay Defects by Adaptive Clock Stretching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 244-252, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen |
Pipelining technique for energy-aware datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1218-1221, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Glitch-free discretely programmable clock generation on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1839-1842, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Roger Su, Raman Mittal, Vivek Garg |
Synchronous Pipelined Relay Stations with Back-Pressure Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 517-520, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Claude Arm, Jean-Marc Masgonty, Christian Piguet |
Double-Latch Clocking Scheme for Low-Power I.P. Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 217-224, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi |
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 289-300, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Anmol Mathur, Qi Wang |
Power Reduction Techniques and Flows at RTL and System Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 28-29, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang 0010 |
Thermal modeling and management of DRAM memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 312-322, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
thermal management, thermal modeling, DRAM memories |
23 | Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee |
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 3-14, 2006, IEEE Computer Society, 0-7695-2732-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen |
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 444-447, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Nuri Alperen Kose, Razaq Jinad, Amar Rasheed, Narasimha Shashidhar, Mohamed Baza, Hani Alshahrani |
Detection of Malicious Threats Exploiting Clock-Gating Hardware Using Machine Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 24(3), pp. 983, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
23 | Gunjan Rajput, V. Logashree, Kunika Naresh Biyani, Santosh Kumar Vishvakarma |
Clock Gating-Based Effectual Realization of Stochastic Hyperbolic Tangent Function for Deep Neural Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(10), pp. 5978-6000, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Mangal Deep Gupta, Rajeev K. Chauhan, Sandeep Gulia |
Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG and Multistage LFSR with Clock Gating Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(3), pp. 2350039:1-2350039:24, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos |
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.12691, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Daniel Xing, Yuntao Liu 0001, Ankur Srivastava 0001 |
Low Power Logic Obfuscation Through System Level Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023, Vienna, Austria, August 7-8, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-1175-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Doyeon Won, Soomin Kim 0001, Taewhan Kim |
Machine Learning Driven Synthesis of Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023, Vienna, Austria, August 7-8, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-1175-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Sora Park, Taewhan Kim |
Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Chaehyun Kim, Taewhan Kim |
Maximizing Power Saving Through State-Driven Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 20th International SoC Design Conference, ISOCC 2023, Jeju, Republic of Korea, October 25-28, 2023, pp. 123-124, 2023, IEEE, 979-8-3503-2703-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Milos Krstic |
SET and SEU Hardened Clock Gating Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCIS ![In: 38th Conference on Design of Circuits and Integrated Systems, DCIS 2023, Málaga, Spain, November 15-17, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-0385-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos |
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 12th International Conference on Modern Circuits and Systems Technologies, MOCAST 2023, Athens, Greece, June 28-30, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2107-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo, Giuseppe Scotti |
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 99702-99708, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Oguz Meteer, Arvid B. Van Den Brink, Marco Jan Gerrit Bekooij |
Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 126-133, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Sora Park, Taewhan Kim |
Selective Clock Gating Based on Comprehensive Power Saving Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 230-231, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Kuruvilla John, R. S. Vinod Kumar, S. S. Kumar 0001 |
Low power pulsed flip-flop with clock gating and conditional pulse enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Autom. Control. ![In: Int. J. Autom. Control. 15(2), pp. 259-274, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | S. Prema, N. Karthikeyan, S. Karthik 0001 |
Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Medical Imaging Health Informatics ![In: J. Medical Imaging Health Informatics 11(12), pp. 3215-3222, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Yassine Attaoui, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, Aimad El Mourabit |
Clock Gating Efficiency and Impact on Power Optimization During Synthesis Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: International Conference on Microelectronics, ICM 2021, New Cairo City, Egypt, December 19-22, 2021, pp. 13-16, 2021, IEEE, 978-1-6654-0839-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Preethi, Mohan Govindsa Kabadi, K. Sudeendra Kumar, K. K. Mahapatra |
Low Power Sorters Using Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2021, Jaipur, India, December 18-22, 2021, pp. 6-11, 2021, IEEE, 978-1-7281-8753-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Chen Zhao, Yongshun Wang |
Clock gating circuit design based on data-driven improvements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EITCE ![In: EITCE 2021: 5th International Conference on Electronic Information Technology and Computer Engineering, Xiamen, China, October 22 - 24, 2021, pp. 54-58, 2021, ACM, 978-1-4503-8432-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | N. L. Venkataraman, Rajagopal Kumar 0001 |
An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Emerg. Telecommun. Technol. ![In: Trans. Emerg. Telecommun. Technol. 31(12), 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Lamjed Touil, Abdelaziz Hamdi, Ismail Gassoumi, Abdellatif Mtibaa |
Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electr. Comput. Eng. ![In: J. Electr. Comput. Eng. 2020, pp. 8108591:1-8108591:9, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Ramaian Subramanian Kamalakannan, Kuppusamy Venkatachalam |
Low power radiation aware transistor level design using tri-state inverter embedded non-clock gating technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(7), pp. 1063-1070, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Khushbu Chandrakar, Suchismita Roy |
A SAT-Based Methodology for Effective Clock Gating for Power Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(1), pp. 1950011:1-1950011:17, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Abhishek Nag, Subhajit Das 0004, Sambhu Nath Pradhan |
Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(5), pp. 1920003:1-1920003:20, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | M. Sharath, G. Poornima |
Design of Energy Efficient ALU Using Clock Gating for a Sensor Node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
REV ![In: Cyber-physical Systems and Digital Twins - Proceedings of the 16th International Conference on Remote Engineering and Virtual Instrumentation, REV 2019, Banglore, India, 3-6 February 2019, pp. 390-399, 2019, Springer, 978-3-030-23161-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Tae-Hyeong Kim, Dae-Jin Kim, Hyeon-Sam Shin, Sang-Ho Lee, Jae-Won Suh, Byung-Do Yang |
Low Power Digital PWM Buck Converter With a Clock-Gating Shift-Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2019, Auckland, New Zealand, January 22-25, 2019, pp. 1-3, 2019, IEEE, 978-89-950044-4-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Yonghwi Kwon 0002, Inhak Han, Youngsoo Shin |
Clock Gating Synthesis of Netlist with Cyclic Logic Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019, pp. 1-6, 2019, ACM, 9781728123509. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Gyoung-Hwan Hyun, Taewhan Kim |
Flip-flop State Driven Clock Gating: Concept, Design, and Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019, pp. 1-6, 2019, ACM, 9781728123509. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Tasnuva Noor, Emre Salman |
A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Ludovic Moreau, Rémi Dekimpe, David Bol |
A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do |
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 32nd IEEE International System-on-Chip Conference, SOCC 2019, Singapore, September 3-6, 2019, pp. 27-32, 2019, IEEE, 978-1-7281-3483-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Sabri Unsal, Adrián Cristal, Mateo Valero |
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(4), pp. 639-652, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | R. Udaiyakumar, Senoj Joseph, T. V. P. Sundararajan, Dhasarathan Vigneswaran, R. Maheswar 0001, Iraj S. Amiri |
Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 102(4), pp. 3477-3488, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Dhiraj Sarkar, Pritam Bhattacharjee, Alak Majumder |
Data-Dependent Clock Gating approach for Low Power Sequential System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1806.02271, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
23 | Pritam Bhattacharjee, Bipasha Nath, Alak Majumder |
LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1805.07409, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
23 | Giyoung Yang, Taewhan Kim |
Design and algorithm for clock gating and flip-flop co-optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, pp. 14, 2018, ACM, 978-1-4503-5950-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Doron Gluzer, Shmuel Wimer |
Probability-Driven Multibit Flip-Flop Integration With Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(3), pp. 1173-1177, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck |
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4), pp. 699-703, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Alireza Namazi, Meisam Abdollahi |
PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, pp. 323-328, 2017, IEEE Computer Society, 978-1-5386-2146-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Yu Liu 0028, Yingyezhe Jin, Peng Li 0001 |
Exploring sparsity of firing activities and clock gating for energy-efficient recurrent spiking neural processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-6023-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Liang Geng, Jizhong Shen, Congyuan Xu |
Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Inf. Technol. Electron. Eng. ![In: Frontiers Inf. Technol. Electron. Eng. 17(9), pp. 962-972, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Liang Geng, Jizhong Shen, Congyuan Xu |
Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 10(4), pp. 193-201, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Abhishek Nag, Sambhu Nath Pradhan |
An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 25(5), pp. 1650033:1-1650033:21, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Georgios Pouiklis, Georgios Ch. Sirakoulis |
Clock gating methodologies and tools: a survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 44(4), pp. 798-816, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Pritam Bhattacharjee, Alak Majumder, Tushar Dhabal Das |
A 90 nm leakage control transistor based clock gating for low power flip flop applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0916-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo |
Power and clock gating modelling in coarse grained reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the ACM International Conference on Computing Frontiers, CF'16, Como, Italy, May 16-19, 2016, pp. 384-391, 2016, ACM, 978-1-4503-4128-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero |
A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2016 International Symposium on Low Power Electronics and Design, ISLPED 2016, San Francisco Airport, CA, USA, August 08 - 10, 2016, pp. 362-367, 2016, ACM, 978-1-4503-4185-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin |
Register grouping for synthesis of clock gating logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: International Conference on IC Design and Technology, ICICDT 2016, Ho Chi Minh, Vietnam, June 27-29, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0827-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Youn Sung Park, Yaoyu Tao, Zhengya Zhang |
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(2), pp. 464-475, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Essam Elsayed, Hatem M. El-Boghdadi |
A novel power-efficient multi-operand digit-multiplier using reconfiguration and clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 71(7), pp. 2539-2564, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Mohsen Riahi Alam, Mostafa Ersali Salehi Nasab, Sied Mehdi Fakhraie |
Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12), pp. 1954-1963, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Joonhwan Yi, Jong-Gyu Kim |
Power modeling for digital circuits with clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 12(24), pp. 20150817, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Bao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris |
Constructing stability-based clock gating with hierarchical clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2015, Salvador, Brazil, September 1-4, 2015, pp. 97-102, 2015, IEEE, 978-1-4673-9419-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Vazgen Melikyan, Eduard Babayan, Anush Melikyan, Davit Babayan, Poghos Petrosyan, Edvard Mkrtchyan |
Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2015 IEEE East-West Design & Test Symposium, EWDTS 2015, Batumi, Georgia, September 26-29, 2015, pp. 1-4, 2015, IEEE Computer Society, 978-1-4673-7776-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Sungyoul Seo, Yong Lee 0002, Joohwan Lee, Sungho Kang 0001 |
A scan shifting method based on clock gating of multiple groups for low power scan testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 162-166, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa |
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 7, pp. 74-80, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Shmuel Wimer, Israel Koren |
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(4), pp. 771-778, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Inhak Han, Youngsoo Shin |
Simplifying Clock Gating Logic by Matching Factored Forms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(6), pp. 1338-1349, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Shmuel Wimer |
Easy and difficult exact covering problems arising in VLSI power reduction by clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Optim. ![In: Discret. Optim. 14, pp. 104-110, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta 0001 |
BTI-Gater: An Aging-Resilient Clock Gating Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 4(2), pp. 180-189, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Shmuel Wimer, Arye Albahari |
A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5), pp. 1465-1472, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Kwanyeob Chae, Saibal Mukhopadhyay |
Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 61-II(3), pp. 173-177, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Robert Najvirt, Andreas Steininger |
Equivalence of clock gating and synchronization with applicability to GALS communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014, pp. 1-8, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Maarten Boersma, Ulrike Schmidt 0002, Markus Kaltenbach |
Automatic detection of sticky clock gating equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2014, Böblingen, Germany, pp. 93-100, 2014, Cuvillier. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
23 | Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa |
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 6, pp. 101-111, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Aslam A. Rafi, T. R. Viswanathan 0001 |
Harmonic Rejection Mixing Techniques Using Clock-Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 48(8), pp. 1862-1874, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Jagrit Kathuria |
Low power clock gating techniques for synchronous buffer-based queue for 3D MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Syst. ![In: Int. J. Embed. Syst. 5(1/2), pp. 36-43, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Chih-Long Chang, Iris Hui-Ru Jiang |
Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2), pp. 242-246, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang 0002, Song-Bin Pan |
Low-power anti-aging zero skew clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 18(2), pp. 27:1-27:37, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Mohamed O. Shaker, Magdy A. Bayoumi |
Novel clock gating techniques for low power flip-flops and its applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 420-424, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Bao Le, Dipanjan Sengupta, Andreas G. Veneris |
Reviving erroneous stability-based clock-gating using partial Max-SAT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, pp. 717-722, 2013, IEEE, 978-1-4673-3029-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Youn Sung Park, Yaoyu Tao, Zhengya Zhang |
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, pp. 422-423, 2013, IEEE, 978-1-4673-4515-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Salim Farah, Magdy A. Bayoumi |
A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013, pp. 349-354, 2013, IEEE, 978-1-4799-1166-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa |
Suspicious timing error prediction with in-cycle clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013, pp. 335-340, 2013, IEEE, 978-1-4673-4951-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Zong-Han Yang, Tsung-Yi Ho |
Timing-aware clock gating of pulsed-latch circuits for low power design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-4435-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Kun-Han Tsai, Shuo Sheng |
Design rule check on the clock gating logic for testability and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2013 IEEE International Test Conference, ITC 2013, Anaheim, CA, USA, September 6-13, 2013, pp. 1-8, 2013, IEEE Computer Society, 978-1-4799-0859-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu |
Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013, pp. 80-85, 2013, IEEE Computer Society, 978-1-4673-4639-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Shih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li |
High-Level Synthesis for Minimum-Area Low-Power Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 28(5), pp. 971-988, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
23 | Ki-Sung Sohn, Da-In Han, Ki-Ju Baek, Nam-Soo Kim, Yeong-Seuk Kim |
Low Power Clock Gating for Shift Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 95-C(8), pp. 1447-1448, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Xin Man, Takashi Horiyama, Shinji Kimura |
Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(8), pp. 1347-1358, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin |
Clock Gating Synthesis of Pulsed-Latch Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7), pp. 1019-1030, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang |
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 17(2), pp. 16:1-16:15, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Ning Huang, En Zhu |
Scan power reduction based on clock-gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 9(12), pp. 1018-1022, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Emilia Noorsal, Kriangkrai Sooksood, Ulrich Bihr, Joachim Becker, Maurits Ortmanns |
Distributed clock gating for power reduction of a programmable waveform generator for neural stimulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMBC ![In: Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2012, San Diego, CA, USA, August 28 - September 1, 2012, pp. 3878-3881, 2012, IEEE, 978-1-4244-4119-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Kazuyuki Tanimura, Nikil D. Dutt |
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2012, part of ESWeek '12 Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012, pp. 453-462, 2012, ACM, 978-1-4503-1426-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|