Search results for "clock-gating"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari	Inductive Noise Reduction at the Architectural Level.	VLSI Design	2000	DBLP DOI BibTeX RDF	SIMD, superscalar, Clock-gating, Ground Bounce
27	Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske	Low Power Design of FSMs by State Assignment and Disabling Self-Loops.	EUROMICRO	1997	DBLP DOI BibTeX RDF	FSM synthesis, encoding constraints, low power design, clock gating, state assignment
27	Suresh Rajgopal	Challenges in Low Power Microprocessor Design.	VLSI Design	1996	DBLP DOI BibTeX RDF	power benchmarks, latch power, idle power, active power, clock enabling, max power, thermal power, transient power, low-power, clock gating, microprocessor design, di/dt
26	Saravanan Ramamoorthy, Haibo Wang 0005, Sarma B. K. Vrudhula	A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design.	ISQED	2008	DBLP DOI BibTeX RDF	low power, memory, circuit design, FIFO
26	Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita	Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier".	ASP-DAC	2007	DBLP DOI BibTeX RDF
26	Wanping Zhang, Ling Zhang, Rui Shi 0003, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng	Fast power network analysis with multiple clock domains.	ICCD	2007	DBLP DOI BibTeX RDF
26	Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy 0001	Tolerance to Small Delay Defects by Adaptive Clock Stretching.	IOLTS	2007	DBLP DOI BibTeX RDF
26	Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen	Pipelining technique for energy-aware datapaths.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
26	Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez	Glitch-free discretely programmable clock generation on chip.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
26	Roger Su, Raman Mittal, Vivek Garg	Synchronous Pipelined Relay Stations with Back-Pressure Tolerance.	IWSOC	2005	DBLP DOI BibTeX RDF
26	Claude Arm, Jean-Marc Masgonty, Christian Piguet	Double-Latch Clocking Scheme for Low-Power I.P. Cores.	PATMOS	2000	DBLP DOI BibTeX RDF
23	Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi	CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.	HPCA	2009	DBLP DOI BibTeX RDF
23	Anmol Mathur, Qi Wang	Power Reduction Techniques and Flows at RTL and System Level.	VLSI Design	2009	DBLP DOI BibTeX RDF
23	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang 0010	Thermal modeling and management of DRAM memory systems.	ISCA	2007	DBLP DOI BibTeX RDF	thermal management, thermal modeling, DRAM memories
23	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design.	MICRO	2006	DBLP DOI BibTeX RDF
23	Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen	Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
23	Nuri Alperen Kose, Razaq Jinad, Amar Rasheed, Narasimha Shashidhar, Mohamed Baza, Hani Alshahrani	Detection of Malicious Threats Exploiting Clock-Gating Hardware Using Machine Learning.	Sensors	2024	DBLP DOI BibTeX RDF
23	Gunjan Rajput, V. Logashree, Kunika Naresh Biyani, Santosh Kumar Vishvakarma	Clock Gating-Based Effectual Realization of Stochastic Hyperbolic Tangent Function for Deep Neural Hardware Accelerators.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
23	Mangal Deep Gupta, Rajeev K. Chauhan, Sandeep Gulia	Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG and Multistage LFSR with Clock Gating Network.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
23	Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos	Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.	CoRR	2023	DBLP DOI BibTeX RDF
23	Daniel Xing, Yuntao Liu 0001, Ankur Srivastava 0001	Low Power Logic Obfuscation Through System Level Clock Gating.	ISLPED	2023	DBLP DOI BibTeX RDF
23	Doyeon Won, Soomin Kim 0001, Taewhan Kim	Machine Learning Driven Synthesis of Clock Gating.	ISLPED	2023	DBLP DOI BibTeX RDF
23	Sora Park, Taewhan Kim	Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating.	ISCAS	2023	DBLP DOI BibTeX RDF
23	Chaehyun Kim, Taewhan Kim	Maximizing Power Saving Through State-Driven Clock Gating.	ISOCC	2023	DBLP DOI BibTeX RDF
23	Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Milos Krstic	SET and SEU Hardened Clock Gating Cell.	DCIS	2023	DBLP DOI BibTeX RDF
23	Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos	Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.	MOCAST	2023	DBLP DOI BibTeX RDF
23	Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo, Giuseppe Scotti	A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers.	IEEE Access	2022	DBLP DOI BibTeX RDF
23	Oguz Meteer, Arvid B. Van Den Brink, Marco Jan Gerrit Bekooij	Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating.	DSD	2022	DBLP DOI BibTeX RDF
23	Sora Park, Taewhan Kim	Selective Clock Gating Based on Comprehensive Power Saving Analysis.	ISCAS	2022	DBLP DOI BibTeX RDF
23	Kuruvilla John, R. S. Vinod Kumar, S. S. Kumar 0001	Low power pulsed flip-flop with clock gating and conditional pulse enhancement.	Int. J. Autom. Control.	2021	DBLP DOI BibTeX RDF
23	S. Prema, N. Karthikeyan, S. Karthik 0001	Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications.	J. Medical Imaging Health Informatics	2021	DBLP DOI BibTeX RDF
23	Yassine Attaoui, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, Aimad El Mourabit	Clock Gating Efficiency and Impact on Power Optimization During Synthesis Flow.	ICM	2021	DBLP DOI BibTeX RDF
23	Preethi, Mohan Govindsa Kabadi, K. Sudeendra Kumar, K. K. Mahapatra	Low Power Sorters Using Clock Gating.	iSES	2021	DBLP DOI BibTeX RDF
23	Chen Zhao, Yongshun Wang	Clock gating circuit design based on data-driven improvements.	EITCE	2021	DBLP DOI BibTeX RDF
23	N. L. Venkataraman, Rajagopal Kumar 0001	An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques.	Trans. Emerg. Telecommun. Technol.	2020	DBLP DOI BibTeX RDF
23	Lamjed Touil, Abdelaziz Hamdi, Ismail Gassoumi, Abdellatif Mtibaa	Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops.	J. Electr. Comput. Eng.	2020	DBLP DOI BibTeX RDF
23	Ramaian Subramanian Kamalakannan, Kuppusamy Venkatachalam	Low power radiation aware transistor level design using tri-state inverter embedded non-clock gating technique.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
23	Khushbu Chandrakar, Suchismita Roy	A SAT-Based Methodology for Effective Clock Gating for Power Minimization.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
23	Abhishek Nag, Subhajit Das 0004, Sambhu Nath Pradhan	Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
23	M. Sharath, G. Poornima	Design of Energy Efficient ALU Using Clock Gating for a Sensor Node.	REV	2019	DBLP DOI BibTeX RDF
23	Tae-Hyeong Kim, Dae-Jin Kim, Hyeon-Sam Shin, Sang-Ho Lee, Jae-Won Suh, Byung-Do Yang	Low Power Digital PWM Buck Converter With a Clock-Gating Shift-Register.	ICEIC	2019	DBLP DOI BibTeX RDF
23	Yonghwi Kwon 0002, Inhak Han, Youngsoo Shin	Clock Gating Synthesis of Netlist with Cyclic Logic Paths.	ICCAD	2019	DBLP DOI BibTeX RDF
23	Gyoung-Hwan Hyun, Taewhan Kim	Flip-flop State Driven Clock Gating: Concept, Design, and Methodology.	ICCAD	2019	DBLP DOI BibTeX RDF
23	Tasnuva Noor, Emre Salman	A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability.	ISCAS	2019	DBLP DOI BibTeX RDF
23	Ludovic Moreau, Rémi Dekimpe, David Bol	A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells.	ISCAS	2019	DBLP DOI BibTeX RDF
23	Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do	Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing.	SoCC	2019	DBLP DOI BibTeX RDF
23	Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Sabri Unsal, Adrián Cristal, Mateo Valero	Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
23	R. Udaiyakumar, Senoj Joseph, T. V. P. Sundararajan, Dhasarathan Vigneswaran, R. Maheswar 0001, Iraj S. Amiri	Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture.	Wirel. Pers. Commun.	2018	DBLP DOI BibTeX RDF
23	Dhiraj Sarkar, Pritam Bhattacharjee, Alak Majumder	Data-Dependent Clock Gating approach for Low Power Sequential System.	CoRR	2018	DBLP BibTeX RDF
23	Pritam Bhattacharjee, Bipasha Nath, Alak Majumder	LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications.	CoRR	2018	DBLP BibTeX RDF
23	Giyoung Yang, Taewhan Kim	Design and algorithm for clock gating and flip-flop co-optimization.	ICCAD	2018	DBLP DOI BibTeX RDF
23	Doron Gluzer, Shmuel Wimer	Probability-Driven Multibit Flip-Flop Integration With Clock Gating.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
23	Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck	Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
23	Alireza Namazi, Meisam Abdollahi	PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files.	DSD	2017	DBLP DOI BibTeX RDF
23	Yu Liu 0028, Yingyezhe Jin, Peng Li 0001	Exploring sparsity of firing activities and clock gating for energy-efficient recurrent spiking neural processors.	ISLPED	2017	DBLP DOI BibTeX RDF
23	Liang Geng, Jizhong Shen, Congyuan Xu	Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme.	Frontiers Inf. Technol. Electron. Eng.	2016	DBLP DOI BibTeX RDF
23	Liang Geng, Jizhong Shen, Congyuan Xu	Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications.	IET Comput. Digit. Tech.	2016	DBLP DOI BibTeX RDF
23	Abhishek Nag, Sambhu Nath Pradhan	An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF
23	Georgios Pouiklis, Georgios Ch. Sirakoulis	Clock gating methodologies and tools: a survey.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
23	Pritam Bhattacharjee, Alak Majumder, Tushar Dhabal Das	A 90 nm leakage control transistor based clock gating for low power flip flop applications.	MWSCAS	2016	DBLP DOI BibTeX RDF
23	Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo	Power and clock gating modelling in coarse grained reconfigurable systems.	Conf. Computing Frontiers	2016	DBLP DOI BibTeX RDF
23	Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero	A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.	ISLPED	2016	DBLP DOI BibTeX RDF
23	Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin	Register grouping for synthesis of clock gating logic.	ICICDT	2016	DBLP DOI BibTeX RDF
23	Youn Sung Park, Yaoyu Tao, Zhengya Zhang	A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
23	Essam Elsayed, Hatem M. El-Boghdadi	A novel power-efficient multi-operand digit-multiplier using reconfiguration and clock gating.	J. Supercomput.	2015	DBLP DOI BibTeX RDF
23	Mohsen Riahi Alam, Mostafa Ersali Salehi Nasab, Sied Mehdi Fakhraie	Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
23	Joonhwan Yi, Jong-Gyu Kim	Power modeling for digital circuits with clock gating.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
23	Bao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris	Constructing stability-based clock gating with hierarchical clustering.	PATMOS	2015	DBLP DOI BibTeX RDF
23	Vazgen Melikyan, Eduard Babayan, Anush Melikyan, Davit Babayan, Poghos Petrosyan, Edvard Mkrtchyan	Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor.	EWDTS	2015	DBLP DOI BibTeX RDF
23	Sungyoul Seo, Yong Lee 0002, Joohwan Lee, Sungho Kang 0001	A scan shifting method based on clock gating of multiple groups for low power scan testing.	ISQED	2015	DBLP DOI BibTeX RDF
23	Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa	Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating.	IPSJ Trans. Syst. LSI Des. Methodol.	2014	DBLP DOI BibTeX RDF
23	Shmuel Wimer, Israel Koren	Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
23	Inhak Han, Youngsoo Shin	Simplifying Clock Gating Logic by Matching Factored Forms.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
23	Shmuel Wimer	Easy and difficult exact covering problems arising in VLSI power reduction by clock gating.	Discret. Optim.	2014	DBLP DOI BibTeX RDF
23	Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta 0001	BTI-Gater: An Aging-Resilient Clock Gating Methodology.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2014	DBLP DOI BibTeX RDF
23	Shmuel Wimer, Arye Albahari	A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
23	Kwanyeob Chae, Saibal Mukhopadhyay	Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
23	Robert Najvirt, Andreas Steininger	Equivalence of clock gating and synchronization with applicability to GALS communication.	PATMOS	2014	DBLP DOI BibTeX RDF
23	Maarten Boersma, Ulrike Schmidt 0002, Markus Kaltenbach	Automatic detection of sticky clock gating equations.	MBMV	2014	DBLP BibTeX RDF
23	Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa	Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling.	IPSJ Trans. Syst. LSI Des. Methodol.	2013	DBLP DOI BibTeX RDF
23	Aslam A. Rafi, T. R. Viswanathan 0001	Harmonic Rejection Mixing Techniques Using Clock-Gating.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
23	Jagrit Kathuria	Low power clock gating techniques for synchronous buffer-based queue for 3D MPSoC.	Int. J. Embed. Syst.	2013	DBLP DOI BibTeX RDF
23	Chih-Long Chang, Iris Hui-Ru Jiang	Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
23	Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang 0002, Song-Bin Pan	Low-power anti-aging zero skew clock gating.	ACM Trans. Design Autom. Electr. Syst.	2013	DBLP DOI BibTeX RDF
23	Mohamed O. Shaker, Magdy A. Bayoumi	Novel clock gating techniques for low power flip-flops and its applications.	MWSCAS	2013	DBLP DOI BibTeX RDF
23	Bao Le, Dipanjan Sengupta, Andreas G. Veneris	Reviving erroneous stability-based clock-gating using partial Max-SAT.	ASP-DAC	2013	DBLP DOI BibTeX RDF
23	Youn Sung Park, Yaoyu Tao, Zhengya Zhang	A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating.	ISSCC	2013	DBLP DOI BibTeX RDF
23	Salim Farah, Magdy A. Bayoumi	A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic.	SoCC	2013	DBLP DOI BibTeX RDF
23	Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa	Suspicious timing error prediction with in-cycle clock gating.	ISQED	2013	DBLP DOI BibTeX RDF
23	Zong-Han Yang, Tsung-Yi Ho	Timing-aware clock gating of pulsed-latch circuits for low power design.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
23	Kun-Han Tsai, Shuo Sheng	Design rule check on the clock gating logic for testability and beyond.	ITC	2013	DBLP DOI BibTeX RDF
23	Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu	Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis.	VLSI Design	2013	DBLP DOI BibTeX RDF
23	Shih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li	High-Level Synthesis for Minimum-Area Low-Power Clock Gating.	J. Inf. Sci. Eng.	2012	DBLP BibTeX RDF
23	Ki-Sung Sohn, Da-In Han, Ki-Ju Baek, Nam-Soo Kim, Yeong-Seuk Kim	Low Power Clock Gating for Shift Register.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
23	Xin Man, Takashi Horiyama, Shinji Kimura	Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
23	Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin	Clock Gating Synthesis of Pulsed-Latch Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
23	Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang	Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
23	Ning Huang, En Zhu	Scan power reduction based on clock-gating.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
23	Emilia Noorsal, Kriangkrai Sooksood, Ulrich Bihr, Joachim Becker, Maurits Ortmanns	Distributed clock gating for power reduction of a programmable waveform generator for neural stimulation.	EMBC	2012	DBLP DOI BibTeX RDF
23	Kazuyuki Tanimura, Nikil D. Dutt	LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks.	CODES+ISSS	2012	DBLP DOI BibTeX RDF