Search results for "flip-flops"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
52	Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski	Using a software testing technique to identify registers for partial scan implementation.	SBCCI	2006	DBLP DOI BibTeX RDF	hardware testing, testability improvement, hardware description language, automatic test generation, partial scan design
52	Qiushuang Zhang, Ian G. Harris	Partial BIST insertion to eliminate data correlation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
52	Seongmoon Wang, Srimat T. Chakradhar	A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.	ITC	2003	DBLP DOI BibTeX RDF
52	Qingwei Wu, Michael S. Hsiao	Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal.	ITC	2003	DBLP DOI BibTeX RDF
52	Irith Pomeranz, Sudhakar M. Reddy	On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains.	ICCD	2002	DBLP DOI BibTeX RDF
52	Qiushuang Zhang, Ian G. Harris	Partial BIST insertion to eliminate data correlation.	ICCAD	1999	DBLP DOI BibTeX RDF
52	Irith Pomeranz, Sudhakar M. Reddy	PASTA: Partial Scan to Enhance Test Compaction.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
52	Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel	Partial Scan Selection Based on Dynamic Reachability and Observability Information.	VLSI Design	1998	DBLP DOI BibTeX RDF	test generation, DFT, partial scan
52	Hsing-Chung Liang, Chung-Len Lee 0001, Jwu E. Chen	Identifying invalid states for sequential circuit test generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
52	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis of Sequential Circuits by Redundancy Removal and Retiming.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	synthesis of sequential circuits, sequentially redundant fault, retiming, redundant fault, redundancy removal
52	Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng	A Test Synthesis Approach to Reducing BALLAST DFT Overhead.	DAC	1997	DBLP DOI BibTeX RDF
52	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
52	Jaehong Park, M. Ray Mercer	Using Functional Information and Strategy Switching in Sequential ATPG.	ICCD	1996	DBLP DOI BibTeX RDF
52	Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia	Pseudo-exhaustive built-in TPG for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
50	Håvard Pedersen Alstad, Snorre Aunet	Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology.	DDECS	2008	DBLP DOI BibTeX RDF
50	S. H. Rasouli, Amir Amirabadi, A. Seyedi, Ali Afzali-Kusha	Double edge triggered Feedback Flip-Flop in sub 100NM technology.	ASP-DAC	2006	DBLP DOI BibTeX RDF
50	Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic	Level conversion for dual-supply systems.	ISLPED	2003	DBLP DOI BibTeX RDF	level conversion, flip-flop, dual-supply voltage
50	Li Ding 0002, Pinaki Mazumder, N. Srinivas	A dual-rail static edge-triggered latch.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
50	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng	An almost full-scan BIST solution-higher fault coverage and shorter test application time.	ITC	1998	DBLP DOI BibTeX RDF
50	Arun Balakrishnan, Srimat T. Chakradhar	Peripheral Partitioning and Tree Decomposition for Partial Scan.	VLSI Design	1998	DBLP DOI BibTeX RDF
49	Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi	Low-Power High-Speed 180-nm CMOS Clock Drivers.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.640 ns, CMOS clock drivers, register array, delay flip-flops, 251 muW, CMOS technology, power dissipation, delay time, 0.18 micron
49	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
49	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel	Automatic test generation using genetically-engineered distinguishing sequences.	VTS	1996	DBLP DOI BibTeX RDF	two-phase algorithm, fault effects, DIGATE, genetic algorithms, genetic algorithm, fault diagnosis, logic testing, sequential circuits, sequential circuit, automatic testing, sequences, flip-flops, automatic test generation, distinguishing sequence
49	Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Scan insertion criteria for low design impact.	VTS	1996	DBLP DOI BibTeX RDF	scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
49	A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha	Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology.	ISVLSI	2006	DBLP DOI BibTeX RDF
49	A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha	Low power low leakage clock gated static pulsed flip-flop.	ISCAS	2006	DBLP DOI BibTeX RDF
47	Karthik Duraisami, Enrico Macii, Massimo Poncino	Using soft-edge flip-flops to compensate NBTI-induced delay degradation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	device aging, seff, setup and hold time, flip-flop, circuit reliability, nbti
47	Sherif A. Tawfik, Volkan Kursun	Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations.	ISQED	2008	DBLP DOI BibTeX RDF
47	Antonio Zenteno Ramírez, Guillermo Espinosa, Víctor H. Champac	Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
47	Wai Chung, Timothy Lo, Manoj Sachdev	A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
47	Yannick Bonhomme, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	Power Driven Chaining of Flip-Flops in Scan Architectures.	ITC	2002	DBLP DOI BibTeX RDF
47	Tomasz Garbolino, Andrzej Hlawiczka	A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits.	EDCC	1999	DBLP DOI BibTeX RDF
47	Samy Makar, Edward J. McCluskey	ATPG for scan chain latches and flip-flops.	VTS	1997	DBLP DOI BibTeX RDF	bistable element, scan chain circuit, combinational defect detection, algorithm, ATPG, automatic test pattern generation, automatic testing, stuck-at fault, flip-flop, latch, checking experiment
47	Toshinobu Ono	Selecting partial scan flip-flops for circuit partitioning.	ICCAD	1994	DBLP DOI BibTeX RDF
42	Yibo Chen, Yuan Xie 0001	Tolerating process variations in high-level synthesis using transparent latches.	ASP-DAC	2009	DBLP DOI BibTeX RDF
42	Boxue Yin, Dong Xiang, Zhen Chen	New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets.	VLSI Design	2009	DBLP DOI BibTeX RDF
42	Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang	Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop.	ISCAS	2006	DBLP DOI BibTeX RDF
42	Kambiz Rahimi, Chris Diorio	In-Circuit Self-Tuning of Clock Latencies.	ISQED	2005	DBLP DOI BibTeX RDF
42	Dong Xiang, Janak H. Patel	Partial Scan Design Based on Circuit State Information and Functional Analysis.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Valid state, invalid state, testability improvement potential, conflict, testability measure, partial scan design
42	Pradeep Varma, Ashutosh Chakraborty	Low-Voltage, Double-Edge-Triggered Flip Flop.	PATMOS	2003	DBLP DOI BibTeX RDF
42	Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu	A cost-effective scan architecture for scan testing with non-scan test power and test application cost.	DAC	2003	DBLP DOI BibTeX RDF
42	Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj	Estimation of state line statistics in sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	signal statistics, transition density, finite-state machine, sequential circuit, Power estimation, switching activity, signal probability
42	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen	Verifying sequential equivalence using ATPG techniques.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF
42	Dong Xiang, Yi Xu	A Multiple Phase Partial Scan Design Method.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
42	Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou	A high-performance low-power static differential double edge-triggered flip-flop.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
42	Huy Nguyen 0001, Rabindra K. Roy, Abhijit Chatterjee	Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	sequential circuit BIST, built0in self-test, fault propagation analysis, BIST, partial reset
42	Lukasz Surdej, Leslaw Gniewek	Fuzzy Hold Flip-Flop and Flip-Flops Hardware Realizations.	Int. J. Fuzzy Syst.	2018	DBLP DOI BibTeX RDF
41	Chul Soo Kim, Joo-Seong Kim, Bai-Sun Kong, Yongsam Moon, Young-Hyun Jun	Presetting pulse-based flip-flop.	ISCAS	2008	DBLP DOI BibTeX RDF
41	Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra	A novel high-speed sense-amplifier-based flip-flop.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
41	Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao	Flip-Flop and Repeater Insertion for Early Interconnect Planning.	DATE	2002	DBLP DOI BibTeX RDF
41	Mark Vesterbacka	A robust differential scan flip-flop.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
35	Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang	Buffer/flip-flop block planning for power-integrity-driven floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
35	Min-Lun Chuang, Chun-Yao Wang	Synthesis of reversible sequential elements.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	sequential elements, sequential circuits, Reversible logic
35	Mohammad Ghasemazar, Massoud Pedram	Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing.	ICCAD	2008	DBLP DOI BibTeX RDF
35	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Optimization technique for flip-flop inserted global interconnect.	ISCAS	2008	DBLP DOI BibTeX RDF
35	Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding	Scan chain clustering for test power reduction.	DAC	2008	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
35	Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull	DVFS in loop accelerators using BLADES.	DAC	2008	DBLP DOI BibTeX RDF	embedded systems, low power, high-level synthesis, voltage scaling, frequency scaling
35	Dong Xiang, Mingjing Chen, Hideo Fujiwara	Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Random testability, scan enable signal, weighted random testing, scan-based BIST
35	Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara	Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Scan forest, test application cost, test data volume, test power
35	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining.	DATE	2007	DBLP DOI BibTeX RDF
35	Himanshu Thapliyal, A. Prasad Vinod 0001	Design of Reversible Sequential Elements With Feasibility of Transistor Implementation.	ISCAS	2007	DBLP DOI BibTeX RDF
35	Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi	High Level Synthesis of Degradable ASICs Using Virtual Binding.	VTS	2007	DBLP DOI BibTeX RDF
35	Kedarnath J. Balakrishnan, Lei Fang	RTL Test Point Insertion to Reduce Delay Test Volume.	VTS	2007	DBLP DOI BibTeX RDF
35	Suresh Kumar Devanathan, Michael L. Bushnell	Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST.	VLSI Design	2007	DBLP DOI BibTeX RDF
35	Haihua Yan, Adit D. Singh	A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI).	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
35	Kambiz Rahimi, Chris Diorio	Design and Application of Adaptive Delay Sequential Elements.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
35	Sriparna Saha 0001, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta	Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI.	ICIT	2006	DBLP DOI BibTeX RDF	balanced partitioning, low power clock trees in nanometer chips, genetic algorithm, cluster analysis, Multiobjective optimization
35	Man Chung Hon	Spec-based flip-flop and latch repeater planning.	ASP-DAC	2006	DBLP DOI BibTeX RDF
35	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	ISLPED	2006	DBLP DOI BibTeX RDF	intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
35	Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya	An Efficient Scan Tree Design for Compact Test Pattern Set.	VLSI Design	2006	DBLP DOI BibTeX RDF
35	Chuan Lin 0002, Hai Zhou 0001	Wire retiming as fixpoint computation.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
35	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy 0001	Low-power scan design using first-level supply gating.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
35	Mario R. Casu, Luca Macchiarulo	Throughput-driven floorplanning with wire pipelining.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
35	Shih Ping Lin 0001, Chung-Len Lee 0001, Jwu E. Chen	A Scan Matrix Design for Low Power Scan-Based Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
35	Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori	Low-Power Design of 90-nm SuperH Processor Core.	ICCD	2005	DBLP DOI BibTeX RDF
35	Saurabh Goyal, Mihir R. Choudhury, S. S. S. P. Rao, L. Kalyan Kumar	Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF
35	Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar	Microarchitecture-aware floorplanning using a statistical design of experiments approach.	DAC	2005	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, wire pipelining
35	Chuan Lin 0002, Hai Zhou 0001	Wire Retiming for System-on-Chip by Fixpoint Computation.	DATE	2004	DBLP DOI BibTeX RDF
35	Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam 0001	Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic.	DSD	2004	DBLP DOI BibTeX RDF
35	Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy	Multiple Scan Tree Design with Test Vector Modification.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
35	Jiann-Chyi Rau, Ching-Hsiu Lin, Jun-Yi Chang	An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
35	V. Seth, Min Zhao 0001, Jiang Hu	Exploiting level sensitive latches in wire pipelining.	ICCAD	2004	DBLP DOI BibTeX RDF
35	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita	On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.	DELTA	2004	DBLP DOI BibTeX RDF
35	Yajun Ran, Malgorzata Marek-Sadowska	On designing via-configurable cell blocks for regular fabrics.	DAC	2004	DBLP DOI BibTeX RDF	via configurable, layout, regular fabric
35	Irith Pomeranz, Sudhakar M. Reddy	Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
35	Ranganathan Sankaralingam, Nur A. Touba	Reducing Test Power During Test Using Programmable Scan Chain Disable.	DELTA	2002	DBLP DOI BibTeX RDF
35	Ramesh C. Tekumalla, Premachandran R. Menon	Identification of primitive faults in combinational and sequentialcircuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
35	Ondrej Novák, Jiri Nosek	Test-per-Clock Testing of the Circuits with Scan.	IOLTW	2001	DBLP DOI BibTeX RDF
35	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell	Path delay fault simulation of sequential circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
35	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer	AQUILA: An Equivalence Checking System for Large Sequential Designs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	state exploration, formal verification, Design verification, equivalence checking
35	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III	Integrated parametric timing optimization of digital systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
35	Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik	On improving test quality of scan-based BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
35	Christer Svensson, Atila Alvandpour	Low power and low voltage CMOS digital circuit techniques.	ISLPED	1998	DBLP DOI BibTeX RDF	low power, CMOS, digital circuits, low voltage
35	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero	A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Initialization sequence, Genetic Algorithm, ATPG
35	Irith Pomeranz, Sudhakar M. Reddy	On the Detection of Reset Faults in Synchronous Sequential Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF
35	Shang-E Tai, Debashis Bhattacharya	A three-stage partial scan design method to ease ATPG.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	minimum feed back vertex set, design for testability, partial scan design
35	Hsing-Chung Liang, Chung-Len Lee 0001, Jwu E. Chen	Identifying Untestable Faults in Sequential Circuits.	IEEE Des. Test Comput.	1995	DBLP DOI BibTeX RDF	initializable, invalid states, controllability, test generation, untestable faults
35	Vivek Chickermane, Jaushin Lee, Janak H. Patel	Addressing design for testability at the architectural level.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
33	Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	CMOS logic devices, reliability, Markov process, monte carlo method, poisson distribution, laplace transform
33	Rubil Ahmadi	A Hold Friendly Flip-Flop For Area Recovery.	ISCAS	2007	DBLP DOI BibTeX RDF