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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5390 occurrences of 2060 keywords
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Results
Found 21101 publication records. Showing 21101 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
31 | Suchendra M. Bhandarkar, Hamid R. Arabnia |
Parallel Computer Vision on a Reconfigurable Multiprocessor Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(3), pp. 292-309, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Reconfigurable multiring network, computer vision, parallel algorithms, image processing, parallel processing, distributed algorithms, distributed processing, reconfigurable architectures, scalable architectures |
31 | Itsuo Takanami, Tadayoshi Horita |
A built-in self-reconfigurable scheme for 3D mesh arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 458-464, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures |
31 | Steven M. P. Yip, Nicholas Bambos |
Scalable routing schemes for massively parallel processing using reconfigurable optical interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 500-, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
scalable routing schemes, reconfigurable optical interconnect, message broadcasting, massively parallel processing system, randomly generated packets, device capabilities, parallel processing, reconfigurable architectures, optical interconnections, message routing, massively parallel processing |
31 | Mounir Hamdi, Yi Pan 0001 |
Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 440-446, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations |
31 | Nikolaos Gaitanis, Panagiotis Kostarakis, Antonis M. Paschalis |
Totally Self Checking reconfigurable duplication system with separate internal fault indication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 316-321, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
decision circuits, totally self checking system, reconfigurable duplication system, separate internal fault indication, single cell fault model, functional self checking units, decision circuit, indication outputs, nonstop repair, fault diagnosis, logic testing, built-in self test, redundancy, redundancy, reconfigurable architectures, switching circuits, error indication |
31 | Patrick W. Dowd, James A. Perreault, John C. Chu, David C. Hoffmeister, Dan Crouse |
LIGHTNING: A Scalable Dynamically Reconfigurable Hierarchical WDM Network for High-Performance Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 4th International Symposium on High Performance Distributed Computing (HPDC '95), Washington, DC, USA, August 2-4, 1995., pp. 220-229, 1995, IEEE Computer Society, 0-8186-7088-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
scalable dynamically reconfigurable hierarchical WDM network, high-performance clustering, supercomputer interconnection, optical network testbed, distributed shared memory environment, single-hop all-optical communication, n-level hierarchy, highly fault tolerant system behavior, memory interface, optical devices, scalability, parallel processing, reconfigurable architectures, system architecture, wavelength division multiplexing, wavelength division multiplexing, optical interconnections, optical information processing, LIGHTNING, traffic intensities |
31 | Hussein M. Alnuweiri |
Constant-Time Parallel Algorithms for Image Labeling on a Reconfigurable Network of Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(3), pp. 320-326, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
constant-time parallel algorithms, reconfigurable network of processors, minimum-labeled PE, timecomplexity, parallel algorithms, computational complexity, image recognition, reconfigurable architectures, multiprocessorinterconnection networks, image labeling |
30 | Ronald G. Dreslinski, David Fick, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge |
Reconfigurable Multicore Server Processors for Low Power Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 247-254, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Server Architectures, Low Power, Reconfigurable |
30 | Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin |
Automatic bus macro placement for partially reconfigurable FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 269-272, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
emips, reconfigurable computing, dynamic partial reconfiguration, floor-planning |
30 | Yanxia Shen, Tai Li, Zhicheng Ji |
Research on the Reconfigurable Implementation of Neural Network Controller Based on FPGA for DC-DC Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part II, pp. 1152-1159, 2009, Springer, 978-3-642-01509-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Reconfigurable design, Neural network, Hardware implementation, FPGA implementation |
30 | Yuzhong Jiao, Xin'an Wang, Xuewen Ni |
A Fully Data-Driven Reconfigurable Architecture with Very Coarse-Grained Execution Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Infoscale ![In: Scalable Information Systems, 4th International ICST Conference, Infoscale 2009, Hong Kong, June 10-11, 2009, Revised Selected Papers, pp. 1-13, 2009, Springer, 978-3-642-10484-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Processing element (PE), Execution unit (EU), Very-coarse-grained, Fully-data-driven, Reconfigurable architecture |
30 | Sebastian Lange, Martin Middendorf |
Design Aspects of Multi-level Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(1), pp. 23-37, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multi-level reconfiguration, dynamic reconfiguration, reconfigurable architecture |
30 | Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala |
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 297-306, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
coarse-grain array, DSP, Reconfigurable systems |
30 | John H. Kelm, Steven S. Lumetta |
HybridOS: runtime support for reconfigurable accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 212-221, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CPU/accelerator architecture, operating system, reconfigurable computing |
30 | Yanhui Wei, Dexin Xu, Yanbin Gao, Jie Zhao 0003, Hegao Cai |
Dynamical Research Based on a New Type of Reconfigurable Robot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIRA (2) ![In: Intelligent Robotics and Applications, First International Conference, ICIRA 2008, Wuhan, China, October 15-17, 2008 Proceedings, Part II, pp. 1056-1065, 2008, Springer, 978-3-540-88516-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Dynamical, Modular robots, Reconfigurable robots |
30 | Alessio Montone, Marco D. Santambrogio, Donatella Sciuto |
A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 450-453, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Area Constraints, Dynamic Reconfigurable System |
30 | Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede |
Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2n). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(9), pp. 1269-1282, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
arithmetic and logic units, Multiprocessor systems, public key cryptosystems, reconfigurable hardware, processor architectures |
30 | Manman Peng, Jiaguang Sun, Yuming Wang |
A Phase-Based Self-Tuning Algorithm for Reconfigurable Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDS ![In: First International Conference on the Digital Society (ICDS 2007), 2-6 January 2007, Guadeloupe, French Caribbean, pp. 27, 2007, IEEE Computer Society, 978-0-7695-2760-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable cache, self-tuning algorithm, low energy, program phase |
30 | Xuegong Zhou, Liang Liang, Ying Wang 0032, Chenglian Peng |
Online Task Scheduling for Heterogeneous Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD (Selected Papers) ![In: Computer Supported Cooperative Work in Design IV, 11th International Conference, CSCWD 2007, Melbourne, Australia, April 26-28, 2007. Revised Selected Papers, pp. 596-607, 2007, Springer, 978-3-540-92718-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Hybrid Task, Scheduling, FPGA, Reconfigurable System |
30 | Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes 0001 |
Infrastructure for dynamic reconfigurable systems: choices and trade-offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 44-49, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
reconfigurable architectures, NoCs, configuration controllers |
30 | Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek |
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 310-315, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable architecture (CGRA), context pipelining, temporal mapping, low power, system-on-chip (SoC), loop pipelining, configuration cache, spatial mapping |
30 | Haibin Shen, Rongquan You, Yier Jin, Aiming Ji |
Interconnect Estimation for Mesh-Based Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 766-775, 2006, Springer, 3-540-36679-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
mesh-based, probability, Interconnect, reconfigurable computing |
30 | Atsushi Kawai, Toshiyuki Fukushige |
Gordon Bell finalists II - $158/GFLOPS astrophysical N-body simulation with reconfigurable add-in card and hierarchical tree algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 48, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cosmological simulation, many-body simulation, tree algorithm, reconfigurable processor |
30 | Yanqiong Fei, Xifang Zhao |
Modules Classification and Automatic Generation of Kinematics on Self-reconfigurable Modular Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 43(2-4), pp. 147-159, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
modules, kinematics, self-reconfigurable |
30 | Sangjin Hong, Shu-Shin Chin |
Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(2), pp. 239-259, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, FFT, DCT, reconfigurable architecture, digital filtering, FIR |
30 | Youngsun Han, Seon Kim, Chulwoo Kim |
Jaguar: A Compiler Infrastructure for Java Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, Proceedings, pp. 386-397, 2005, Springer, 3-540-30881-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Java, FPGA, compiler, Reconfigurable computing, Verilog |
30 | Yuan-Hsiu Chen, Pao-Ann Hsiung |
Hardware Task Scheduling and Placement in Operating Systems for Dynamically Reconfigurable SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 489-498, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Operating System for Reconfigurable SoC, Hardware Scheduling, Placement, Dynamic Partial Reconfiguration |
30 | Chih-Hao Tseng, Pao-Ann Hsiung |
UML-Based Design Flow and Partitioning Methodology for Dynamically Reconfigurable Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 479-488, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, UML, partitioning, reconfigurable computing, codesign, sequence diagram, design flow |
30 | Gerard K. Rauwerda, Paul M. Heysters, Gerard J. M. Smit |
Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 30(3), pp. 263-282, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
heterogeneous reconfigurable architecture, MONTIUM, wireless communication algorithms, adaptivity, System-on-Chip (SoC), Software Defined Radio (SDR) |
30 | Zhi Guo, Betul Buyukkurt, Walid A. Najjar |
Input data reuse in compiling window operations onto reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 249-256, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
reuse analysis, compilation, high-level synthesis, VHDL, reconfigurable computing |
30 | Katherine Compton, Scott Hauck |
Flexibility measurement of domain-specific reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 155-161, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
programmable hardware, flexibility, reconfigurable hardware |
30 | Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, Gerhard Tröster |
The case for reconfigurable hardware in wearable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pers. Ubiquitous Comput. ![In: Pers. Ubiquitous Comput. 7(5), pp. 299-308, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Body area computing system, Field-programmable gate arrays, Embedded systems, Wearable computing, Reconfigurable hardware |
30 | Stefan Janson, Daniel Merkle, Martin Middendorf, Hossam A. ElGindy, Hartmut Schmeck |
On Enforced Convergence of ACO and its Implementation on the Reconfigurable Mesh Architecture Using Size Reduction Tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 26(3), pp. 221-238, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scheduling, ant colony optimization, run-time reconfigurability, reconfigurable mesh |
30 | John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, David Lim |
Automated tools to implement and test Internet systems in reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Commun. Rev. ![In: Comput. Commun. Rev. 33(3), pp. 103-110, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
network intrusion detection and prevention, Internet, Field Programmable Gate Array (FPGA), networks, tools, firewall, reconfigurable hardware |
30 | Jose Antonio Boluda, Fernando Pardo |
A reconfigurable architecture for autonomous visual-navigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Vis. Appl. ![In: Mach. Vis. Appl. 13(5), pp. 322-331, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Log-polar vision, Differential algorithms, Reconfigurable architectures, Autonomous systems, Visual navigation |
30 | Behzad Mohebbi, Eliseu Chavez Filho, Rafael Maestre, Mark Davies, Fadi J. Kurdahi |
A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 103-108, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
reconfigurable computing, software-defined radio |
30 | Sebastian Wallner |
A Reconfigurable Multi-threaded Architecture Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 193-207, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Computation Threads, Hardware Virtualization, Datapath Processor, Pipelining, Reconfigurable Architectures |
30 | Sandeep Koranne |
A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 415-434, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
embedded core based test scheduling, reconfigurable wrapper, parallel scheduling of malleable tasks, system-on-chip test, VLSI test |
30 | Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh |
Instruction generation for hybrid reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 605-627, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, high-level synthesis, reconfigurable computing |
30 | Daler N. Rakhmatov, Sarma B. K. Vrudhula |
Hardware-software bipartitioning for dynamically reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 145-150, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
network flows, reconfigurable systems, hardware-software partitioning |
30 | Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano |
Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 38-43, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
high level and architectural synthesis, reconfigurable computing |
30 | Eduardo Augusto Bezerra, Fabian Vargas 0001, Michael Paul Gough |
Improving Reconfigurable Systems Reliability by Combining Periodical Test and Redundancy Techniques: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(2), pp. 163-174, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
programmable-logic-array and space applications, fault tolerance, test, reconfigurable computing |
30 | David Caliga, David Peter Barker |
Delivering acceleration: the potential for increased HPC application performance using reconfigurable logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the 2001 ACM/IEEE conference on Supercomputing, Denver, CO, USA, November 10-16, 2001, CD-ROM, pp. 32, 2001, ACM, 1-58113-293-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGA, reconfigurable computing |
30 | Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh |
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 573-578, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
scheduling, SIMD, MPEG-2, automatic target recognition, dynamic configuration, reconfigurable processors |
30 | Andrew A. Chien, Jay H. Byun |
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 209-221, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Multiprocess Protection, Process isolation, Machine Virtualization, Adaptive Computing, Reconfigurable Processor |
30 | Markus Weinhardt, Wayne Luk |
Pipeline Vectorization for Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 52-62, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
hardware pipelines, FPGAs, reconfigurable computing, vectorization, loop transformations |
30 | Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh |
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 38-, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
3-D floorplanning, Reconfigurable computing, floorplanning |
30 | Jacir Luiz Bordim, Tomoo Watanabe, Koji Nakano, Tatsuya Hayashi |
A Tool for Algorithm Visualization on the Reconfigurable Mesh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99), 23-25 June 1999, Fremantle, Australia, pp. 406-413, 1999, IEEE Computer Society, 0-7695-0231-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Parallel Algorithms, Algorithm Animation, Reconfigurable Mesh |
30 | Alexandre F. Tenca, Milos D. Ercegovac |
A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 216-225, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
long-precision, computer arithmetic, reconfigurable architecture |
30 | Koji Nakano, Stephan Olariu |
An Optimal Algorithm for the Angle-Restricted All Nearest Neighbor Problem on the Reconfigurable Mesh, with Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(9), pp. 983-990, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
proximity problems, ARANN, mobile computing, ANN, lower bounds, Reconfigurable mesh |
30 | Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya |
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Fifth International Workshop on Hardware/Software Codesign, CODES/CASHE 1997, March 24-26, 1997, Braunschweig, Germany, pp. 147-151, 1997, IEEE Computer Society, 0-8186-7895-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
hardware/software co-operation, a computer architecture using FPGA, bus-based reconfigurable co-processor architecture, high-level synthesis and optimization, C compiler to hardware modules |
30 | Ju-wook Jang, Heonchul Park, Viktor K. Prasanna |
A Fast Algorithm for Computing a Histogram on Reconfigurable Mesh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 17(2), pp. 97-106, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
parallel algorithm, mapping, Histogram, reconfigurable mesh |
30 | Biing-Feng Wang, Gen-Huey Chen |
Constant Time Algorithms for the Transitive Closure and Some Related Graph Problems on Processor Arrays with Reconfigurable Bus Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(4), pp. 500-507, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
related graph problems, reconfigurable bus systems, parallel algorithms, graph theory, minimum spanning trees, bipartite graphs, transitive closure, transitive closure, connected components, processor arrays, undirected graph, bridges, biconnected components, graph problems, articulation points |
30 | Shinichi Kato, Minoru Watanabe |
Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 139-148, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Dawei Wang 0020, Sikun Li, Yong Dou |
Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 679-684, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Deepak Sreedharan, Ali Akoglu |
A hybrid processing element based reconfigurable architecture for hashing algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Yong-Sheng Yin, Gaoming Du, Yu-Kun Song |
Study on the Multi-pipeline Reconfigurable Computing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (4) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 4: Embedded Programming / Database Technology / Neural Networks and Applications / Other Applications, December 12-14, 2008, Wuhan, China, pp. 122-125, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Florian Thoma, Matthias Kühnle, Philippe Bonnot 0001, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker 0001 |
MORPHEUS: Heterogeneous Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 409-414, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Sikun Li, Dawei Wang 0020, Tun Li, Yong Dou |
Distributed Collaborative Partition Method of Reconfigurable SoC Using Ant Colony Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD ![In: Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, CSCWD 2007, April 26-28, 2007, Melbourne, Australia, pp. 133-138, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Koji Nakano |
Randomized Initialization on the 1-Dimensional Reconfigurable Mesh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), 3-6 December 2007, Adelaide, Australia, pp. 293-300, 2007, IEEE Computer Society, 0-7695-3049-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Reiner W. Hartenstein |
The Neumann Syndrome calls for a revolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPRCTA ![In: Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications, HPRCTA 2007,held in conjunction with SC07, Reno, Nevada, USA, November 11, 2007, 2007, ACM Press, 978-1-59593-894-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Behnam Salemi, Mark Moll, Wei-Min Shen |
SUPERBOT: A Deployable, Multi-Functional, and Modular Self-Reconfigurable Robotic System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2006, October 9-15, 2006, Beijing, China, pp. 3636-3641, 2006, IEEE, 1-4244-0258-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Sajid Baloch, Tughrul Arslan, Adrian Stoica |
An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis |
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Guy Gogniat, Tilman Wolf, Wayne P. Burleson |
Reconfigurable Security Support for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), CD-ROM / Abstracts Proceedings, 4-7 January 2006, Kauai, HI, USA, 2006, IEEE Computer Society, 0-7695-2507-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Marisa Llorens, Javier Oliver 0001 |
Marked-Controlled Reconfigurable Workflow Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYNASC ![In: 8th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC 2006), 26-29 September 2006, Timisoara, Romania, pp. 407-413, 2006, IEEE Computer Society, 0-7695-2740-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Wenyin Fu, Katherine Compton |
An execution environment for reconfigurable computing (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 267, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Timothy O'Sullivan, Richard Studdert |
Agent technology and reconfigurable computing for mobile devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), Santa Fe, New Mexico, USA, March 13-17, 2005, pp. 963-969, 2005, ACM, 1-58113-964-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Jawad Khan, Ranga Vemuri |
Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson |
An EHW Architecture for the Design of Unconstrained Low-Power FIR Filters for Sensor Control Using Custom-Reconfigurable Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June - 1 July 2005, Washington, DC, USA, pp. 147-153, 2005, IEEE Computer Society, 0-7695-2399-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Christoph Steiger, Herbert Walder, Marco Platzner |
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(11), pp. 1393-1407, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, real-time, operating system, partial reconfiguration, online scheduling |
30 | Marisa Llorens, Javier Oliver 0001 |
Structural and Dynamic Changes in Concurrent Systems: Reconfigurable Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(9), pp. 1147-1158, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Juanjo Noguera, Rosa M. Badia |
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(2), pp. 385-406, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Adaptable architectures and microarchitectures, runtime support for dynamic reconfiguration, dynamic scheduling |
30 | Miljan Vuletic, Laura Pozzi, Paolo Ienne |
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 596-605, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Brian F. Veale, John K. Antonio, Monte P. Tull |
Code Re-ordering for a Class of Reconfigurable Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1170, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Ingrid Verbauwhede, Patrick Schaumont |
The happy marriage of architecture and application in next-generation reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 363-376, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
real-time systems, embedded |
30 | Guangzhi Li, Dongmei Wang, Jennifer Yates, Robert D. Doverspike, Charles R. Kalmanek |
Detailed Study of IP/ Reconfigurable Optical Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BROADNETS ![In: 1st International Conference on Broadband Networks (BROADNETS 2004), 25-29 October 2004, San Jose, CA, USA, pp. 64-73, 2004, IEEE Computer Society, 0-7695-2221-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins |
Designing an Operating System for a Heterogeneous Reconfigurable So. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 174, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Saburo Matunaga, Ryuichi Hodoshima, Hideto Okada, Naoki Miyashita, Nobumasa Yamaguchi |
Ground experiment system of reconfigurable robot satellites. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: Seventh International Conference on Control, Automation, Robotics and Vision, ICARCV 2002, Singapore, 2-5 December 2002, Proceedings, pp. 57-62, 2002, IEEE, 981-04-8364-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Reiner W. Hartenstein |
Reconfigurable Computing: A New Business Model and its Impact on SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 103-111, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Grant B. Wigley, David A. Kearney |
The First Real Operating System for Reconfigurable Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 6th Australasian Computer Systems Architecture Conference (ACSAC 2001), 29-30 January 2001, Gold Coast, Queensland, Australia, pp. 130-137, 2001, IEEE Computer Society, 0-7695-0954-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Yi Pan 0001 |
Constant-Time Hough Transform on a 3D Reconfigurable Mesh Using Fewer Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 966-973, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Juanjo Noguera, Rosa M. Badia |
Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000., pp. 100-106, 2000, ACM / IEEE Computer Society, 0-7695-0765-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Jose Antonio Boluda, Fernando Pardo, Francisco Blasco, Joan Pelechano |
A Pipelined Reconfigurable Architecture for Visual-Based Navigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1071-1074, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Ju-wook Jang, Madhusudan Nigam, Viktor K. Prasanna, Sartaj Sahni |
Constant Time Algorithms for Computational Geometry on the Reconfigurable Mesh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(1), pp. 1-12, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
30 | J. C. Cogolludo, Sanguthevar Rajasekaran |
Permutation Routing on Reconfigurable Meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISAAC ![In: Algorithms and Computation, 4th International Symposium, ISAAC '93, Hong Kong, December 15-17, 1993, Proceedings, pp. 157-166, 1993, Springer, 3-540-57568-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
30 | Roy M. Jenevein, James C. Browne |
A control processor for a reconfigurable array computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 9th International Symposium on Computer Architecture (ISCA 1982), Austin, TX, USA, April 26-29, 1982, pp. 81-89, 1982, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP BibTeX RDF |
|
29 | Brian Holland, Karthik Nagarajan, Alan D. George |
RAT: RC Amenability Test for Rapid Performance Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(4), pp. 22:1-22:31, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
formulation methodology, strategic design methodology, FPGA, reconfigurable computing, performance prediction |
29 | Andreas Dandalis, Viktor K. Prasanna |
An adaptive cryptographic engine for internet protocol security architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(3), pp. 333-353, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
performance tradeoffs, reconfigurable components, cryptography, reconfigurable computing, AES, configurable, high performance, IPSec, reconfigurable systems, Adaptive computing |
29 | Andreas Dandalis, Viktor K. Prasanna |
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 547-562, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable components, reconfigurable computing, configurable, high performance, Boolean satisfiability, reconfigurable systems, Adaptive computing, performance trade-offs |
29 | Edwin Hsing-Mean Sha, Kenneth Steiglitz |
Reconfigurability and Reliability of Systolic/Wavefront Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(7), pp. 854-862, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
wavefront arrays, fault-tolerant redundant structures, reliable arrays, application graph, finitely reconfigurable, locally reconfigurable, reliability, lower bound, fault tolerant computing, reconfigurability, time complexity, systolic arrays, systolic arrays, reconfigurable architectures, dynamic graphs, bounded-degree graphs |
29 | Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte |
The MOLEN Polymorphic Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(11), pp. 1363-1375, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Custom computing machines, reconfigurable microcode, polymorphic processors, FPGA, reconfigurable processors, firmware |
29 | Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger |
A Partitioning Programming Environment for a Novel Parallel Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 544-548, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
partitioning programming environment, novel parallel architecture, embedded accelerator, reconfigurable datapath hardware, accelerator partitioning, profiling-driven partitioning, resource-driven sequential partitioning, resource-driven structural partitioning, parallel architectures, software tools, programming environments, reconfigurable architectures, software performance evaluation, parallelizing compiler, performance optimization, program interpreters, parallelising compilers, parallelizing programming environment, optimising compilers, C programs |
29 | John Schewel, Michael Thornburg, Steve Casselman |
Transformable computers & hardware object technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 518-522, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain |
28 | Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner 0001, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker 0001 |
Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Systems ![In: Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications., pp. 245-267, 2010, Springer, 978-9-04-813484-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich |
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Systems ![In: Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications., pp. 51-71, 2010, Springer, 978-9-04-813484-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Heiko Hinkelmann, Peter Zipf, Manfred Glesner |
Dynamically Reconfigurable Systems for Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Systems ![In: Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications., pp. 315-334, 2010, Springer, 978-9-04-813484-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Andreas Schallenberg, Wolfgang Nebel, Andreas Herrholz, Philipp A. Hartmann, Kim Grüttner, Frank Oppenheimer |
PolyDyn - Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Systems ![In: Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications., pp. 139-158, 2010, Springer, 978-9-04-813484-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen |
ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Systems ![In: Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications., pp. 199-221, 2010, Springer, 978-9-04-813484-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf |
FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Systems ![In: Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications., pp. 355-374, 2010, Springer, 978-9-04-813484-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
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