Search results for "reconfigurable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Suchendra M. Bhandarkar, Hamid R. Arabnia	Parallel Computer Vision on a Reconfigurable Multiprocessor Network.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Reconfigurable multiring network, computer vision, parallel algorithms, image processing, parallel processing, distributed algorithms, distributed processing, reconfigurable architectures, scalable architectures
31	Itsuo Takanami, Tadayoshi Horita	A built-in self-reconfigurable scheme for 3D mesh arrays.	ISPAN	1997	DBLP DOI BibTeX RDF	fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures
31	Steven M. P. Yip, Nicholas Bambos	Scalable routing schemes for massively parallel processing using reconfigurable optical interconnect.	ICPADS	1996	DBLP DOI BibTeX RDF	scalable routing schemes, reconfigurable optical interconnect, message broadcasting, massively parallel processing system, randomly generated packets, device capabilities, parallel processing, reconfigurable architectures, optical interconnections, message routing, massively parallel processing
31	Mounir Hamdi, Yi Pan 0001	Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses.	ISPAN	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations
31	Nikolaos Gaitanis, Panagiotis Kostarakis, Antonis M. Paschalis	Totally Self Checking reconfigurable duplication system with separate internal fault indication.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	decision circuits, totally self checking system, reconfigurable duplication system, separate internal fault indication, single cell fault model, functional self checking units, decision circuit, indication outputs, nonstop repair, fault diagnosis, logic testing, built-in self test, redundancy, redundancy, reconfigurable architectures, switching circuits, error indication
31	Patrick W. Dowd, James A. Perreault, John C. Chu, David C. Hoffmeister, Dan Crouse	LIGHTNING: A Scalable Dynamically Reconfigurable Hierarchical WDM Network for High-Performance Clustering.	HPDC	1995	DBLP DOI BibTeX RDF	scalable dynamically reconfigurable hierarchical WDM network, high-performance clustering, supercomputer interconnection, optical network testbed, distributed shared memory environment, single-hop all-optical communication, n-level hierarchy, highly fault tolerant system behavior, memory interface, optical devices, scalability, parallel processing, reconfigurable architectures, system architecture, wavelength division multiplexing, wavelength division multiplexing, optical interconnections, optical information processing, LIGHTNING, traffic intensities
31	Hussein M. Alnuweiri	Constant-Time Parallel Algorithms for Image Labeling on a Reconfigurable Network of Processors.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	constant-time parallel algorithms, reconfigurable network of processors, minimum-labeled PE, timecomplexity, parallel algorithms, computational complexity, image recognition, reconfigurable architectures, multiprocessorinterconnection networks, image labeling
30	Ronald G. Dreslinski, David Fick, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge	Reconfigurable Multicore Server Processors for Low Power Operation.	SAMOS	2009	DBLP DOI BibTeX RDF	Server Architectures, Low Power, Reconfigurable
30	Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin	Automatic bus macro placement for partially reconfigurable FPGA designs.	FPGA	2009	DBLP DOI BibTeX RDF	emips, reconfigurable computing, dynamic partial reconfiguration, floor-planning
30	Yanxia Shen, Tai Li, Zhicheng Ji	Research on the Reconfigurable Implementation of Neural Network Controller Based on FPGA for DC-DC Converters.	ISNN (2)	2009	DBLP DOI BibTeX RDF	Reconfigurable design, Neural network, Hardware implementation, FPGA implementation
30	Yuzhong Jiao, Xin'an Wang, Xuewen Ni	A Fully Data-Driven Reconfigurable Architecture with Very Coarse-Grained Execution Units.	Infoscale	2009	DBLP DOI BibTeX RDF	Processing element (PE), Execution unit (EU), Very-coarse-grained, Fully-data-driven, Reconfigurable architecture
30	Sebastian Lange, Martin Middendorf	Design Aspects of Multi-level Reconfigurable Architectures.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	multi-level reconfiguration, dynamic reconfiguration, reconfigurable architecture
30	Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala	Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.	PATMOS	2008	DBLP DOI BibTeX RDF	coarse-grain array, DSP, Reconfigurable systems
30	John H. Kelm, Steven S. Lumetta	HybridOS: runtime support for reconfigurable accelerators.	FPGA	2008	DBLP DOI BibTeX RDF	CPU/accelerator architecture, operating system, reconfigurable computing
30	Yanhui Wei, Dexin Xu, Yanbin Gao, Jie Zhao 0003, Hegao Cai	Dynamical Research Based on a New Type of Reconfigurable Robot.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	Dynamical, Modular robots, Reconfigurable robots
30	Alessio Montone, Marco D. Santambrogio, Donatella Sciuto	A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems.	DELTA	2008	DBLP DOI BibTeX RDF	Area Constraints, Dynamic Reconfigurable System
30	Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2n).	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	arithmetic and logic units, Multiprocessor systems, public key cryptosystems, reconfigurable hardware, processor architectures
30	Manman Peng, Jiaguang Sun, Yuming Wang	A Phase-Based Self-Tuning Algorithm for Reconfigurable Cache.	ICDS	2007	DBLP DOI BibTeX RDF	reconfigurable cache, self-tuning algorithm, low energy, program phase
30	Xuegong Zhou, Liang Liang, Ying Wang 0032, Chenglian Peng	Online Task Scheduling for Heterogeneous Reconfigurable Systems.	CSCWD (Selected Papers)	2007	DBLP DOI BibTeX RDF	Hybrid Task, Scheduling, FPGA, Reconfigurable System
30	Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes 0001	Infrastructure for dynamic reconfigurable systems: choices and trade-offs.	SBCCI	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, NoCs, configuration controllers
30	Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek	Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture.	ISLPED	2006	DBLP DOI BibTeX RDF	coarse-grained reconfigurable architecture (CGRA), context pipelining, temporal mapping, low power, system-on-chip (SoC), loop pipelining, configuration cache, spatial mapping
30	Haibin Shen, Rongquan You, Yier Jin, Aiming Ji	Interconnect Estimation for Mesh-Based Reconfigurable Computing.	EUC	2006	DBLP DOI BibTeX RDF	mesh-based, probability, Interconnect, reconfigurable computing
30	Atsushi Kawai, Toshiyuki Fukushige	Gordon Bell finalists II - $158/GFLOPS astrophysical N-body simulation with reconfigurable add-in card and hierarchical tree algorithm.	SC	2006	DBLP DOI BibTeX RDF	cosmological simulation, many-body simulation, tree algorithm, reconfigurable processor
30	Yanqiong Fei, Xifang Zhao	Modules Classification and Automatic Generation of Kinematics on Self-reconfigurable Modular Machines.	J. Intell. Robotic Syst.	2005	DBLP DOI BibTeX RDF	modules, kinematics, self-reconfigurable
30	Sangjin Hong, Shu-Shin Chin	Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	low power, FFT, DCT, reconfigurable architecture, digital filtering, FIR
30	Youngsun Han, Seon Kim, Chulwoo Kim	Jaguar: A Compiler Infrastructure for Java Reconfigurable Computing.	ICESS	2005	DBLP DOI BibTeX RDF	Java, FPGA, compiler, Reconfigurable computing, Verilog
30	Yuan-Hsiu Chen, Pao-Ann Hsiung	Hardware Task Scheduling and Placement in Operating Systems for Dynamically Reconfigurable SoC.	EUC	2005	DBLP DOI BibTeX RDF	Operating System for Reconfigurable SoC, Hardware Scheduling, Placement, Dynamic Partial Reconfiguration
30	Chih-Hao Tseng, Pao-Ann Hsiung	UML-Based Design Flow and Partitioning Methodology for Dynamically Reconfigurable Computing Systems.	EUC	2005	DBLP DOI BibTeX RDF	FPGA, UML, partitioning, reconfigurable computing, codesign, sequence diagram, design flow
30	Gerard K. Rauwerda, Paul M. Heysters, Gerard J. M. Smit	Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	heterogeneous reconfigurable architecture, MONTIUM, wireless communication algorithms, adaptivity, System-on-Chip (SoC), Software Defined Radio (SDR)
30	Zhi Guo, Betul Buyukkurt, Walid A. Najjar	Input data reuse in compiling window operations onto reconfigurable hardware.	LCTES	2004	DBLP DOI BibTeX RDF	reuse analysis, compilation, high-level synthesis, VHDL, reconfigurable computing
30	Katherine Compton, Scott Hauck	Flexibility measurement of domain-specific reconfigurable hardware.	FPGA	2004	DBLP DOI BibTeX RDF	programmable hardware, flexibility, reconfigurable hardware
30	Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, Gerhard Tröster	The case for reconfigurable hardware in wearable computing.	Pers. Ubiquitous Comput.	2003	DBLP DOI BibTeX RDF	Body area computing system, Field-programmable gate arrays, Embedded systems, Wearable computing, Reconfigurable hardware
30	Stefan Janson, Daniel Merkle, Martin Middendorf, Hossam A. ElGindy, Hartmut Schmeck	On Enforced Convergence of ACO and its Implementation on the Reconfigurable Mesh Architecture Using Size Reduction Tasks.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	scheduling, ant colony optimization, run-time reconfigurability, reconfigurable mesh
30	John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, David Lim	Automated tools to implement and test Internet systems in reconfigurable hardware.	Comput. Commun. Rev.	2003	DBLP DOI BibTeX RDF	network intrusion detection and prevention, Internet, Field Programmable Gate Array (FPGA), networks, tools, firewall, reconfigurable hardware
30	Jose Antonio Boluda, Fernando Pardo	A reconfigurable architecture for autonomous visual-navigation.	Mach. Vis. Appl.	2003	DBLP DOI BibTeX RDF	Log-polar vision, Differential algorithms, Reconfigurable architectures, Autonomous systems, Visual navigation
30	Behzad Mohebbi, Eliseu Chavez Filho, Rafael Maestre, Mark Davies, Fadi J. Kurdahi	A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	reconfigurable computing, software-defined radio
30	Sebastian Wallner	A Reconfigurable Multi-threaded Architecture Model.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF	Computation Threads, Hardware Virtualization, Datapath Processor, Pipelining, Reconfigurable Architectures
30	Sandeep Koranne	A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	embedded core based test scheduling, reconfigurable wrapper, parallel scheduling of malleable tasks, system-on-chip test, VLSI test
30	Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh	Instruction generation for hybrid reconfigurable systems.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, high-level synthesis, reconfigurable computing
30	Daler N. Rakhmatov, Sarma B. K. Vrudhula	Hardware-software bipartitioning for dynamically reconfigurable systems.	CODES	2002	DBLP DOI BibTeX RDF	network flows, reconfigurable systems, hardware-software partitioning
30	Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano	Datapath Merging and Interconnection Sharing for Reconfigurable Architectures.	ISSS	2002	DBLP DOI BibTeX RDF	high level and architectural synthesis, reconfigurable computing
30	Eduardo Augusto Bezerra, Fabian Vargas 0001, Michael Paul Gough	Improving Reconfigurable Systems Reliability by Combining Periodical Test and Redundancy Techniques: A Case Study.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	programmable-logic-array and space applications, fault tolerance, test, reconfigurable computing
30	David Caliga, David Peter Barker	Delivering acceleration: the potential for increased HPC application performance using reconfigurable logic.	SC	2001	DBLP DOI BibTeX RDF	FPGA, reconfigurable computing
30	Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh	MorphoSys: case study of a reconfigurable computing system targeting multimedia applications.	DAC	2000	DBLP DOI BibTeX RDF	scheduling, SIMD, MPEG-2, automatic target recognition, dynamic configuration, reconfigurable processors
30	Andrew A. Chien, Jay H. Byun	Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor.	FCCM	1999	DBLP DOI BibTeX RDF	Multiprocess Protection, Process isolation, Machine Virtualization, Adaptive Computing, Reconfigurable Processor
30	Markus Weinhardt, Wayne Luk	Pipeline Vectorization for Reconfigurable Systems.	FCCM	1999	DBLP DOI BibTeX RDF	hardware pipelines, FPGAs, reconfigurable computing, vectorization, loop transformations
30	Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh	3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	3-D floorplanning, Reconfigurable computing, floorplanning
30	Jacir Luiz Bordim, Tomoo Watanabe, Koji Nakano, Tatsuya Hayashi	A Tool for Algorithm Visualization on the Reconfigurable Mesh.	ISPAN	1999	DBLP DOI BibTeX RDF	Parallel Algorithms, Algorithm Animation, Reconfigurable Mesh
30	Alexandre F. Tenca, Milos D. Ercegovac	A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures.	FCCM	1998	DBLP DOI BibTeX RDF	long-precision, computer arithmetic, reconfigurable architecture
30	Koji Nakano, Stephan Olariu	An Optimal Algorithm for the Angle-Restricted All Nearest Neighbor Problem on the Reconfigurable Mesh, with Applications.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	proximity problems, ARANN, mobile computing, ANN, lower bounds, Reconfigurable mesh
30	Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya	A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor.	CODES	1997	DBLP DOI BibTeX RDF	hardware/software co-operation, a computer architecture using FPGA, bus-based reconfigurable co-processor architecture, high-level synthesis and optimization, C compiler to hardware modules
30	Ju-wook Jang, Heonchul Park, Viktor K. Prasanna	A Fast Algorithm for Computing a Histogram on Reconfigurable Mesh.	IEEE Trans. Pattern Anal. Mach. Intell.	1995	DBLP DOI BibTeX RDF	parallel algorithm, mapping, Histogram, reconfigurable mesh
30	Biing-Feng Wang, Gen-Huey Chen	Constant Time Algorithms for the Transitive Closure and Some Related Graph Problems on Processor Arrays with Reconfigurable Bus Systems.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	related graph problems, reconfigurable bus systems, parallel algorithms, graph theory, minimum spanning trees, bipartite graphs, transitive closure, transitive closure, connected components, processor arrays, undirected graph, bridges, biconnected components, graph problems, articulation points
30	Shinichi Kato, Minoru Watanabe	Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI.	SAMOS	2009	DBLP DOI BibTeX RDF
30	Dawei Wang 0020, Sikun Li, Yong Dou	Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization.	ASP-DAC	2008	DBLP DOI BibTeX RDF
30	Deepak Sreedharan, Ali Akoglu	A hybrid processing element based reconfigurable architecture for hashing algorithms.	IPDPS	2008	DBLP DOI BibTeX RDF
30	Yong-Sheng Yin, Gaoming Du, Yu-Kun Song	Study on the Multi-pipeline Reconfigurable Computing System.	CSSE (4)	2008	DBLP DOI BibTeX RDF
30	Florian Thoma, Matthias Kühnle, Philippe Bonnot 0001, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker 0001	MORPHEUS: Heterogeneous Reconfigurable Computing.	FPL	2007	DBLP DOI BibTeX RDF
30	Sikun Li, Dawei Wang 0020, Tun Li, Yong Dou	Distributed Collaborative Partition Method of Reconfigurable SoC Using Ant Colony Optimization.	CSCWD	2007	DBLP DOI BibTeX RDF
30	Koji Nakano	Randomized Initialization on the 1-Dimensional Reconfigurable Mesh.	PDCAT	2007	DBLP DOI BibTeX RDF
30	Reiner W. Hartenstein	The Neumann Syndrome calls for a revolution.	HPRCTA	2007	DBLP DOI BibTeX RDF
30	Behnam Salemi, Mark Moll, Wei-Min Shen	SUPERBOT: A Deployable, Multi-Functional, and Modular Self-Reconfigurable Robotic System.	IROS	2006	DBLP DOI BibTeX RDF
30	Sajid Baloch, Tughrul Arslan, Adrian Stoica	An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures.	FPL	2006	DBLP DOI BibTeX RDF
30	Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis	Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware.	IPDPS	2006	DBLP DOI BibTeX RDF
30	Guy Gogniat, Tilman Wolf, Wayne P. Burleson	Reconfigurable Security Support for Embedded Systems.	HICSS	2006	DBLP DOI BibTeX RDF
30	Marisa Llorens, Javier Oliver 0001	Marked-Controlled Reconfigurable Workflow Nets.	SYNASC	2006	DBLP DOI BibTeX RDF
30	Wenyin Fu, Katherine Compton	An execution environment for reconfigurable computing (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
30	Timothy O'Sullivan, Richard Studdert	Agent technology and reconfigurable computing for mobile devices.	SAC	2005	DBLP DOI BibTeX RDF
30	Jawad Khan, Ranga Vemuri	Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units.	IPDPS	2005	DBLP DOI BibTeX RDF
30	Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson	An EHW Architecture for the Design of Unconstrained Low-Power FIR Filters for Sensor Control Using Custom-Reconfigurable Technology.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
30	Christoph Steiger, Herbert Walder, Marco Platzner	Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	FPGA, real-time, operating system, partial reconfiguration, online scheduling
30	Marisa Llorens, Javier Oliver 0001	Structural and Dynamic Changes in Concurrent Systems: Reconfigurable Petri Nets.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
30	Juanjo Noguera, Rosa M. Badia	Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	Adaptable architectures and microarchitectures, runtime support for dynamic reconfiguration, dynamic scheduling
30	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.	FPL	2004	DBLP DOI BibTeX RDF
30	Brian F. Veale, John K. Antonio, Monte P. Tull	Code Re-ordering for a Class of Reconfigurable Microprocessors.	FPL	2004	DBLP DOI BibTeX RDF
30	Ingrid Verbauwhede, Patrick Schaumont	The happy marriage of architecture and application in next-generation reconfigurable systems.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	real-time systems, embedded
30	Guangzhi Li, Dongmei Wang, Jennifer Yates, Robert D. Doverspike, Charles R. Kalmanek	Detailed Study of IP/ Reconfigurable Optical Networks.	BROADNETS	2004	DBLP DOI BibTeX RDF
30	Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins	Designing an Operating System for a Heterogeneous Reconfigurable So.	IPDPS	2003	DBLP DOI BibTeX RDF
30	Saburo Matunaga, Ryuichi Hodoshima, Hideto Okada, Naoki Miyashita, Nobumasa Yamaguchi	Ground experiment system of reconfigurable robot satellites.	ICARCV	2002	DBLP DOI BibTeX RDF
30	Reiner W. Hartenstein	Reconfigurable Computing: A New Business Model and its Impact on SoC Design.	DSD	2001	DBLP DOI BibTeX RDF
30	Grant B. Wigley, David A. Kearney	The First Real Operating System for Reconfigurable Computers.	ACSAC	2001	DBLP DOI BibTeX RDF
30	Yi Pan 0001	Constant-Time Hough Transform on a 3D Reconfigurable Mesh Using Fewer Processors.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
30	Juanjo Noguera, Rosa M. Badia	Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures.	ISSS	2000	DBLP DOI BibTeX RDF
30	Jose Antonio Boluda, Fernando Pardo, Francisco Blasco, Joan Pelechano	A Pipelined Reconfigurable Architecture for Visual-Based Navigation.	EUROMICRO	1999	DBLP DOI BibTeX RDF
30	Ju-wook Jang, Madhusudan Nigam, Viktor K. Prasanna, Sartaj Sahni	Constant Time Algorithms for Computational Geometry on the Reconfigurable Mesh.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF
30	J. C. Cogolludo, Sanguthevar Rajasekaran	Permutation Routing on Reconfigurable Meshes.	ISAAC	1993	DBLP DOI BibTeX RDF
30	Roy M. Jenevein, James C. Browne	A control processor for a reconfigurable array computer.	ISCA	1982	DBLP BibTeX RDF
29	Brian Holland, Karthik Nagarajan, Alan D. George	RAT: RC Amenability Test for Rapid Performance Prediction.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	formulation methodology, strategic design methodology, FPGA, reconfigurable computing, performance prediction
29	Andreas Dandalis, Viktor K. Prasanna	An adaptive cryptographic engine for internet protocol security architectures.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	performance tradeoffs, reconfigurable components, cryptography, reconfigurable computing, AES, configurable, high performance, IPSec, reconfigurable systems, Adaptive computing
29	Andreas Dandalis, Viktor K. Prasanna	Run-time performance optimization of an FPGA-based deduction engine for SAT solvers.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	reconfigurable components, reconfigurable computing, configurable, high performance, Boolean satisfiability, reconfigurable systems, Adaptive computing, performance trade-offs
29	Edwin Hsing-Mean Sha, Kenneth Steiglitz	Reconfigurability and Reliability of Systolic/Wavefront Arrays.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	wavefront arrays, fault-tolerant redundant structures, reliable arrays, application graph, finitely reconfigurable, locally reconfigurable, reliability, lower bound, fault tolerant computing, reconfigurability, time complexity, systolic arrays, systolic arrays, reconfigurable architectures, dynamic graphs, bounded-degree graphs
29	Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte	The MOLEN Polymorphic Processor.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Custom computing machines, reconfigurable microcode, polymorphic processors, FPGA, reconfigurable processors, firmware
29	Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger	A Partitioning Programming Environment for a Novel Parallel Architecture.	IPPS	1996	DBLP DOI BibTeX RDF	partitioning programming environment, novel parallel architecture, embedded accelerator, reconfigurable datapath hardware, accelerator partitioning, profiling-driven partitioning, resource-driven sequential partitioning, resource-driven structural partitioning, parallel architectures, software tools, programming environments, reconfigurable architectures, software performance evaluation, parallelizing compiler, performance optimization, program interpreters, parallelising compilers, parallelizing programming environment, optimising compilers, C programs
29	John Schewel, Michael Thornburg, Steve Casselman	Transformable computers & hardware object technology.	IPPS	1995	DBLP DOI BibTeX RDF	transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain
28	Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner 0001, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker 0001	Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich	Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Heiko Hinkelmann, Peter Zipf, Manfred Glesner	Dynamically Reconfigurable Systems for Wireless Sensor Networks.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Andreas Schallenberg, Wolfgang Nebel, Andreas Herrholz, Philipp A. Hartmann, Kim Grüttner, Frank Oppenheimer	PolyDyn - Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen	ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
28	Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf	FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF