Search results for "switch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Guy G. Lemieux, David M. Lewis	Analytical Framework for Switch Block Design.	FPL	2002	DBLP DOI BibTeX RDF
39	Tao Lin 0003, Scott F. Midkiff, Jahng S. Park	A Dynamic Topology Switch for the Emulation of Wireless Mobile Ad Hoc Networks.	LCN	2002	DBLP DOI BibTeX RDF	MANET routing protocols, wireless networks, Wireless ad hoc networks, network simulation, network emulation
39	Driss Benhaddou, Ala I. Al-Fuqaha, Ghulam M. Chaudhry	New Multiprotocol WDM/CDMA-Based Optical Switch Architecture.	Annual Simulation Symposium	2001	DBLP DOI BibTeX RDF
39	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures
39	Thomas E. Anderson, Susan S. Owicki, James B. Saxe, Charles P. Thacker	High Speed Switch Scheduling for Local Area Networks.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF	iterative matching, statistical matching, ATM networks, switching scheduling
38	Dengyuan Xu	A Novel Scheduling Algorithm Based on Buffered Crossbar Switch Fabric in EPFTS Switch.	CSSE (3)	2008	DBLP DOI BibTeX RDF
38	Qiaoyan Yu, Paul Ampadu	Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment.	DFT	2008	DBLP DOI BibTeX RDF
38	Dawei Wang, Zheng Cao, Xinchun Liu, Ninghui Sun	HPP Switch: A Novel High Performance Switch for HPC.	Hot Interconnects	2008	DBLP DOI BibTeX RDF
38	Young-Keun Park, Gyungho Lee	ATM cell scheduling with queue length-based priority scheme.	ICCCN	1995	DBLP DOI BibTeX RDF	ATM cell scheduling, queue length based priority scheme, nonblocking switch, optimal input bypass queueing method, switch throughput maximisation, cell delay variations, delay variance, cell loss rate, neural network, asynchronous transfer mode, asynchronous transfer mode, ATM switches, buffer size, B-ISDN, FIFO queueing, nonuniform traffic, head-of-line blocking, input queues, cell loss probabilities
37	Afshin Shiravi, Paul S. Min, Yoon G. Kim	Traffic Dispatching Algorithm in Three-Stage Switch.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF	three-stage switch, sequence preserving, load balancing, Packet switch
37	Keun-Bae Kim, Hyup Jong Kim	Back-Pressure Buffering Scheme to Improve the Cell Loss Property on the Output Buffered ATM Switch.	LCN	1996	DBLP DOI BibTeX RDF	back-pressure buffering, cell loss property, output buffered ATM switch, input cells, push-out mechanism, selective pressure mechanism, small sized memory, asynchronous transfer mode, shared memory, queueing theory, simulation results, computer simulation, performance comparison, FIFO, switch fabric, output buffer
37	Aditya Agrawal, Magdy A. Bayoumi, Amr Elchouemi	A new ATM congestion control scheme for shared buffer switch architectures.	ICCCN	1995	DBLP DOI BibTeX RDF	pre-emptive congestion control scheme, shared buffer switch architectures, rate-based feedback scheme, guaranteed service traffic, continuous bit-rate traffic, leaky bucket mechanism, backward explicit congestion notification feedback scheme, mean inter-arrival time, buffer threshold throttle factor, cell reject throttle factor, rate reduction delta, transient behaviour, filter time, asynchronous transfer mode, ATM networks, simulation model, ATM switch, dynamic bandwidth allocation, best-effort traffic, variable bit-rate traffic, predictive scheme
37	Peter Lidén, Peter Dahlgren	Switch-level modeling of transistor-level stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling
36	Vincent John Mooney III, George F. Riley, Eung S. Shin	Round-Robin Arbiter Design and Generation.	ISSS	2002	DBLP DOI BibTeX RDF	distributed arbiter, round-robin token passing, terabit switch, synthesis, arbiter
36	Chenggong Charles Fan, Jehoshua Bruck	Tolerating Multiple Faults in Multistage Interconnection Networks with Minimal Extra Stages.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	extra-stage, switch faults, stage masks, fault tolerance, Multistage Interconnection Networks (MIN)
36	Ge Nong, Jogesh K. Muppala, Mounir Hamdi	A Performance Model for ATM Switches with Multiple Input Queues.	ICCCN	1997	DBLP DOI BibTeX RDF	performance evaluation, analytical modeling, computer simulation, ATM switch
35	Boris Nechaev, Vern Paxson, Mark Allman, Andrei V. Gurtov	On calibrating enterprise switch measurements.	Internet Measurement Conference	2009	DBLP DOI BibTeX RDF	network traces, switch-based packet capture, trace calibration, enterprise networks
35	Saad Mneimneh	Matching from the first iteration: an iterative switching algorithm for an input queued switch.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	iterative switching algorithms, number of iterations, speedup, matching algorithms, input queued switch
35	Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee	Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	VLIW DSP processor, optimizing context switch overhead, microkernel design
35	Yan Wang, Zhiwen Bai, Miao Zhang, Wen Du, Ying Qin, Xiyang Liu	Fitness calculation approach for the switch-case construct in evolutionary testing.	GECCO	2008	DBLP DOI BibTeX RDF	switch-case construct, fitness function, evolutionary testing
35	Katsuya Watabe, Tetsuya Saito, Nobutaka Matsumoto, Takuo Tanemura, Hideaki Imaizumi, Abdullah Al Amin, Mitsuru Takenaka, Yoshiaki Nakano, Hiroyuki Morikawa	80Gb/s Multi-wavelength Optical Packet Switching Using PLZT Switch.	ONDM	2007	DBLP DOI BibTeX RDF	multi-wavelength, optical packet, PLZT switch, WDM
35	O. Zouraraki, Paraskevas Bakopoulos, K. Vyrsokinos, Hercules Avramopoulos	2x2 Bismuth-Oxide-Fiber Based Crossbar Switch for All-Optical Switching Architectures.	ONDM	2007	DBLP DOI BibTeX RDF	Optically controlled 2x2 switch, Bismuth Oxide Nonlinear fiber, Ultrafast Nonlinear Interferometer (UNI), all-optical signal processing
35	Bill Lin 0001, Isaac Keslassy	Frame-aggregated concurrent matching switch.	ANCS	2007	DBLP DOI BibTeX RDF	100% throughput, concurrent matching switch, frame scheduling, load-balanced router, packet switching
35	Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner	A switch architecture and signal synchronization for GALS system-on-chips.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC switch, clock stretching, synchronization, GALS
35	Roberto Rojas-Cessa, Eiji Oki, H. Jonathan Chao	Concurrent fault detection for a multiple-plane packet switch.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	parallel planes, fault detection, packet switch, concurrent testing, single fault
35	Edson L. Horta, Sergio Takeo Kofuji	A Run-Time Reconfigurable ATM Switch.	IPDPS	2002	DBLP DOI BibTeX RDF	Partial RTR, ATM Switch, Reconfigurable Logic
35	Koji M. Kobayashi, Shuichi Miyazaki, Yasuo Okabe	Competitive buffer management for multi-queue switches in qos networks using packet buffering algorithms.	SPAA	2009	DBLP DOI BibTeX RDF	multi-queue switches, competitive analysis, buffer management
35	Simone Medardoni, Marcello Lajolo, Davide Bertozzi	Variation tolerant NoC design by means of self-calibrating links.	DATE	2008	DBLP DOI BibTeX RDF
35	Brian Towles, William J. Dally	Guaranteed scheduling for switches with configuration overhead.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	packet switching, optical switches
35	K. Ravindran	Design of Multicast Packet Swithches for High - speed Multi - Service Networks.	HPDC	1996	DBLP DOI BibTeX RDF
34	Cory Hawkins, Benjamin A. Small, D. Scott Wills, Keren Bergman	The Data Vortex, an All Optical Path Multicomputer Interconnection Network.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Optical switch fabrics, photonic packet switch, data vortex switch architecture, packet switching, optical switching
34	Niraj K. Jha	Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	CVS parity trees, strongly self-checking parity, single stuck-at, stuck-open, stuck-on fault detection, cascode voltage switch, differential cascode voltage switch, EX-OR gates, single-ended cascode voltage switch, logic testing, fault location, logic gates, two-rail checkers
34	Hossein Saidi 0001, Masoud Reza Hashemi	On the necessary and sufficient requirement of a CIOQ switch to emulate an Output Queued switch.	Opt. Switch. Netw.	2012	DBLP DOI BibTeX RDF
34	Yury Audzevich, Levente Bodrog, Yoram Ofek, Miklós Telek	Packet Loss Analysis of Load-Balancing Switch with ON/OFF Input Processes.	EPEW	2009	DBLP DOI BibTeX RDF
34	Artem Starostin, Alexandra Tsyban	Verified Process-Context Switch for C-Programmed Kernels.	VSTTE	2008	DBLP DOI BibTeX RDF
34	Ping Chen, Andy Ye	The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays.	FPL	2008	DBLP DOI BibTeX RDF
34	Gaspar Mora, Pedro Javier García, José Flich, José Duato	RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management.	ICPP	2007	DBLP DOI BibTeX RDF
34	Chih-Chieh Chou, Cheng-Shang Chang, Duan-Shin Lee, Jay Cheng	A Necessary and Sufficient Condition for the Construction of 2-to-1 Optical FIFO Multiplexers by a Single Crossbar Switch and Fiber Delay Lines.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
34	Heng-Ming Hsu, Ching-Liang Dai, Ming-Ming Hsieh, Ming-Chang Tsai, Hsuan-Jung Peng	Implementation and analysis of microwave switch in CMOS-MEMS technology.	ISCAS	2006	DBLP DOI BibTeX RDF
34	Jodelson A. Sabino, Thomas Stützle, Mauro Birattari, José Eugênio Leal	ACO Applied to Switch Engine Scheduling in a Railroad Yard.	ANTS Workshop	2006	DBLP DOI BibTeX RDF
34	Xiangrong Zhou, Peter Petrov	Rapid and low-cost context-switch through embedded processor customization for real-time and control applications.	DAC	2006	DBLP DOI BibTeX RDF
34	Jiho Chang, JongSu Yi, JunSeong Kim	A Switch Wrapper Design for SNA On-Chip-Network.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
34	Jordan E. Massad, Hartono Sumali, David S. Epp, Christopher W. Dyck	Modeling, Simulation, and Testing of the Mechanical Dynamics of an RF MEMS Switch.	ICMENS	2005	DBLP DOI BibTeX RDF
34	Bill Lin 0001, Isaac Keslassy	A Scalable Switch for Service Guarantees.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
34	Li Zhao 0002, Yan Luo, Laxmi N. Bhuyan, Ravishankar R. Iyer 0001	Design and Implementation of a Content-Aware Switch Using a Network Processor.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
34	Carlos Roberto dos Santos, Shusaburo Motoyama	A QoS Provisioned CIOQ ATM Switch with m Internal Links.	ICT	2004	DBLP DOI BibTeX RDF
34	Xing Fan, Magnus Jonsson, Hoai Hoang	Efficient Many-to-Many Real-Time Communication Using an Intelligent Ethernet Switch.	ISPAN	2004	DBLP DOI BibTeX RDF
34	Abdel Ejnioui, N. Ranganathan	Routing on field-programmable switch matrices.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
34	Laxmi N. Bhuyan, Hu-Jun Wang	Switch MSHR: A Technique to Reduce Remote Read Memory Access Time in CC-NUMA Multiprocessors.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	CC-NUMA multiprocessor, memory latency problem, miss status holding register, interconnection network, execution-driven simulation
34	Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu	Automated Test Model Generation from Switch Level Custom Circuits.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
34	Ali Mohammad Zareh Bidoki, Nasser Yazdani, Sayed Vahid Azhari, Siavash Samadian-Barzoki	A High Speed ATM/IP Switch Fabric Using Distributed Scheduler.	ICOIN	2003	DBLP DOI BibTeX RDF
34	David A. Helder, Sugih Jamin	End-Host Multicast Communication Using Switch-Trees Protocols.	CCGRID	2002	DBLP DOI BibTeX RDF	end-host multicast, peer-to-peer
34	Ravi R. Iyer 0001, Laxmi N. Bhuyan, Ashwini K. Nanda	Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors.	IPDPS	2000	DBLP DOI BibTeX RDF
34	Rajgopal Kannan, Sibabrata Ray	A Fair and Efficient Multicast ATM Switch based on Deflection Routing.	ISCC	2000	DBLP DOI BibTeX RDF	Multicasting, ATM Networks, Deflection Routing
34	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors.	HPCA	1999	DBLP DOI BibTeX RDF
34	Matthew G. Jacunski, P. Sadayappan, Dhabaleswar K. Panda 0001	All-to-All Broadcast on Switch-Based Clusters of Workstations.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
34	Srinidhi Varadarajan, Tzi-cker Chiueh	EtheReal: A Host-Transparent Real-Time Fast Ethernet Switch.	ICNP	1998	DBLP DOI BibTeX RDF	electronic switching systems, quality of service, real-time systems, local area networks, packet switching, multimedia communication, network operating systems, microcomputer applications
34	Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan 0001	Algorithms for an FPGA switch module routing problem with application to global routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
34	Christopher A. Ryan, Joseph G. Tront	FX: a fast approximate fault simulator for the switch-level using VHDL.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
34	Kent L. Einspahr, Sharad C. Seth	A switch-level test generation system for synchronous and asynchronous circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
33	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
33	Adnan Aziz, Amit Prakash, Vijaya Ramachandran	A near optimal scheduler for switch-memory-switch routers.	SPAA	2003	DBLP DOI BibTeX RDF	schedulers, parallelism, matching, randomization, routers
33	Pertti Raatikainen, Teleste Oy, Juha Zidbeck	Performance Comparison of Experimented Switching Architectures for ATM.	EUROMICRO	1996	DBLP DOI BibTeX RDF	broadband switching, transfer delay performance, Frame Synchronized Ring, switch structures, multidrop bus, multistage banyan network, interconnection networks, ATM, multiprocessor interconnection networks, ATM-switch, crossbar
33	Qin Zheng	An Enhanced Timed-Round-Robin Traffic Control Scheme for ATM Networks.	LCN	1996	DBLP DOI BibTeX RDF	timed round robin traffic control, guaranteed bandwidth, dynamic bandwidth sharing, bursty data traffic, integrated digital networks, cell transmission scheduling algorithm, feedback flow control, link bandwidth, ATM switch design, asynchronous transfer mode, asynchronous transfer mode, ATM networks, real-time communications, switch architectures
33	Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou	Pipelined Memory Shared Buffer for VLSI Switches.	SIGCOMM	1995	DBLP DOI BibTeX RDF	gigabit VLSI switch buffer, multiport buffer, pipelined memory, crossbar switch, shared buffering, input queueing
33	Saad AlKasabi, Salim Hariri	Performance analysis of a high-speed dynamically reconfigurable LAN.	LCN	1995	DBLP DOI BibTeX RDF	dynamically reconfigurable LAN, reconfigurable switch, highspeed multi-link ring local area network, switch reconfigurability, multi-link ring network, M/M/n, M/D/n, virtual channel occupancy probabilities, infinite state Markov model, finite state Markov model, OPNET tool, packet transfer time, virtual channel flow, performance evaluation, field programmable gate arrays, performance analysis, local area networks, reconfigurable architectures, wormhole routing, network performance, queuing systems, interconnection topologies, system throughput
32	Joseph Kee-Yin Ng, Ge Nong	Multimedia applications on FDDI networks connected by an ATM switch.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	high-speed local area network, internetwork multimedia applications, ATM switch interconnected networks, asynchronous transfer mode, video, local area networks, images, audio, graphics, digital simulation, multimedia communication, multimedia applications, text, ATM switch, data transfer, FDDI, broadband networks, B-ISDN, B-ISDN, simulation experiments, LAN interconnection, FDDI networks, network parameters
32	Eduard Cerny, Jan Gecsei	Functional Description of Connector-Switch-Attenuator Networks.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	connector-switch-attenuator networks, switch-level abstraction, digital MOS circuits, functional description, electron device testing, formal verification, logic testing, failure analysis, switching networks, characteristic functions, field effect integrated circuits
31	JIanDe Yu, Jinmei Lai	A novel minloop SB design to improve FPGA routability.	FPGA	2009	DBLP DOI BibTeX RDF	minimum-loop-size maximization method, minloop switch box, routing resources design, fpga
31	Simin He 0001, Shutao Sun, Wei Zhao, Yanfeng Zheng, Wen Gao 0001	Smooth switching problem in buffered crossbar switches.	SIGMETRICS	2005	DBLP DOI BibTeX RDF	CICQ, scheduling, smoothness, switch, buffered crossbar
31	María Blanca Caminero, Carmen Carrión 0001, Francisco J. Quiles 0001, José Duato, Sudhakar Yalamanchili	A Solution for Handling Hybrid Traffic in Clustered Environments: The MultiMedia Router MMR.	IPDPS	2003	DBLP DOI BibTeX RDF	Clusters of Workstations (COWs), Quality of Service (QoS), multimedia communications, router architecture, switch scheduling
31	Krishna Kant 0001	Performance of internal overload controls in large switches.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	internal overload control performance, large switches, switch sizes, call capacity, voice circuits, overload performance, network integrity, peripheral scanning schemes, scheduling, performance evaluation, virtual machines, logic CAD, circuit analysis computing, simulation model, service integrity, buffer sizes, switching circuits
30	Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux	On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch
30	Joe Kelly, Dean Nicholson, Edwin Lowery, Victor Grothen	Light-Enhanced FET Switch Improves ATE RF Power Settling.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	FET, RF switch, power settling, HVM, high-volume manufacturing, ATE, test time, settling time
30	Xiumin Gao	Tunable Optical Trap Induced by Focal Shift and Focal Switch in a Focusing Apodized Optical System.	BMEI (2)	2008	DBLP DOI BibTeX RDF	optical trap, focal shift, focal switch, apodizer
30	Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung	The exact channel density and compound design for generic universal switch blocks.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	universal switch block, routing algorithm, FPGA architecture
30	Timothy J. Brothers, Suresh Muknahallipatna, Jerry C. Hamann	Fibre Channel Switch Modeling at Fibre Channel-2 Level for Large Fabric Storage Area Network Simulations using OMNeT++: Preliminary Results.	LCN	2007	DBLP DOI BibTeX RDF	FC-2 level, Simulator, Modeling, Scaling, Switch, Fabric, Fibre Channel
30	Li Zhao 0002, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer 0001	A Network Processor-Based, Content-Aware Switch.	IEEE Micro	2006	DBLP DOI BibTeX RDF	content-aware switch, ENP2611, Intel IXP 2400, network processor
30	Iñigo Artundo, Daniel Manjarres, Wim Heirman, Christof Debaes, Joni Dambre, Jan M. Van Campenhout, Hugo Thienpont	Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior.	ISPA Workshops	2006	DBLP DOI BibTeX RDF	interconnection network, multiprocessors, Reconfiguration, distributed shared memory, context switch
30	Christoforos Kachris, Stamatis Vassiliadis	Design of a web switch in a reconfigurable platform.	ANCS	2006	DBLP DOI BibTeX RDF	web switch, reconfigurable logic
30	John Mason	Teaching by analogy: the switch statement.	ACM SIGCSE Bull.	2004	DBLP DOI BibTeX RDF	methodology, switch, analogy
30	Haralambos Laskaridis, Georgios I. Papadimitriou, Andreas S. Pomportsis	Applying Optical Reconfiguration on ATM Switch Fabrics.	IPDPS	2003	DBLP DOI BibTeX RDF	ATM, reconfiguration, correlation, switch fabric
30	Jan-Jan Wu, Da-Wei Wang 0004, Yih-Fang Lin	Placement of I/O servers to improve parallel I/O performance on switch-based clusters.	ICS	2003	DBLP DOI BibTeX RDF	part-time I/O assignment, switch-based clusters, parallel I/O, bipartite matching
30	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF	RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
30	María Blanca Caminero, Carmen Carrión 0001, Francisco J. Quiles 0001, José Duato, Sudhakar Yalamanchili	Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router.	IPDPS	2002	DBLP DOI BibTeX RDF	Quality of Service, multimedia communications, router architecture, switch scheduler
30	Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul	System-Level Modeling of a Network Switch SoC.	ISSS	2002	DBLP DOI BibTeX RDF	memory visualization level design, network switch, computer-aided design, performance modeling, system modeling
30	David Whelihan, Herman Schmit	Memory optimization in single chip network switch fabrics.	DAC	2002	DBLP DOI BibTeX RDF	network switch, SOC, memory optimization
30	Damon S. Love, Sudhakar Yalamanchili, José Duato, María Blanca Caminero, Francisco J. Quiles 0001	Switch Scheduling in the Multimedia Router (MMR).	IPDPS	2000	DBLP DOI BibTeX RDF	Quality of Service (QoS), Multimedia traffic, Router architecture, Switch scheduling
30	Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee	ATM switch design by high-level modeling, formal verification and high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	verification, synthesis, ATM switch, high-level design
30	William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland	A FIFO Data Switch Design Experiment.	ASYNC	1998	DBLP DOI BibTeX RDF	Data Switch, P**3, Asynchronous, FIFO
30	Jaehong Shim, Kyongok Yun, Kyunghee Choi, Gihyun Jung, Seungkyu Park, Dugkyoo Choi	A switch scheduling algorithm for periodic messages using laxity decomposition method.	RTCSA	1997	DBLP DOI BibTeX RDF	switch scheduling algorithm, periodic messages, laxity decomposition method, real time messages scheduling, laxities, schedulable messages, MLF algorithm, time division multiple access, simulation results, traffic matrix
30	Hea-Sook Park, Sung-Jin Moon, Man-Sik Park, Boseob Kwon, Kwang-Suk Song	Design of inter processor communication controller using ATM switch and analysis of its optimal message length considering retransmission.	RTCSA	1997	DBLP DOI BibTeX RDF	inter processor communication controller, optimal message length, distributed large-scale multiprocessors, ATM adaptation layer, message error rate, message retransmission rate, asynchronous transfer mode, ATM switch, asynchronous transfer mode switches
30	George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis	Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control.	ARVLSI	1997	DBLP DOI BibTeX RDF	single-chip ATM switch, VLSI router, pipelined queue management, credit-based flow control
30	Tadayoshi Horita, Itsuo Takanami	A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.	ISPAN	1997	DBLP DOI BibTeX RDF	mesh arrays, the 1frac{1}{2} track-switch model, fault-tolerance, polynomial time algorithm, wafer scale integration
30	Cheng-Shang Chang, Philip Heidelberger, Perwez Shahabuddin	Fast Simulation of Packet Loss Rates in a Shared Buffer Communications Switch.	ACM Trans. Model. Comput. Simul.	1995	DBLP DOI BibTeX RDF	importance sampling, packet loss, variance reduction, queuing model, rare event, communications switch
30	Manju V. Hegde, Morteza Naraghi-Pour, Y. Li	The deflecting multicast switch.	ICCCN	1995	DBLP DOI BibTeX RDF	deflecting multicast switch, multicast switching paradigm, replication functions, routing functions, low connection complexity, modular implementation, self-replication algorithm, self-routing algorithm, minimal control overhead, cell sequence maintenance, buffer delays, uniform traffic patterns, numerical results, analytical results, ATM, upper bound, distributed control, telecommunication network routing, cell loss probability
30	Jian Wang, Ted H. Szymanski	Power analysis of Input-Queued and Crosspoint-Queued crossbar switches.	CCECE	2009	DBLP DOI BibTeX RDF
30	Ziqian Dong, Roberto Rojas-Cessa	Input- and Output-Based Shared-Memory Crosspoint-Buffered Packet Switches for Multicast Traffic Switching and Replication.	ICC	2008	DBLP DOI BibTeX RDF
30	Teresa Nachiondo Frinós, José Flich, José Duato	Efficient Reduction of HOL Blocking in Multistage Networks.	IPDPS	2005	DBLP DOI BibTeX RDF
30	Ayman G. Fayoumi, Fahad Ahmed Al-Zahrani, Abdulgader A. Habiballa, Anura P. Jayasumana	Performance Analysis of Multi-Fiber Synchronous Photonic Share-per-link Packet Switches.	LCN	2005	DBLP DOI BibTeX RDF