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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4401 occurrences of 2030 keywords
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Results
Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
27 | Stephen Roderick Hines, Gary S. Tyson, David B. Whalley |
Addressing instruction fetch bottlenecks by using an instruction register file. |
LCTES |
2007 |
DBLP DOI BibTeX RDF |
L0/filter cache, instruction packing, instruction register file |
27 | Xiangxue Li, Dong Zheng 0001, Kefei Chen |
Efficient Blind Signatures from Linear Feedback Shift Register. |
CDVE |
2007 |
DBLP DOI BibTeX RDF |
Linear Feedback Shift Register, Blind Signature |
27 | Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni |
On the latency, energy and area of checkpointed, superscalar register alias tables. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
latency, checkpointing, energy, register renaming |
27 | Kimish Patel, Wonbok Lee, Massoud Pedram |
Minimizing power dissipation during write operation to register files. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
write operation, power, register file |
27 | Xiangxue Li, Dong Zheng 0001, Kefei Chen |
Efficient Linkable Ring Signatures and Threshold Signatures from Linear Feedback Shift Register. |
ICA3PP |
2007 |
DBLP DOI BibTeX RDF |
characteristic sequence, linkable ring signature, linear feedback shift-register, threshold signature |
27 | Dong Zheng 0001, Xiangxue Li, Kefei Chen, Jianhua Li |
Linkable Ring Signatures from Linear Feedback Shift Register. |
EUC Workshops |
2007 |
DBLP DOI BibTeX RDF |
Characteristic sequence, Linkabilty, Anonymity, Linear feedback shift register, Ring signatures |
27 | Deniz Dal, Nazanin Mansouri |
A high-level register optimization technique for minimizing leakage and dynamic power. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
power islands, register optimization, partitioning, HLS, high level synthesis, leakage, DSM |
27 | Jinpyo Park, Soo-Mook Moon |
Optimistic register coalescing. |
ACM Trans. Program. Lang. Syst. |
2004 |
DBLP DOI BibTeX RDF |
Copy coalescing, noncopy coalescing, graph coloring, register allocation |
27 | Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes 0001, Everton Carara |
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
transaction level, VHDL, SystemC, System modeling, register transfer level |
27 | Rama Sangireddy, Arun K. Somani |
Application-Specific Computing with Adaptive Register File Architectures. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
Computing capacity, compute-intensive Function, Memory bandwidth, Register File |
27 | Mary D. Brown, Yale N. Patt |
Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. |
HPCA |
2002 |
DBLP DOI BibTeX RDF |
redundant binary, limited bypass, pipelined register file, signed digit |
27 | Ramesh Karri, Balakrishnan Iyer |
Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register transfer level, on line testing |
27 | Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata |
Dataflow Analysis for Resource Contention and Register Leakage Properties. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
Register Leakage, Simulation, Formal Verification, Resource Contention |
27 | Zahari M. Darus, Iftekhar Ahmed 0003, Liakot Ali |
A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
test processor chip, multiple polynomial linear feedback shift register, ASIC chip, scan-path testing, external IC tester, simulation, fault coverage, shift registers, pattern generator, multiple seed |
27 | Christos A. Papachristou, Mikhail Baklashov |
A test synthesis technique using redundant register transfers. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
behavioral variables, conditional statements, redundant register transfers, structural signals, test synthesis technique, testability metrics, graph theory, logic testing, controllability, high level synthesis, VHDL, observability, fault coverage, data path, hardware overhead, behavioral descriptions |
27 | R. Moreno, Román Hermida, Milagros Fernández |
Register estimation in unscheduled dataflow graphs. |
ACM Trans. Design Autom. Electr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
register estimation, scheduling, probabilities, high-level synthesis, area estimation |
27 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register-transfer level estimation techniques for switching activity and power consumption. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs |
27 | Li Cheng, Dingxing Wang, Meiming Shen, Weimin Zheng, Peng Shanling |
The Compiler for Supporting Multithreading in Cyclic Register Windows. |
ISPAN |
1996 |
DBLP DOI BibTeX RDF |
pipeline, Multithreading, compilation optimization, register allocation, multicomputers |
27 | Rajesh Gupta 0003, Melvin A. Breuer |
Partial scan design of register-transfer level circuits. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
serial scan design, I-paths, design for testability, register-transfer level designs, balanced structures, partial scan design |
27 | Kala Srivatsan, Chaitali Chakrabarti, Lori Lucke |
Low power data format converter design using semi-static register allocation. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
code convertors, low power data format converter design, semi-static register allocation, processing modules, VLSI, linear programming, integer programming, signal processing, digital signal processing, power consumption, integer linear programming, heuristic programming, heuristic programming, VLSI implementations |
27 | Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy |
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
MUSTC-testing, multi-stage-combinational test, control paths, signal types, module level pre-computed test sets, scheduling, logic testing, integrated circuit testing, combinational circuits, automatic testing, automatic test, register-transfer level, test scheduling, data-paths |
26 | Stéphane Demri, Ranko Lazic 0001 |
LTL with the freeze quantifier and register automata. |
ACM Trans. Comput. Log. |
2009 |
DBLP DOI BibTeX RDF |
Computational complexity, expressiveness |
26 | Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura |
Lagrangian relaxation based register placement for high-performance circuits. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella 0001, Antonio González 0001 |
End-to-end register data-flow continuous self-test. |
ISCA |
2009 |
DBLP DOI BibTeX RDF |
end-to-end protection, online testing, degradation, design errors, control logic |
26 | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie |
Register File Power Reduction Using Bypass Sensitive Compiler. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Peter Koepke, Ryan Siders |
Register computations on ordinals. |
Arch. Math. Log. |
2008 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classification (2000) 03D60, 03E45 |
26 | Chun Jason Xue, Edwin Hsing-Mean Sha, Zili Shao, Meikang Qiu |
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Jason Cong, Junjuan Xu |
Simultaneous FU and Register Binding Based on Network Flow Method. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda |
REWIRED - Register Write Inhibition by Resource Dedication. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Fang Lu, Lei Wang 0004, Xiaobing Feng 0002, Zhiyuan Li 0001, Zhaoqing Zhang |
Exploiting idle register classes for fast spill destination. |
ICS |
2008 |
DBLP DOI BibTeX RDF |
spilling cost, data transfer |
26 | Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki |
Safe clocking register assignment in datapath synthesis. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Jens Palsberg |
Verification of Register Allocators. |
VMCAI |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Mojtaba Amiri-Kamalabad, Seyed Ghassem Miremadi, Mahdi Fazeli |
A Power Efficient Approach to Fault-Tolerant Register File Design. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Vivek Sarkar, Rajkishore Barik |
Extended Linear Scan: An Alternate Foundation for Global Register Allocation. |
CC |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Min Ni, Seda Ogrenci Memik |
Early planning for clock skew scheduling during register binding. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo |
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Yukihide Kohira, Atsushi Takahashi 0001 |
A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Jie Guo 0007, Jun Liu, Björn Mennenga, Gerhard P. Fettweis |
A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Zhixiong Zhou, Hu He 0001, Yanjun Zhang, Yihe Sun, Adriel Cheng |
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh |
Optimal register sharing for high-level synthesis of SSA form programs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Kiran Puttaswamy, Gabriel H. Loh |
Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Keith D. Cooper, Anshuman Dasgupta |
Tailoring Graph-coloring Register Allocation For Runtime Compilation. |
CGO |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Stéphane Demri, Ranko Lazic 0001 |
LTL with the Freeze Quantifier and Register Automata. |
LICS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Sebastian Hack, Daniel Grund, Gerhard Goos |
Register Allocation for Programs in SSA-Form. |
CC |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail |
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. |
DSN |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Fernando Magno Quintão Pereira, Jens Palsberg |
Register Allocation Via Coloring of Chordal Graphs. |
APLAS |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yixin Shi, Gyungho Lee |
Dynamic Partition of Memory Reference Instructions - A Register Guided Approach. |
Euro-Par |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Steven Hsu, Amit Agarwal 0001, Kaushik Roy 0001, Ram Krishnamurthy 0001, Shekhar Borkar |
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
dual-Vt/Vcc, flip-flop, hot spot, level converter |
26 | Deming Chen, Jason Cong |
Register binding and port assignment for multiplexer optimization. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Hassan Al Atat, Iyad Ouaiss |
Register Binding for FPGAs with Embedded Memory. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Betül Demiröz, Haluk Topcuoglu, Mahmut T. Kandemir |
A Hybrid Evolutionary Algorithm for Solving the Register Allocation Problem. |
EvoCOP |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Dong Chun Lee, Hongjin Kim, Il-Sun Hwang |
Improved Location Scheme Using Circle Location Register in Mobile Networks. |
International Conference on Computational Science |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Haibo Lin, Wenlong Li, Zhizhong Tang |
Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture. |
APPT |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga |
Reducing Access Count to Register-Files through Operand Reuse. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Nestoras Tzartzanis, William W. Walker |
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
26 | José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez |
Energy Aware Register File Implementation through Instruction Predecode. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Cagdas Akturan, Margarida F. Jacome |
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga |
Register File Energy Reduction by Operand Data Reuse. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
26 | D. A. F. Ei-Dib, Mohamed I. Elmasry |
Low-power register-exchange Viterbi decoder for high-speed wireless communications. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Modulo scheduling with integrated register spilling for clustered VLIW architectures. |
MICRO |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Cagdas Akturan, Margarida F. Jacome |
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors. |
CODES |
2001 |
DBLP DOI BibTeX RDF |
embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors |
26 | Abhiram G. Ranade, Sonal Kothari, Raghavendra Udupa |
Register Efficient Mergesorting. |
HiPC |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang |
"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Cindy Norris, James B. Fenwick Jr. |
Understanding and Improving Register Assignment. |
Euro-Par |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin |
The Design of a Register Renaming Unit. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Keith D. Cooper, L. Taylor Simpson |
Live Range Splitting in a Graph Coloring Register Allocator. |
CC |
1998 |
DBLP DOI BibTeX RDF |
|
26 | A. V. S. Sastry, Roy Dz-Ching Ju |
A New Algorithm for Scalar Register Promotion based on SSA Form. |
PLDI |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Dirk Herrmann, Rolf Ernst |
Register synthesis for speculative computation. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Josep Llosa, Mateo Valero, Eduard Ayguadé |
Heuristics for Register-Constrained Software Pipelining. |
MICRO |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Robert G. Burger, Oscar Waddell, R. Kent Dybvig |
Register Allocation Using Lazy Saves, Eager Restores, and Greedy Shuffling. |
PLDI |
1995 |
DBLP DOI BibTeX RDF |
|
26 | Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham |
Minimum register requirements for a modulo schedule. |
MICRO |
1994 |
DBLP DOI BibTeX RDF |
|
26 | Wolfgang Ambrosch, M. Anton Ertl, Felix Beer, Andreas Krall |
Dependence-Conscious Global Register Allocation. |
Programming Languages and System Architectures |
1994 |
DBLP DOI BibTeX RDF |
|
26 | Clifford Liem, Trevor C. May, Pierre G. Paulin |
Register assignment through resource classification for ASIP microcode generation. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
26 | Qi Ning, Guang R. Gao |
A Novel Framework of Register Allocation for Software Pipelining. |
POPL |
1993 |
DBLP DOI BibTeX RDF |
|
26 | Shlomit S. Pinter |
Register Allocation with Instruction Scheduling: A New Approach. |
PLDI |
1993 |
DBLP DOI BibTeX RDF |
|
26 | B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker |
Register Allocation for Software Pipelined Loops. |
PLDI |
1992 |
DBLP DOI BibTeX RDF |
|
26 | Rajiv Gupta 0001 |
A fine-grained MIMD architecture based upon register channels. |
MICRO |
1990 |
DBLP BibTeX RDF |
multiprocessor system, parallelizing compilers, instruction scheduling, aliasing, channels, fine-grained parallelism |
26 | Nam Sung Woo |
A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
26 | Rajiv Gupta 0001, Mary Lou Soffa, Tim Steele |
Register Allocation via Clique Separators. |
PLDI |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Cees J. A. Jansen, Dick E. Boekee |
The Shortest Feedback Shift Register That Can Generate A Given Sequence. |
CRYPTO |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Manuel L. Anido, David J. Allerton, Ed Zaluska |
A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine. |
ISCA |
1989 |
DBLP DOI BibTeX RDF |
Computer Image Generation, Computer Architecture, VLSI Design, Interprocessor Communication, RISC, Reduced Instruction Set Computers |
26 | David Knapp |
An Interactive Tool for Register-level Structure Optimization. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Baruch Awerbuch, Lefteris M. Kirousis, Evangelos Kranakis, Paul M. B. Vitányi |
A Proof Technique for Register Automicity. |
FSTTCS |
1988 |
DBLP DOI BibTeX RDF |
|
26 | Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu |
High-speed generation of LFSR signatures. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
high-speed generation, LFSR signatures, compaction simulation, single-input signature register, equivalent multiple-input implementation, finite field theory, high-speed signature computations, lookahead technique, internal-XOR LFSR, external-XOR LFSR, performance evaluation, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, BIST, linear feedback shift register, binary sequences, subsequences |
26 | Jacob Savir |
Reduced Latch Count Shift Registers. |
J. Electron. Test. |
1997 |
DBLP DOI BibTeX RDF |
shift register latch, scan register, shifting clocks, STUMPS architecture, LSSD |
25 | Mohamed M. Sabry, José L. Ayala, David Atienza |
Thermal-aware compilation for system-on-chip processing architectures. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
compiler, register-file, thermal-aware |
25 | Lian Li 0002, Hui Feng, Jingling Xue |
Compiler-directed scratchpad memory management via graph coloring. |
ACM Trans. Archit. Code Optim. |
2009 |
DBLP DOI BibTeX RDF |
live range splitting, memory coloring, graph coloring, memory allocation, Scratchpad memory, register coalescing, software-managed cache |
25 | Dietmar Ebner, Bernhard Scholz, Andreas Krall |
Progressive spill code placement. |
CASES |
2009 |
DBLP DOI BibTeX RDF |
constrained min-cut, spilling, register allocation, SSA form |
25 | Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki |
Safe clocking for the setup and hold timing constraints in datapath synthesis. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
ordered clocking, register assignment, datapath synthesis |
25 | Andrei Sergeevich Terechko, Henk Corporaal |
Inter-cluster communication in VLIW architectures. |
ACM Trans. Archit. Code Optim. |
2007 |
DBLP DOI BibTeX RDF |
intercluster communication, pipelining, Instruction-level parallelism, register allocation, VLIW, instruction scheduler, optimizing compiler, clock frequency, cluster assignment |
25 | Asadollah Shahbahrami, Ben H. H. Juurlink, Demid Borodin, Stamatis Vassiliadis |
Avoiding Conversion and Rearrangement Overhead in SIMD Architectures. |
Int. J. Parallel Program. |
2006 |
DBLP DOI BibTeX RDF |
Embedded media processors, multimedia kernels, register file, subword parallelism |
25 | Sultan Al-Hinai, Lynn Margaret Batten, Bernard D. Colbert, Kenneth Koon-Ho Wong |
Algebraic Attacks on Clock-Controlled Stream Ciphers. |
ACISP |
2006 |
DBLP DOI BibTeX RDF |
irregular clocking, stream cipher, linear feedback shift register, algebraic attack, clock control |
25 | Van-Ly Le, Werner Schindler |
How to Embed Short Cycles into Large Nonlinear Feedback-Shift Registers. |
SCN |
2004 |
DBLP DOI BibTeX RDF |
short cycles, systems of algebraic equations, low-cost group identification, Nonlinear feedback shift register, invariant theory |
25 | Mizuhito Ogawa, Zhenjiang Hu, Isao Sasano |
Iterative-free program analysis. |
ICFP |
2003 |
DBLP DOI BibTeX RDF |
SP term, dynamic programming, program analysis, register allocation, control flow graph, tree width, catamorphism |
25 | Venkata Krishnan, Josep Torrellas |
The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. |
IEEE PACT |
1999 |
DBLP DOI BibTeX RDF |
register communication, Chip-multiprocessor, speculative multithreading, data-dependence speculation |
25 | Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero |
A distributed processor state management architecture for large-window processors. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Xuxian Jiang, Helen J. Wang, Dongyan Xu, Yi-Min Wang |
RandSys: Thwarting Code Injection Attacks with System Service Interface Randomization. |
SRDS |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Sumeet Kumar, Aneesh Aggarwal |
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors. |
HPCA |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Yen-Jen Chang |
An Alternative Real-Time Filter Scheme to Block Buffering. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
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