Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
34	Ronaldo Rodrigues Ferreira, Gabriel L. Nazar, Jean da Rolt, Álvaro F. Moreira, Luigi Carro	Live-Out Register Fencing: Interrupt-Triggered Soft Error Correction Based on the Elimination of Register-to-Register Communication.	ACM Trans. Embed. Comput. Syst.	2016	DBLP DOI BibTeX RDF
34	Nam Duong, Rakesh Kumar	Register Multimapping: A technique for reducing register bank conflicts in processors with large register files.	SASP	2009	DBLP DOI BibTeX RDF
33	Hanspeter Mössenböck, Michael Pfeiffer 0004	Linear Scan Register Allocation in the Context of SSA Form and Register Constraints.	CC	2002	DBLP DOI BibTeX RDF
32	Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González 0001	Modulo Scheduling with Reduced Register Pressure.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	register allocation, software pipelining, Instruction scheduling, loop scheduling, register spilling
32	Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz	A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification.	MICRO	1998	DBLP DOI BibTeX RDF	dependency redirection, physical register reuse, register and memory renaming, result reuse, value temporal locality
32	Meng-chou Chang, Feipei Lai	Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors
32	Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke	Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions.	CGO	2010	DBLP DOI BibTeX RDF	ARCompact, dual instruction set architecture, variable-length instructions, register allocation, code size, instruction selection
32	Xuejun Yang, Yu Deng 0001, Li Wang 0027, Xiaobo Yan, Jing Du 0002, Ying Zhang 0032, Guibin Wang, Tao Tang 0001	SRF Coloring: Stream Register File Allocation via Graph Coloring.	J. Comput. Sci. Technol.	2009	DBLP DOI BibTeX RDF	SRF coloring, stream register file, memory management, compiler optimization, graph coloring, stream processor
32	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.	DAC	2008	DBLP DOI BibTeX RDF	dynamic resizing, performance, embedded processor, register file
32	Kimish Patel, Wonbok Lee, Massoud Pedram	Active bank switching for temperature control of the register file in a microprocessor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	register file, thermal model, temperature-aware design
32	Joel David Hamkins, Russell G. Miller	Post's Problem for Ordinal Register Machines.	CiE	2007	DBLP DOI BibTeX RDF	ordinal computability, ordinal register machine, Post’s Problem, computability
32	Michael Drmota, Helmut Prodinger	The register function for t-ary trees.	ACM Trans. Algorithms	2006	DBLP DOI BibTeX RDF	Horton-Strahler numbers, Register function, generating functions, asymptotics
32	Chantana Chantrapornchai, Wanlop Surakumpolthorn, Edwin Hsing-Mean Sha	Design Exploration Framework Under Impreciseness Based on Register-Constrained Inclusion Scheduling.	ASIAN	2004	DBLP DOI BibTeX RDF	Imprecise Design Exploration, Scheduling/Allocation, Multiple design attributes, Register constraint, Inclusion Scheduling, Imprecise information
32	Kun Zhang 0006, Tao Zhang 0037, Santosh Pande	Binary translation to improve energy efficiency through post-pass register re-allocation.	EMSOFT	2004	DBLP DOI BibTeX RDF	cache power consumption, dead registers, register re-allocation, unused registers
32	Masaharu Goto, Toshinori Sato	Leakage Energy Reduction in Register Renaming.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF	super-scalar processors, embedded processors, register renaming, deep submicron, Leakage energy
32	Nam Sung Kim, Trevor N. Mudge	Reducing register ports using delayed write-back queues and operand pre-fetch.	ICS	2003	DBLP DOI BibTeX RDF	write queue, low power, instruction level parallelism, register file, out-of-order processor
32	Torben Amtoft, Robert Muller	Inferring annotated types for inter-procedural register allocation with constructor flattening.	TLDI	2003	DBLP DOI BibTeX RDF	type systems, register allocation, effects, defunctionalization, certifying compilers
32	Josep M. Codina, F. Jesús Sánchez, Antonio González 0001	A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors.	IEEE PACT	2001	DBLP DOI BibTeX RDF	register allocation, Modulo scheduling, clustered architectures, spill code, cluster assignment
32	Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan 0002	CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis.	VLSI Design	2000	DBLP DOI BibTeX RDF	Register and Module Assignment Design for low power, High level synthesis, Low power design, Floorplanning
32	Massimiliano Poletto, Vivek Sarkar	Linear scan register allocation.	ACM Trans. Program. Lang. Syst.	1999	DBLP DOI BibTeX RDF	compilers, register allocation, code optimization
32	Matthias Mutz	Register Transfer Level VHDL Models without Clocks.	DATE	1998	DBLP DOI BibTeX RDF	VHDL RT subset, register transfer level models
32	Ambuj K. Singh, James H. Anderson, Mohamed G. Gouda	The Elusive Atomic Register.	J. ACM	1994	DBLP DOI BibTeX RDF	linearizability, atomic register, wait-free synchronization
32	Werner E. Kluge	Data File Management in Shift Register Memories.	ACM Trans. Database Syst.	1978	DBLP DOI BibTeX RDF	LIFO/FIFO operation modes, management of sequentially organized files, record retrieval, updating, insertion, data transformations, deletion, relocation, shift-register memories
32	Joseph S. M. Ho, Ian F. Akyildiz	Dynamic hierarchical database architecture for location management in PCS networks.	IEEE/ACM Trans. Netw.	1997	DBLP DOI BibTeX RDF	call delivery, directory register, location registeration, visitor location register, home location register
31	Anjali Mahajan, M. Sadique Ali	Hybrid Evolutionary Algorithm for the Graph Coloring Register Allocation Problem for Embedded Systems.	Trans. Comput. Sci.	2009	DBLP DOI BibTeX RDF
31	Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose	Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	General, Microprocessors, Pipeline processors, Performance attributes
31	Mei Wen, Nan Wu 0003, Maolin Guan, Chunyuan Zhang	Load scheduling: Reducing pressure on distributed register files for free.	ASP-DAC	2008	DBLP DOI BibTeX RDF
31	Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley	Register Bank Assignment for Spatially Partitioned Processors.	LCPC	2008	DBLP DOI BibTeX RDF
31	Haluk Rahmi Topcuoglu, Betül Demiröz, Mahmut T. Kandemir	Solving the Register Allocation Problem for Embedded Systems Using a Hybrid Evolutionary Algorithm.	IEEE Trans. Evol. Comput.	2007	DBLP DOI BibTeX RDF
31	Weihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu	Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors.	PACT	2007	DBLP DOI BibTeX RDF
31	Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar 0001, Chris Reade	Register Sharing Verification During Data-Path Synthesis.	ICCTA	2007	DBLP DOI BibTeX RDF
31	Santosh G. Nagarakatte, R. Govindarajan	Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation.	CC	2007	DBLP DOI BibTeX RDF
31	Noureddine Chabini, Wayne H. Wolf	Register binding guided by the size of variables.	ICCD	2007	DBLP DOI BibTeX RDF
31	Qingying Deng, Minxuan Zhang, Jiang Jiang	Register File Management and Compiler Optimization on EDSMT.	ISPA Workshops	2007	DBLP DOI BibTeX RDF
31	Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim	Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture.	DAC	2007	DBLP DOI BibTeX RDF
31	Dae-Hwan Kim, Hyuk-Jae Lee	Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors.	SAMOS	2006	DBLP DOI BibTeX RDF
31	V. Krishna Nandivada, Jens Palsberg	SARA: Combining Stack Allocation and Register Allocation.	CC	2006	DBLP DOI BibTeX RDF
31	Fernando Magno Quintão Pereira, Jens Palsberg	Register Allocation After Classical SSA Elimination is NP-Complete.	FoSSaCS	2006	DBLP DOI BibTeX RDF
31	Jongwoo Bae, Neungsoo Park, Seong-Won Lee	Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter.	EUC	2006	DBLP DOI BibTeX RDF
31	Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya	A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.	DFT	2006	DBLP DOI BibTeX RDF
31	Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu	Register binding for clock period minimization.	DAC	2006	DBLP DOI BibTeX RDF	high-level synthesis, clock skew, timing optimization
31	Khaing Khaing Kyi Win, Weng-Fai Wong	Cooperative Instruction Scheduling with Linear Scan Register Allocation.	HiPC	2005	DBLP DOI BibTeX RDF
31	Rami Beidas, Jianwen Zhu	Scalable interprocedural register allocation for high level synthesis.	ASP-DAC	2005	DBLP DOI BibTeX RDF
31	Nagendran Rangan, Karam S. Chatha	A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling.	VLSI Design	2005	DBLP DOI BibTeX RDF
31	Kentaro Hamayasu, Vasily G. Moshnyaga	Impact of Register-Cache Bandwidth Variation on Processor Performance.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
31	Saisanthosh Balakrishnan, Gurindar S. Sohi	Exploiting Value Locality in Physical Register Files.	MICRO	2003	DBLP DOI BibTeX RDF
31	Atsushi Ohori	Register Allocation by Proof Transformation.	ESOP	2003	DBLP DOI BibTeX RDF
31	Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa	On the Design of a Register Queue Based Processor Architecture (FaRM-rq).	ISPA	2003	DBLP DOI BibTeX RDF
31	Ramesh Karri, Balakrishnan Iyer, Israel Koren	Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
31	Xuemei Zhao, Yizheng Ye	Design and Realization of a Low Power Register File Using Energy Model.	PATMOS	2002	DBLP DOI BibTeX RDF
31	Changqing Fu, Kent D. Wilken	A faster optimal register allocator.	MICRO	2002	DBLP DOI BibTeX RDF
31	Lin Zhong 0001, Jiong Luo, Yunsi Fei, Niraj K. Jha	Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors.	ICCD	2002	DBLP DOI BibTeX RDF
31	Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, S. Wolter, Steffen Buch, Marek Wróblewski, Josef A. Nossek	Low power register file architecture for application specific DSPs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
31	Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan	Analysis of the influence of register file size on energyconsumption, code size, and execution time.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
31	Mike J. G. Lewis, L. E. M. Brackenbury	Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank.	ASYNC	2001	DBLP DOI BibTeX RDF
31	Sid Ahmed Ali Touati	Register Saturation in Superscalar and VLIW Codes.	CC	2001	DBLP DOI BibTeX RDF
31	Soner Önder, Rajiv Gupta 0001	Load and store reuse using register file contents.	ICS	2001	DBLP DOI BibTeX RDF
31	Nazanin Mansouri, Ranga Vemuri	Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs.	DATE	1999	DBLP DOI BibTeX RDF
31	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	A design-for-testability technique for register-transfer level circuits using control/data flow extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
31	Sylvain Lelait, Guang R. Gao, Christine Eisenbeis	A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops.	CC	1998	DBLP DOI BibTeX RDF
31	Fred C. Chow, Robert Kennedy, Shin-Ming Liu, Raymond Lo, Peng Tu	Register Promotion by Partial Redundancy Elimination of Loads and Stores.	PLDI	1998	DBLP DOI BibTeX RDF
31	Johan Agat	Types for Register Allocation.	Implementation of Functional Languages	1997	DBLP DOI BibTeX RDF
31	Silvia M. Müller, Uzi Vishkin	Conflict-Free Access to Multiple Single-Ported Register Files.	IPPS	1997	DBLP DOI BibTeX RDF
31	Tsung-Yi Wu, Youn-Long Lin	Register minimization beyond sharing among variables.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
31	Todd A. Proebsting, Charles N. Fischer	Demand-Driven Register Allocation.	ACM Trans. Program. Lang. Syst.	1996	DBLP DOI BibTeX RDF	optimizing compiler
31	David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker	Global Predicate Analysis and Its Application to Register Allocation.	MICRO	1996	DBLP DOI BibTeX RDF
31	Rajiv Gupta 0001, Mary Lou Soffa, Denise Ombres	Efficient Register Allocation via Coloring Using Clique Separators.	ACM Trans. Program. Lang. Syst.	1994	DBLP DOI BibTeX RDF	clique separators, node priorities, graph coloring, spans, spill code, interference graph
31	Qi Ning	Register allocation for optimal loop scheduling.	CASCON	1993	DBLP BibTeX RDF
31	Todd A. Proebsting, Charles N. Fischer	Probalistic Register Allocation.	PLDI	1992	DBLP DOI BibTeX RDF
31	Angelika Zobel	Program structure as basis for parallelizing global register allocation.	ICCL	1992	DBLP DOI BibTeX RDF
31	Philip H. Sweany, Steven J. Beaty	Post-compaction register assignment in a retargetable compiler.	MICRO	1990	DBLP BibTeX RDF
31	Vatsa Santhanam, Daryl Odnert	Register Allocation Across Procedure and Module Boundaries.	PLDI	1990	DBLP DOI BibTeX RDF	RISC
31	Gregory J. Chaitin	Register Allocation & Spilling via Graph Coloring.	SIGPLAN Symposium on Compiler Construction	1982	DBLP DOI BibTeX RDF
31	Gregory J. Chaitin	Register allocation and spilling via graph coloring (with retrospective)	Best of PLDI	1982	DBLP DOI BibTeX RDF
31	David R. Ditzel, Hubert R. McLellan	Register Allocation for Free: The C Machine Stack Cache.	ASPLOS	1982	DBLP DOI BibTeX RDF
31	Philip Brisk, Majid Sarrafzadeh	Interference graphs for procedures in static single information form are interval graphs.	SCOPES	2007	DBLP DOI BibTeX RDF	k-colorable subgraph problem, linear scan register allocation, static single information (SSI) form, compilers, register allocation, interval graph
31	Xiaowei Li 0001, Toshimitsu Masuzawa, Hideo Fujiwara	Strong self-testability for data paths high-level synthesis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment
31	Andrzej Hlawiczka, Michal Kopec	Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	serial seeding, linear hybrid cellular automata, n-cell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, n-bit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flip-flops, flip-flops, shift registers, pattern generators, integrated circuit economics
31	Frank Mayer, Albrecht P. Stroele	A Versatile BIST Technique Combining Test Registers and Accumulators.	VLSI Design	2000	DBLP DOI BibTeX RDF	test register, built-in self-test, register-transfer level, accumulator
31	Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu	A MISR Computation Algorithm for Fast Signature Simulation.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	single-input signature register, memory-oriented policy, time-oriented policy, reverse zero-checking policy, Multiple-input signature register
31	Joan Carletta, Christos A. Papachristou	Structural constraints for circular self-test paths.	VTS	1995	DBLP DOI BibTeX RDF	circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits
31	David W. Wall	Experience with a Software-Defined Machine Architecture.	ACM Trans. Program. Lang. Syst.	1992	DBLP DOI BibTeX RDF	optimization, profiling, graph coloring, register allocation, RISC, pipeline scheduling, intermediate language, register windows, interprocedural
30	Weifeng Xu, Russell Tessier	Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
30	Ioannis E. Venetis, Guang R. Gao	Mapping the LU decomposition on a many-core architecture: challenges and solutions.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	register tiling, load balancing, multi-core, local memory, LU decomposition
30	Peter Koepke	Ordinal Computability.	CiE	2009	DBLP DOI BibTeX RDF	Ordinal machines, Infinite Time Register Machines, Constructible sets
30	Virgil Palanciuc, Dragos Badea	A Spill Code Minimization Technique-Application in the Metrowerks StarCore C Compiler.	Int. J. Parallel Program.	2004	DBLP DOI BibTeX RDF	rematerialization, Optimization, register allocation, spill code
30	Lal George, Matthias Blume	Taming the IXP network processor.	PLDI	2003	DBLP DOI BibTeX RDF	Intel IXA, bank assignment, programming languages, code generation, register allocation, integer linear programming, network processors
30	Christoph W. Keßler, Andrzej Bednarski	A Dynamic Programming Approach to Optimal Integrated Code Generation.	LCTES/OM	2001	DBLP DOI BibTeX RDF	integrated code generation, time profile, dynamic programming, register allocation, instruction scheduling, instruction selection
29	Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda	Power Reduction in VLIW Processor with Compiler Driven Bypass Network.	VLSI Design	2007	DBLP DOI BibTeX RDF
29	Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin	Speculative software management of datapath-width for energy optimization.	LCTES	2004	DBLP DOI BibTeX RDF	narrow-width regions, compiler, reconfigurable computing, speculative execution, energy management, clock-gating
29	Xiaotong Zhuang, Santosh Pande, John S. Greenland Jr.	A Framework for Parallelizing Load/Stores on Embedded Processors.	IEEE PACT	2002	DBLP DOI BibTeX RDF
29	Chii-Hwa Lee, Min-Shiang Hwang, Wei-Pang Yang	Enhanced privacy and authentication for the global system for mobile communications.	Wirel. Networks	1999	DBLP DOI BibTeX RDF
29	Luis Villa, Roger Espasa, Mateo Valero	Effective Usage of Vector Registers in Advanced Vector Architectures.	IEEE PACT	1997	DBLP DOI BibTeX RDF
29	Alfred V. Aho, Stephen C. Johnson, Jeffrey D. Ullman	Code Generation for Machines with Multiregister Operations.	POPL	1977	DBLP DOI BibTeX RDF
28	Brian R. Nickerson	Graph Coloring Register Allocation for Processors with Multi-Register Operands.	PLDI	1990	DBLP DOI BibTeX RDF	Intel 80960
27	Diego Figueira	Forward-XPath and extended register automata on data-trees.	ICDT	2010	DBLP DOI BibTeX RDF	alternating tree register automata, data-tree, forward XPath, infinite alphabet, unranked ordered tree, XML
27	Jongeun Lee, Aviral Shrivastava	A compiler optimization to reduce soft errors in register files.	LCTES	2009	DBLP DOI BibTeX RDF	architectural vulnerability factor, link-time optimization, embedded system, compilation, static analysis, soft error, register file
27	Insup Shin, Seungwhun Paik, Youngsoo Shin	Register allocation for high-level synthesis using dual supply voltages.	DAC	2009	DBLP DOI BibTeX RDF	low power, high-level synthesis, register allocation, dual supply voltage
27	Maziar Goudarzi, Tohru Ishihara	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asymmetric sram, leakage, instruction cache, register renaming
27	Han Liang, Piyush Mishra, Kaijie Wu 0001	Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy