Search results for "ATPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Makoto Sugihara, Hiroshi Date, Hiroto Yasuura	A novel test methodology for core-based system LSIs and a testing time minimization problem.	ITC	1998	DBLP DOI BibTeX RDF
9	Sandip Kundu	GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification.	ITC	1998	DBLP DOI BibTeX RDF
9	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee	An Implicit Algorithm for Finding Steady States and its Application to FSM Verification.	DAC	1998	DBLP DOI BibTeX RDF	model checking, verification, guided search
9	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo	Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	Wolfgang Kunz, Dominik Stoffel, Prem R. Menon	Logic optimization and equivalence checking by implication analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das	Delay Fault Coverage Enhancement Using Variable Observation Times.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	statistical delay fault coverage, delay test observation times, delay fault testing
9	Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton	Approximate timing analysis of combinational circuits under the XBD0 model.	ICCAD	1997	DBLP DOI BibTeX RDF	delay computation, timing analysis, False path
9	Chuan-Yu Wang, Kaushik Roy 0001	COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	CMOS Digital Circuits, Reliability, Power Estimation
9	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Fast identification of untestable delay faults using implications.	ICCAD	1997	DBLP DOI BibTeX RDF
9	Laura Farinetti, Pier Luca Montessoro	The Dynamic Rollback Problem in Concurrent Event-Driven Fault Simulation.	VTS	1997	DBLP DOI BibTeX RDF	Fault Simulation
9	Nur A. Touba, Bahram Pouya	Testing Embedded Cores Using Partial Isolation Rings.	VTS	1997	DBLP DOI BibTeX RDF	Intellectual Property Cores, Isolation Rings, Boundary Scan, Hill Climbing, Partial Scan, Embedded Cores, Digital Testing
9	Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs	Diagnostic Test Pattern Generation for Sequential Circuits.	VTS	1997	DBLP DOI BibTeX RDF
9	Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham	A Novel Solution for Chip-Level Functional Timing Verification.	VTS	1997	DBLP DOI BibTeX RDF	Chip-level Functional Timing Verification, Formal Verification techniques, Critical Path Analysis
9	Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Cellular automata for deterministic sequential test pattern generation.	VTS	1997	DBLP DOI BibTeX RDF	deterministic sequential test pattern generation, cellular automaton identification, hardware structure, area occupation, ASIC testing, evolutionary algorithm, cellular automata, BIST, fault coverage, stuck-at faults, FSM, deterministic automata
9	Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das	Delay Fault Coverage Enhancement Using Multiple Test Observation Times.	VLSI Design	1997	DBLP DOI BibTeX RDF
9	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
9	Angela Krstic, Kwang-Ting Cheng	Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits.	DAC	1997	DBLP DOI BibTeX RDF
9	Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal	Functional test generation for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
9	Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng	Perturb and simplify: multilevel Boolean network optimizer.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
9	Kowen Lai, Christos A. Papachristou	BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
9	Ghassan Al Hayek, Chantal Robach	On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification
9	Timothy John Lambert, Kewal K. Saluja	Methods for Dynamic Test Vector compaction in Sequential Test Generation.	VLSI Design	1996	DBLP DOI BibTeX RDF
9	Luis Entrena-Arrontes, Kwang-Ting Cheng	Combinational and sequential logic optimization by redundancy addition and removal.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Soo Young Lee, Kewal K. Saluja	Test application time reduction for sequential circuits with scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken	Efficient orthonormality testing for synthesis with pass-transistor selectors.	ICCAD	1995	DBLP DOI BibTeX RDF
9	Sujit Dey, Vijay Gangaram, Miodrag Potkonjak	A controller-based design-for-testability technique for controller-data path circuits.	ICCAD	1995	DBLP DOI BibTeX RDF
9	Hussain Al-Asaad, John P. Hayes	Design verification via simulation and automatic test pattern generation.	ICCAD	1995	DBLP DOI BibTeX RDF	test generation, logic simulation, Design verification, error models
9	Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham	Efficient multisine testing of analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits
9	Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal	Functional test generation for non-scan sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, functional test vectors, growth and disappearance fault model, complete stuck fault coverage, algebraic transformations, synthesized FSMs, VLSI, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, automatic testing, functional test generation
9	Jaushin Lee, Janak H. Patel	Architectural level test generation for microprocessors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
9	Eric Felt, Alberto L. Sangiovanni-Vincentelli	Testing of analog systems using behavioral models and optimal experimental design techniques.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Shih-Chieh Chang, Malgorzata Marek-Sadowska	Perturb and simplify: multi-level boolean network optimizer.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi	Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
9	Eun Sei Park, M. Ray Mercer	An efficient delay test generation system for combinational logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
9	Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham	Test compaction for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
9	Robert C. Aitken	Diagnosis of leakage faults with IDDQ.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	leakage fault model, Fault diagnosis, I DDQ testing
9	Arno Kunzmann, Hans-Joachim Wunderlich	An analytical approach to the partial scan problem.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	partial scan path, sequential test generation, design for testability
9	Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda	Diagnosis oriented test pattern generation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
9	Christian Jay	Experience in functional-level test generation and fault coverage in a silicon compiler.	EURO-DAC	1990	DBLP DOI BibTeX RDF