Search results for "3DIC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Chao Song, Minxuan Zhang	Improved access pattern for ROB soft error rate mitigation based on 3D integration technology.	3DIC	2015	DBLP DOI BibTeX RDF
1	Benjamin Vianne, Alexis Farcy, Vincent Fiori, Cédrick Chappaz, Norbert Chevrier, G. Lobascio, Pascal Chausse, F. Ponthenier, A. Ruckly, Stephanie Escoubas, Olivier Thomas	Stress management strategy to limit die curvature during silicon interposer integration.	3DIC	2015	DBLP DOI BibTeX RDF
1	Pornvitoo Rittinon, Ken Suzuki, Hideo Miura	Thermal stability of electroplated copper thin-film interconnections.	3DIC	2015	DBLP DOI BibTeX RDF
1	Yuan Yuan Dai, Mei Zhen Ng, P. Anantha, Chee Lip Gan, Chuan Seng Tan	Copper micro and nano particles mixture for 3D interconnections application.	3DIC	2015	DBLP DOI BibTeX RDF
1	Chung H. Lam	Neuromorphic semiconductor memory.	3DIC	2015	DBLP DOI BibTeX RDF
1	Hiroshi Taka, Katsumasa Suzuki, Norihiro Tsujioka, Shoichi Murakami	Development of high-quality low-temperature (≤ 120°C) PECVD-SiN films by organosilane.	3DIC	2015	DBLP DOI BibTeX RDF
1	Tomoharu Ogita	Invited talk: Technology and overview of Sony's 3D stacked CMOS image sensor.	3DIC	2015	DBLP DOI BibTeX RDF
1	Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi	Guard-ring monitoring system for inspecting defects in TSV-based data buses.	3DIC	2015	DBLP DOI BibTeX RDF
1	Hiroaki Ikeda, Shigenobu Sekine, Ryuji Kimura, Koichi Shimokawa, Keiji Okada, Hiroaki Shindo, Tatsuya Ooi, Rei Tamaki, Makoto Nagata	Nano-Function materials for TSV technologies.	3DIC	2015	DBLP DOI BibTeX RDF
1	Gamal Refai-Ahmed, Ivor Barber, Anthony Torza, Brian Philofsky	A holistic view of chip-level thermal architecture from heterogeneous stacked dice to system level in telecoms applications.	3DIC	2015	DBLP DOI BibTeX RDF
1	Isao Sugaya, Hajime Mitsuishi, Hidehiro Maeda, Kazuya Okamoto	New precision wafer bonding technologies for 3DIC.	3DIC	2015	DBLP DOI BibTeX RDF
1	Shuuichi Kariyazaki, Kenichi Kuboyama, Ryuichi Oikawa, Takuo Funaya	New signal skew cancellation method for 2 Gbps transmission in glass and organic interposers to achieve 2.5D package employing next generation high bandwidth memory (HBM).	3DIC	2015	DBLP DOI BibTeX RDF
1	K. W. Lee, Chisato Nagai, Ai Nakamura, Hiroki Aizawa, Ji Chel Bea, Mitsumasa Koyanagi, Hideto Hashiguchi, Takafumi Fukushima, Tanaka Tanaka	Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers.	3DIC	2015	DBLP DOI BibTeX RDF
1	Susheela Narasimhan	Power tile optimization and packaging for efficient temperature management of ASIC's in networking applications.	3DIC	2015	DBLP DOI BibTeX RDF
1	Arun Raghupathy, Hoa Do, Brian Philofsky, Gamal Refai-Ahmed	Best engineering practice for thermal characterization of stacked dice FPGA devices.	3DIC	2015	DBLP DOI BibTeX RDF
1	Joungho Kim	Active Si interposer for 3D IC integrations.	3DIC	2015	DBLP DOI BibTeX RDF
1	Cui Huang, Dong Wu, Liyang Pan, Zheyao Wang	Air-gap/SiO2 liner TSVs with improved electrical performance.	3DIC	2015	DBLP DOI BibTeX RDF
1	Asisa Kumar Panigrahi, Satish Bonam, Tamal Ghosh, Siva Rama Krishna Vanjari, Shiv Govind Singh	Long term efficacy of ultra-thin Ti passivation layer for achieving low temperature, low pressure Cu-Cu Wafer-on-Wafer bonding.	3DIC	2015	DBLP DOI BibTeX RDF
1	Shogo Hachiya, Takahiro Onagi, Sheyang Ning, Ken Takeuchi	Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory.	3DIC	2015	DBLP DOI BibTeX RDF
1	Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto	Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers.	3DIC	2015	DBLP DOI BibTeX RDF
1	Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne	Processing active devices on Si interposer and impact on cost.	3DIC	2015	DBLP DOI BibTeX RDF
1	Eric Beyne	3D system integration research at IMEC.	3DIC	2015	DBLP DOI BibTeX RDF
1	Wei-Chung Lo	3D research activities in ITRI.	3DIC	2015	DBLP DOI BibTeX RDF
1	Hisashi Kino, Hideto Hashiguchi, Seiya Tanikawa, Yohei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka	Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC.	3DIC	2015	DBLP DOI BibTeX RDF
1	Tadashi Kamada	The issues of automated driving vehicle and the expectations for 3D integration technology.	3DIC	2015	DBLP DOI BibTeX RDF
1	Gaël Pillonnet, Nicolas Jeanniot, Pascal Vivet	3D ICs: An opportunity for fully-integrated, dense and efficient power supplies.	3DIC	2015	DBLP DOI BibTeX RDF
1	Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka	Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors.	3DIC	2015	DBLP DOI BibTeX RDF
1	R. Ranga Reddy, Sugandh Tanna, Shiv Govind Singh, Om Krishna Singh	TSV noise coupling in 3D IC using guard ring.	3DIC	2015	DBLP DOI BibTeX RDF
1	Mostafizur Rahman, Santosh Khasanvis, Jiajun Shi, Mingyu Li, Csaba Andras Moritz	Fine-grained 3-D integrated circuit fabric using vertical nanowires.	3DIC	2015	DBLP DOI BibTeX RDF
1	Ryo Takigawa, Kohei Nitta, Akihiro Ikeda, Mitsuaki Kumazawa, Toshiharu Hirai, Michio Komatsu, Tanemasa Asano	High-speed via hole filling using electrophoresis of Ag nanoparticles.	3DIC	2015	DBLP DOI BibTeX RDF
1	Yang Zhang, Thomas E. Sarvey, Muhannad S. Bakir	Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation.	3DIC	2014	DBLP DOI BibTeX RDF
1	Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa	Modeling of substrate contacts in TSV-based 3D ICs.	3DIC	2014	DBLP DOI BibTeX RDF
1	Jing Tao, Alan Mathewson, Kafil M. Razeeb	Bumpless interconnects formed with nanowire ACF for 3D applications.	3DIC	2014	DBLP DOI BibTeX RDF
1	Andrzej Kociubinski, M. Duk, Tomasz Bieniek, Grzegorz Janczyk, Michal Borecki	Innovative SiC over Si photodiode based dual-band, 3D integrated detector.	3DIC	2014	DBLP DOI BibTeX RDF
1	Joeri De Vos, Vladimir Cherman, Mikael Detalle, Teng Wang, Abdellah Salahouelhadj, Robert Daily, Geert Van der Plas, Eric Beyne	Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges.	3DIC	2014	DBLP DOI BibTeX RDF
1	Yann Beilliard, Stéphane Moreau, Léa Di Cioccio, Perceval Coudrain, G. Romano, A. Nowodzinski, F. Aussenac, P.-H. Jouneau, E. Rolland, Thomas Signamarcheix	Advances toward reliable high density Cu-Cu interconnects by Cu-SiO2 direct hybrid bonding.	3DIC	2014	DBLP DOI BibTeX RDF
1	Youngwoo Kim, Jonghyun Cho, Kiyeong Kim, Heegon Kim, Joungho Kim, Srikrishna Sitaraman, Venky Sundaram, Rao R. Tummala	Analysis and optimization of a power distribution network in 2.5D IC with glass interposer.	3DIC	2014	DBLP DOI BibTeX RDF
1	Sonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez	Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation.	3DIC	2014	DBLP DOI BibTeX RDF
1	K. W. Lee, Chisato Nagai, Ai Nakamura, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tanaka Tanaka, Mitsumasa Koyanagi	Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV.	3DIC	2014	DBLP DOI BibTeX RDF
1	Qiaosha Zou, Jia Zhan, Fen Ge, Matt Poremba, Yuan Xie 0001	Designing vertical bandwidth reconfigurable 3D NoCs for many core systems.	3DIC	2014	DBLP DOI BibTeX RDF
1	Cristiano Santos, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Augusto da Luz Reis	Thermal performance of 3D ICs: Analysis and alternatives.	3DIC	2014	DBLP DOI BibTeX RDF
1	Keiji Matsumoto, Hiroyuki Mori, Yasumitsu Orii	Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack.	3DIC	2014	DBLP DOI BibTeX RDF
1	Daniel Nilsen Wright, Maaike M. Visser Taklo, Astrid-Sofie B. Vardøy, Helge Kristiansen	Metal coated polymer spheres for compliant fine pitch ball grid arrays.	3DIC	2014	DBLP DOI BibTeX RDF
1	James F. Rohan, Declan Casey, Monika Zygowska, Michael Moore, Brian Shanahan	Electroless metal deposition for IC and TSV applications.	3DIC	2014	DBLP DOI BibTeX RDF
1	Masayuki Sato 0001, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	On-chip checkpointing with 3D-stacked memories.	3DIC	2014	DBLP DOI BibTeX RDF
1	Paul D. Franzon, Eric Rotenberg, James Tuck 0001, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, Steve Lipa, Chao Li 0004, Jong Beom Park, Joshua Schabel	3D-enabled customizable embedded computer (3DECC).	3DIC	2014	DBLP DOI BibTeX RDF
1	Randy Widialaksono, Wenxu Zhao, W. Rhett Davis, Paul D. Franzon	Leveraging 3D-IC for on-chip timing uncertainty measurements.	3DIC	2014	DBLP DOI BibTeX RDF
1	Cristiano Santos, Papa Momar Souare, François de Crecy, Perceval Coudrain, Jean-Philippe Colonna, Pascal Vivet, Andras Borbely, Ricardo Reis 0001, M. Haykel Ben Jamaa, Vincent Fiori, Alexis Farcy	Using TSVs for thermal mitigation in 3D circuits: Wish and truth.	3DIC	2014	DBLP DOI BibTeX RDF
1	Robert Fischbach, Andy Heinig, Peter Schneider	Design rule check and layout versus schematic for 3D integration and advanced packaging.	3DIC	2014	DBLP DOI BibTeX RDF
1	Mariappan Murugesan, Takafumi Fukushima, Ji Chel Bea, K. W. Lee, Mitsu Koyanagi, Y. Imai, S. Kimura, Tetsu Tanaka	Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI.	3DIC	2014	DBLP DOI BibTeX RDF
1	Tomasz Bieniek, Grzegorz Janczyk, Magdalena Ekwinska, T. Budzynski, Piotr Gluszko, Piotr Grabiec, Andrzej Kociubinski	Novel methodology for 3D MEMS-IC design and co-simulation on MEMS microphone smart system example.	3DIC	2014	DBLP DOI BibTeX RDF
1		2014 International 3D Systems Integration Conference, 3DIC 2014, Kinsdale, Ireland, December 1-3, 2014	3DIC	2014	DBLP BibTeX RDF
1	Ricky Anthony, Santosh Kulkarni, Ningning Wang, Seán Cian O'Mathuna	Advanced processing for high efficiency inductors for 2.5D/3D Power Supply in Package.	3DIC	2014	DBLP DOI BibTeX RDF
1	Armin Grünewald, Michael G. Wahl, Rainer Brück 0001	Manufacturing and test assistance for 3D-Integrated heterogeneous systems.	3DIC	2014	DBLP DOI BibTeX RDF
1	Severin Zimmermann, Thomas Brunschwiler, Brian R. Burg, Jonas Zuercher, Guo Hong, Dimos Poulikakos, Mario Baum, Christian Hofmann	Characterization of particle beds in percolating thermal underfills based on centrifugation.	3DIC	2014	DBLP DOI BibTeX RDF
1	Chaoqi Zhang 0001, Paragkumar Thadesar, Muneeb Zia, Thomas E. Sarvey, Muhannad S. Bakir	Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnects.	3DIC	2014	DBLP DOI BibTeX RDF
1	Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi	Analysis of thermal stress distribution for TSV with novel structure.	3DIC	2014	DBLP DOI BibTeX RDF
1	Oded Raz, Pinxiang Duan, Harm J. S. Dorren	Simple and low cost technique for stacking known good dies to create compact 3D stacked parallel optics assemblies.	3DIC	2014	DBLP DOI BibTeX RDF
1	Katsuya Kikuchi, Masahiro Aoyagi, Masaaki Ujiie, Shinya Takayama	Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI system.	3DIC	2014	DBLP DOI BibTeX RDF
1	Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu	A built-in supply current test circuit for electrical interconnect tests of 3D ICs.	3DIC	2014	DBLP DOI BibTeX RDF
1	X. Sun, Geert Van der Plas, Mikael Detalle, Eric Beyne	Analysis of 3D interconnect performance: Effect of the Si substrate resistivity.	3DIC	2014	DBLP DOI BibTeX RDF
1	Dorota S. Temple, Dean Malta, Erik P. Vick, Matthew R. Lueck, Scott H. Goodwin, Mark S. Muzilla, Christopher M. Masterjohn, Mark R. Skokan	Advanced 3D mixed-signal processor for infrared focal plane arrays: Fabrication and test.	3DIC	2014	DBLP DOI BibTeX RDF
1	Emma Kowalczuk, Arnab Bhattacharya 0007, Ka Chung Lee, Jesse Alton, Martin Igarashi, Stephane Barbeau	Fault localisation of defects using Electro Optical Terahertz Pulse Reflectometry and 3D EM modelling with Virtual Known Good Device.	3DIC	2014	DBLP DOI BibTeX RDF
1	Fumihiro Inoue, Harold Philipsen, Marleen H. van der Veen, Kevin Vandersmissen, Stefaan Van Huylenbroeck, Herbert Struyf, Tetsu Tanaka	Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias.	3DIC	2014	DBLP DOI BibTeX RDF
1	Bui Thanh Tung 0001, Xiaojin Cheng, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Masahiro Aoyagi	Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration.	3DIC	2014	DBLP DOI BibTeX RDF
1	Takafumi Fukushima, Yuka Ito, Mariappan Murugesan, Jicheol Bea, Kang Wook Lee 0002, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi	Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration.	3DIC	2014	DBLP DOI BibTeX RDF
1	Mehdi Saedi, Kambiz Samadi, Arpit Mittal, Rajat Mittal	Thermal implications of mobile 3D-ICs.	3DIC	2014	DBLP DOI BibTeX RDF
1	Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi	An impact of circuit scale on the performance of 3-D stacked arithmetic units.	3DIC	2014	DBLP DOI BibTeX RDF
1	Khadim Dieng, Philippe Artillan, Cédric Bermond, Olivier Guiller, Thierry Lacrevaz, Sylvain Joblot, Gregory Houzet, Alexis Farcy, Yann Lamy, Bernard Fléchet	Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposer.	3DIC	2014	DBLP DOI BibTeX RDF
1	Yoriko Mizushima, Young-Suk Kim, Tomoji Nakamura, Shoichi Kodama, Nobuhide Maeda, Koji Fujimoto, Takayuki Ohba	Impact of Thermomechanical Stresses on Ultra-thin Si Stacked Structure.	3DIC	2014	DBLP DOI BibTeX RDF
1	Naoya Watanabe, Masahiro Aoyagi, Daisuke Katagawa, Tsubasa Bandoh, Takahiko Mitsui, Eiichi Yamamoto	Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal.	3DIC	2014	DBLP DOI BibTeX RDF
1	Young Sik Song, Yunho Han, Tai Hong Yim	Conventional magnetron sputtering of metal seed layers on high aspect ratio vias with tilting.	3DIC	2014	DBLP DOI BibTeX RDF
1	T. Robert Harris, Paul D. Franzon, W. Rhett Davis, Lee Wang	Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits.	3DIC	2014	DBLP DOI BibTeX RDF
1	Daniel H. Jung, Heegon Kim, Jonghoon J. Kim, Sukjin Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi	Fault detection and isolation of multiple defects in through silicon via (TSV) channel.	3DIC	2014	DBLP DOI BibTeX RDF
1	Qiaosha Zou, Matt Poremba, Yuan Xie 0001	A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests.	3DIC	2014	DBLP DOI BibTeX RDF
1	Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi	Substrate monitoring system for inspecting defects in TSV-based data buses.	3DIC	2014	DBLP DOI BibTeX RDF
1	Jonghoon J. Kim, Bumhee Bae, Sukjin Kim, Sunkyu Kong, Heegon Kim, Daniel H. Jung, Joungho Kim	Magnetically-coupled current probing structure consisting of TSVs and RDLs in 2.5D and 3D ICs.	3DIC	2014	DBLP DOI BibTeX RDF
1	Hong-Yeol Lim, Min-Kwan Kee, Gi-Ho Park	Phase detection based data prefetching for utilizing memory bandwidth of 3D integrated circuits.	3DIC	2013	DBLP DOI BibTeX RDF
1	Bei Zhang, Baohu Li, Vishwani D. Agrawal	Yield analysis of a novel wafer manipulation method in 3D stacking.	3DIC	2013	DBLP DOI BibTeX RDF
1	Zhenqian Zhang, Brandon Noia, Krishnendu Chakrabarty, Paul D. Franzon	Face-to-face bus design with built-in self-test in 3D ICs.	3DIC	2013	DBLP DOI BibTeX RDF
1	Keiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka, Katsuyuki Sakuma, Hidekazu Kikuchi, Hiroyuki Mori, Yasumitsu Orii, Fumiaki Yamada, Kohei Fujihara, Junichi Takamatsu, Koji Kondo	Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack.	3DIC	2013	DBLP DOI BibTeX RDF
1	Julia Hsin-Lin Lu, Wing-Fai Loke, Dimitrios Peroulis, Byunghoo Jung	Implementing wireless communication links in 3-D ICs utilizing wide-band on-chip meandering microbump antenna.	3DIC	2013	DBLP DOI BibTeX RDF
1	Kouji Kiyoyama, Y. Sato, Hiroyuki Hashimoto, Kang Wook Lee 0002, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi	A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor.	3DIC	2013	DBLP DOI BibTeX RDF
1	Katsuya Kikuchi, Fumiki Kato, Shunsuke Nemoto, Hiroshi Nakagawa, Masahiro Aoyagi, Youtaro Yasu, Kohji Koshiji	Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging.	3DIC	2013	DBLP DOI BibTeX RDF
1	Tiantao Lu, Ankur Srivastava 0001	Detailed electrical and reliability study of tapered TSVs.	3DIC	2013	DBLP DOI BibTeX RDF
1	William Wahby, Ashish Dembla, Muhannad S. Bakir	Evaluation of 3DICs and fabrication of monolithic interlayer vias.	3DIC	2013	DBLP DOI BibTeX RDF
1	Thorbjorn Ebefors, Jessica Fredlund, Daniel Perttu, Raymond van Dijk, Lorenzo Cifola, Mikko Kaunisto, Pekka Rantakari, Tauno Vaha-Heikkila	The development and evaluation of RF TSV for 3D IPD applications.	3DIC	2013	DBLP DOI BibTeX RDF
1	Zvi Or-Bach	The monolithic 3D advantage: Monolithic 3D is far more than just an alternative to 0.7x scaling.	3DIC	2013	DBLP DOI BibTeX RDF
1	Hiroyuki Hashimoto, Takafumi Fukushima, Kang Wook Lee 0002, Mitsumasa Koyanagi, Tetsu Tanaka	Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system.	3DIC	2013	DBLP DOI BibTeX RDF
1	Zhenqian Zhang, Paul D. Franzon	TSV-based, modular and collision detectable face-to-back shared bus design.	3DIC	2013	DBLP DOI BibTeX RDF
1	Nahid M. Hossain, MunEm Hossain, Abdul Hamid Bin Yousuf, Masud H. Chowdhury	Thermal aware Graphene based Through Silicon Via design for 3D IC.	3DIC	2013	DBLP DOI BibTeX RDF
1	Jonghoon J. Kim, Heegon Kim, Sukjin Kim, Bumhee Bae, Daniel H. Jung, Sunkyu Kong, Joungho Kim, Junho Lee, Kunwoo Park	Non-contact wafer-level TSV connectivity test methodology using magnetic coupling.	3DIC	2013	DBLP DOI BibTeX RDF
1	Mariappan Murugesan, Jichoel Bea, Kang Wook Lee 0002, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi, Yuji Sutou, H. Wang, J. Koike	Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV.	3DIC	2013	DBLP DOI BibTeX RDF
1	Rene Puschmann, Mathias Bottcher, Irene Bartusseck, Frank Windrich, Conny Fiedler, Peggy John, Charles Alix Manier, Kai Zoschke, Jurgen Grafe, Hermann Oppermann, Jürgen Wolf, K. Dieter Lang, Michael Ziesmann	3D integration of standard integrated circuits.	3DIC	2013	DBLP DOI BibTeX RDF
1	Melanie Brocard, Cédric Bermond, Thierry Lacrevaz, Alexis Farcy, Patrick Le Maitre, P. Scheer, Patrick Leduc, Séverine Cheramy, Bernard Fléchet	RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits.	3DIC	2013	DBLP DOI BibTeX RDF
1	Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri, Hafizur Rahaman 0001	Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing.	3DIC	2013	DBLP DOI BibTeX RDF
1	Jason Chew, Uday Mahajan, Rajeev Bajaj, Iad Mirshad, Robert Newcomb 0002	Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination.	3DIC	2013	DBLP DOI BibTeX RDF
1	Jason Chew, Uday Mahajan, Rajeev Bajaj, Iad Mirshad, Robert Newcomb 0002	Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination.	3DIC	2013	DBLP DOI BibTeX RDF
1	Osamu Nukaga, Tatsuya Shioiri, Satoshi Yamamoto, Tatsuo Suemasu	Glass interposer with high-density three-dimensional structured TGV for 3D system integration.	3DIC	2013	DBLP DOI BibTeX RDF
1	Akihiro Ikeda, L. J. Qiu, K. Nakahara, Tanemasa Asano	Surface passivation of Cu cone bump by self-assembled-monolayer for room temperature Cu-Cu bonding.	3DIC	2013	DBLP DOI BibTeX RDF

Publications at "3DIC"( http://dblp.L3S.de/Venues/3DIC )