Search results for "caches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Shuai Wang 0006, Jie S. Hu, Sotirios G. Ziavras	Self-Adaptive Data Caches for Soft-Error Reliability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
25	Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer	Adaptive insertion policies for managing shared caches.	PACT	2008	DBLP DOI BibTeX RDF	set dueling, shared cache, replacement, cache partitioning
25	Tanu Malik, Xiaodan Wang, Randal C. Burns, Debabrata Dash, Anastasia Ailamaki	Automated physical design in database caches.	ICDE Workshops	2008	DBLP DOI BibTeX RDF
25	Jun Yan 0008, Wei Zhang 0002	WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF
25	Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail	Thermal Management of On-Chip Caches Through Power Density Minimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
25	Peter Petrov, Alex Orailoglu	Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	software-controlled caching, Embedded systems, low-power, memory management, cache organization
25	Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlke	Compiler-managed partitioned data caches for low power.	LCTES	2007	DBLP DOI BibTeX RDF	hardware/software co-managed cache, instruction-driven cache management, partitioned cache, low-power, embedded processor
25	Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares	Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors.	PACT	2007	DBLP DOI BibTeX RDF
25	Madhu Mutyam, Narayanan Vijaykrishnan	Working with process variation aware caches.	DATE	2007	DBLP DOI BibTeX RDF
25	Mrinmoy Ghosh, Hsien-Hsin S. Lee	Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems.	ICPADS	2007	DBLP DOI BibTeX RDF
25	Sungjune Youn, Hyunhee Kim, Jihong Kim 0001	A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.	ISLPED	2007	DBLP DOI BibTeX RDF	chip multiprocessors (CMPS), performance, embedded systems, architecture, low-power, L2 cache
25	Houman Homayoun, Alexander V. Veidenbaum	Reducing leakage power in peripheral circuits of L2 caches.	ICCD	2007	DBLP DOI BibTeX RDF
25	Fernando Duarte, Fabrício Benevenuto, Virgílio A. F. Almeida, Jussara M. Almeida	Locality of Reference in an Hierarchy of Web Caches.	Networking	2006	DBLP DOI BibTeX RDF	entropy, Web caching, locality of reference
25	Keshavan Varadarajan, S. K. Nandy 0001, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer 0001, Srihari Makineni, Donald Newell	Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions.	MICRO	2006	DBLP DOI BibTeX RDF
25	Georgios Keramidas, Konstantinos Aisopos, Stefanos Kaxiras	Dynamic Dictionary-Based Data Compression for Level-1 Caches.	ARCS	2006	DBLP DOI BibTeX RDF
25	Dinesh C. Suresh, Walid A. Najjar, Jun Yang 0002	Power Efficient Instruction Caches for Embedded Systems.	SAMOS	2005	DBLP DOI BibTeX RDF
25	Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail	Thermal Management of On-Chip Caches Through Power Density Minimization.	MICRO	2005	DBLP DOI BibTeX RDF
25	Won-Ho Park, Andreas Moshovos, Babak Falsafi	RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free".	ICCD	2005	DBLP DOI BibTeX RDF
25	Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge	Total leakage optimization strategies for multi-level caches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, cache memory, gate leakage
25	Kimish Patel, Enrico Macii, Massimo Poncino	Zero clustering: an approach to extend zero compression to instruction caches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	clustering, compression, permutation, application-specific
25	Peter Petrov, Daniel Tracy, Alex Orailoglu	Energy-effcient physically tagged caches for embedded processors with virtual memory.	DAC	2005	DBLP DOI BibTeX RDF
25	Jiaxin J. Gao, Dallan Quass, Yiu-Kai Ng	Selective-Splitting and Cache-Maintenance Algorithms for Associative-Client Caches.	Distributed Parallel Databases	2004	DBLP DOI BibTeX RDF	selective splitting, associative-client cache, cache maintenance/behaviors, invalid access prevention
25	Chuanjun Zhang, Jun Yang 0002, Frank Vahid	Low Static-Power Frequent-Value Data Caches.	DATE	2004	DBLP DOI BibTeX RDF
25	Yingmin Li, Dharmesh Parikh, Yan Zhang 0028, Karthik Sankaranarayanan, Mircea R. Stan, Kevin Skadron	State-Preserving vs. Non-State-Preserving Leakage Control in Caches.	DATE	2004	DBLP DOI BibTeX RDF
25	Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger	Static energy reduction techniques for microprocessor caches.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
25	Khalil Amiri, Sanghyun Park, Renu Tewari, Sriram Padmanabhan	Scalable template-based query containment checking for web semantic caches.	ICDE	2003	DBLP DOI BibTeX RDF
25	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor.	DATE	2003	DBLP DOI BibTeX RDF
25	Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau	Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors.	DATE	2003	DBLP DOI BibTeX RDF
25	Bradford M. Beckmann, David A. Wood 0001	TLC: Transmission Line Caches.	MICRO	2003	DBLP DOI BibTeX RDF
25	Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu	Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.	PACS	2003	DBLP DOI BibTeX RDF
25	Xavier Vera, Björn Lisper, Jingling Xue	Data Caches in Multitasking Hard Real-Time Systems.	RTSS	2003	DBLP DOI BibTeX RDF
25	George Karakostas, Dimitrios N. Serpanos	Exploitation of different types of locality for Web caches.	ISCC	2002	DBLP DOI BibTeX RDF
25	Ahmed Amer, Darrell D. E. Long, Randal C. Burns	Group-Based Management of Distributed File Caches.	ICDCS	2002	DBLP DOI BibTeX RDF
25	James Giles, Reiner Sailer, Dinesh C. Verma, Suresh Chari	Authentication for Distributed Web Caches.	ESORICS	2002	DBLP DOI BibTeX RDF	Security, Authentication, Distributed Applications, CDN, Cookies
25	Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.	HPCA	2001	DBLP DOI BibTeX RDF
25	Harry Dwyer, John Fernando	Establishing a tight bound on task interference in embedded system instruction caches.	CASES	2001	DBLP DOI BibTeX RDF
25	Emmanuel Cecchet	Parallel Pull-Based LRU: A Request Distribution Algorithm for Clustered Web Caches Using a DSM for Memory Mapped Networks.	CCGRID	2001	DBLP DOI BibTeX RDF
25	Marian Stanca, Stamatis Vassiliadis, Sorin Cotofana, Henk Corporaal	Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note).	Euro-Par	2000	DBLP DOI BibTeX RDF
25	Maged M. Michael, Ashwini K. Nanda	Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors.	HPCA	1999	DBLP DOI BibTeX RDF
25	Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos	An analytical, transistor-level energy model for SRAM-based caches.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
25	Kun-Lung Wu, Philip S. Yu	Load Balancing and Hot Spot Relief for Hash Routing among a Collection of Proxy Caches.	ICDCS	1999	DBLP DOI BibTeX RDF	adaptable controlled replication, hot spot relief, CARP, hash routing, load balancing
25	Kuang-Chih Liu, Chung-Ta King	A Performance Study on Bounteous Transfer in Multiprocessor Sectored Caches.	J. Supercomput.	1997	DBLP DOI BibTeX RDF	sectored cache, partial block invalidation, multiprocessor, Cache coherence, data prefetching, false sharing
25	Yuguang Wu, Richard R. Muntz	Stack Evaluation of Arbitrary Set-Associative Multiprocessor Caches.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	coherence by invalidation, stack evaluation, simulation, Cache memory, set-associative
25	Jeffrey D. Gee, Alan Jay Smith	The effectiveness of caches for vector processors.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF
25	Senthil Krishnamoorthy, Alok N. Choudhary	An Evaluation of Set-Associativity in Two-Level Caches for Shared Memory Multiprocessors.	PARLE	1992	DBLP DOI BibTeX RDF
25	Urs Hölzle, Craig Chambers, David M. Ungar	Optimizing Dynamically-Typed Object-Oriented Languages With Polymorphic Inline Caches.	ECOOP	1991	DBLP DOI BibTeX RDF
25	James R. Goodman	Coherency for Multiprocessor Virtual Address Caches.	ASPLOS	1987	DBLP DOI BibTeX RDF
25	Ramya Prabhakar, Shekhar Srikantaiah, Mahmut T. Kandemir, Christina M. Patrick	Adaptive multi-level cache allocation in distributed storage architectures.	ICS	2010	DBLP DOI BibTeX RDF	SLO, I/O, multi-server, multi-level, storage cache
25	Enric Herrero, José González 0002, Ramon Canal	Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.	ISCA	2010	DBLP DOI BibTeX RDF	elastic cooperative caching, tiled microarchitectures, chip multiprocessors, memory hierarchy
25	Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	ZerehCache: armoring cache architectures in high defect density technologies.	MICRO	2009	DBLP DOI BibTeX RDF	fault-tolerant cache, process variation, manufacturing yield
25	Yu Chen, Wenlong Li, Changkyu Kim, Zhizhong Tang	Efficient shared cache management through sharing-aware replacement and streaming-aware insertion policy.	IPDPS	2009	DBLP DOI BibTeX RDF
25	Xiaoxia Wu, Jian Li 0059, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie 0001	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
25	Jason Zebchuk, Srihari Makineni, Donald Newell	Re-examining cache replacement policies.	ICCD	2008	DBLP DOI BibTeX RDF
25	Rakesh Reddy, Peter Petrov	Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems.	CASES	2007	DBLP DOI BibTeX RDF	real-time embedded systems, cache interference
25	Ahmad Zmily, Christos Kozyrakis	A low power front-end for embedded processors using a block-aware instruction set.	CASES	2007	DBLP DOI BibTeX RDF	instruction re-ordering, low power front-end, software hints, tagless instruction cache, unified instruction cache and BTB, instruction prefetching
25	Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan	Improving the reliability of on-chip L2 cache using redundancy.	ICCD	2007	DBLP DOI BibTeX RDF
25	Manish Verma, Peter Marwedel	Overlay techniques for scratchpad memories in low power embedded processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
25	Michele Co, Dee A. B. Weikle, Kevin Skadron	Evaluating trace cache energy efficiency.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	fetch engine energy efficiency, Trace cache
25	Vilas Sridharan, Hossein Asadi 0001, Mehdi Baradaran Tahoori, David R. Kaeli	Reducing Data Cache Susceptibility to Soft Errors.	IEEE Trans. Dependable Secur. Comput.	2006	DBLP DOI BibTeX RDF	refresh, refetch, Fault tolerance, reliability, cache memories, soft errors, error modeling
25	Aamer Jaleel, Matthew Mattina, Bruce L. Jacob	Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads.	HPCA	2006	DBLP DOI BibTeX RDF
25	Badrish Chandramouli, Jun Yang 0001, Amin Vahdat	Distributed Network Querying with Bounded Approximate Caching.	DASFAA	2006	DBLP DOI BibTeX RDF
25	Harini Ramaprasad, Frank Mueller 0001	Tightening the Bounds on Feasible Preemption Points.	RTSS	2006	DBLP DOI BibTeX RDF
25	Harini Ramaprasad, Frank Mueller 0001	Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
25	Jichuan Chang, Gurindar S. Sohi	Cooperative Caching for Chip Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
25	Yue Luo, Lizy Kurian John, Lieven Eeckhout	SMA: A Self-Monitored Adaptive Cache Warm-Up Scheme for Microprocessor Simulation.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	Microprocessor simulation, cache warm-up, simulation time reduction, sampling
25	Jan Staschulat, Rolf Ernst	Scalable precision cache analysis for preemptive scheduling.	LCTES	2005	DBLP DOI BibTeX RDF	scheduling, embedded systems, cache, worst case execution time analysis
25	Lars Wehmeyer, Peter Marwedel	Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software.	DATE	2005	DBLP DOI BibTeX RDF
25	Theo Härder	Caching over the Entire User-to-Data Path in the Internet.	Data Management in a Connected World	2005	DBLP DOI BibTeX RDF
25	Sujaa Rani Mohan, E. K. Park, Yijie Han	Association Rule-Based Data Mining Agents for Personalized Web Caching.	COMPSAC (2)	2005	DBLP DOI BibTeX RDF
25	Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke	Automated data cache placement for embedded VLIW ASIPs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	cache, ASIP, cache optimization, embedded applications
25	Chuanjun Zhang	An efficient direct mapped instruction cache for application-specific embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	efficient cache design, instruction cache, low power cache
25	Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt	Compilation techniques for energy reduction in horizontally partitioned cache architectures.	CASES	2005	DBLP DOI BibTeX RDF	XScale, horizontally-partitioned cache, mini-cache, split cache, compiler, energy, data cache
25	Harini Ramaprasad, Frank Mueller 0001	Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
25	Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras	Implementing branch-predictor decay using quasi-static memory cells.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Energy aware computing
25	Muhamed F. Mudawar	Scalable cache memory design for large-scale SMT architectures.	WMPI	2004	DBLP DOI BibTeX RDF	scalable multiported cache memory, simultaneous multithreaded architectures
25	Arindam Mallik, Gokhan Memik	A Case for Clumsy Packet Processors.	MICRO	2004	DBLP DOI BibTeX RDF
25	Chunrong Lai, Shih-Lien Lu	Efficient Victim Mechanism on Sector Cache Organization.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
25	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
25	Yue Luo, Lizy Kurian John, Lieven Eeckhout	Self-Monitored Adaptive Cache Warm-Up for Microprocessor Simulation.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
25	Ed T. Upchurch, Thomas L. Sterling, Jay B. Brockman	Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs.	SC	2004	DBLP DOI BibTeX RDF
25	Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt	Cache Scrubbing in Microprocessors: Myth or Necessity?	PRDC	2004	DBLP DOI BibTeX RDF
25	Gokhan Memik, Glenn Reinman, William H. Mangione-Smith	Just Say No: Benefits of Early Cache Miss Determinatio.	HPCA	2003	DBLP DOI BibTeX RDF
25	Mohan G. Kabadi, Ranjani Parthasarathi	Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
25	Zhigang Hu, Philo Juang, Kevin Skadron, Douglas W. Clark, Margaret Martonosi	Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.	ICCD	2002	DBLP DOI BibTeX RDF
25	Ashutosh S. Dhodapkar, James E. Smith 0001	Managing Multi-Configuration Hardware via Dynamic Working Set Analysis.	ISCA	2002	DBLP DOI BibTeX RDF
25	Yiming Hu, Qing Yang 0001, Tycho Nightingale	RAPID-Cache - A Reliable and Inexpensive Write Cache for Disk I/O Systems.	HPCA	1999	DBLP DOI BibTeX RDF
25	Renu Tewari, Michael Dahlin, Harrick M. Vin, Jonathan S. Kay	Design Considerations for Distributed Caching on the Internet.	ICDCS	1999	DBLP DOI BibTeX RDF	WWW, caching, cooperative caching, hint, hierarchical caching
25	Erik Hagersten, Mats Grindal, Anders Landin, Ashley Saulsbury, Bengt Werner, Seif Haridi	Simulating the Data Diffusion Machine.	PARLE	1993	DBLP DOI BibTeX RDF
25	Feipei Lai, Chyuan-Yow Wu, Tai-Ming Parng	A memory management unit and cache controller for the MARS system.	MICRO	1990	DBLP BibTeX RDF
25	Tam M. Nguyen, Vason P. Srini, Alvin M. Despain	A two-tier memory architecture for high-performance multiprocessor systems.	ICS	1988	DBLP DOI BibTeX RDF	Prolog, Prolog, CRAY X-MP
20	Frank McCown, Michael L. Nelson	Usage analysis of a public website reconstruction tool.	JCDL	2008	DBLP DOI BibTeX RDF	search engine caches, digital preservation, web archiving
20	Zhiyuan Li 0001	Simultaneous Minimization of Capacity and Conflict Misses.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	array padding, caches, optimizing compilers, loop transformation
20	Wenlong Li, Eric Q. Li, Aamer Jaleel, Jiulong Shan, Yurong Chen 0001, Qigang Wang, Ravi R. Iyer 0001, Ramesh Illikkal, Yimin Zhang 0002, Dong Liu, Michael Liao, Wei Wei, Jinhua Du	Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	DRAM caches, small-scale CMP, medium-scale CMP, large-scale CMP, hardware-software co-simulation, terabyte-level workloads, multithreaded data mining applications, cache design, memory performance, multicore systems, memory system performance
20	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparing memory systems for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches
20	Kamen Yotov, Keshav Pingali, Paul Stodghill	Automatic measurement of memory hierarchy parameters.	SIGMETRICS	2005	DBLP DOI BibTeX RDF	hardware parameters, optimization, caches, measurement, memory hierarchy, autonomic systems, self-tuning, micro-benchmarks
20	G. Edward Suh, Larry Rudolph, Srinivas Devadas	Dynamic Partitioning of Shared Cache Memory.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	CMP and SMT, shared caches, cache partitioning
20	Kaustubh Patil, Kiran Seth, Frank Mueller 0001	Compositional static instruction cache simulation.	LCTES	2004	DBLP DOI BibTeX RDF	scheduling, real-time systems, caches, worst-case execution time
20	Tony Givargis, Frank Vahid, Jörg Henkel	Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores.	ISSS	2000	DBLP DOI BibTeX RDF	silicon platforms, caches, low-power design, estimation, System-on-a-chip, intellectual property, cores, system parameters
20	Karlheinz Weiß, Thorsten Steckstor, Wolfgang Rosenstiel	Performance Analysis of a RTOS by Emulation of an Embedded System.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	VxWorks, SPYDER-CORE-P1, embedded system, caches, emulation, microcontroller, real-time operating system, RTOS, ASI
20	Georg Färber, Franz Fischer, Thomas Kolloch, Annette Muth	Improving processor utilization with a task classification model based application specific hard real-time architecture.	RTCSA	1997	DBLP DOI BibTeX RDF	task classification model, application specific hard real-time architecture, real-time architecture, target architecture framework, tightly coupled heterogeneous multiprocessor system, rapid prototyping platform, caches, pipelines, microprocessors, templates, schedulability analysis, execution times, software prototyping, hard real time systems, processor utilization