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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 471 occurrences of 218 keywords
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Results
Found 784 publication records. Showing 784 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
27 | Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley |
Device-level early floorplanning algorithms for RF circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin |
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
27 | S. A. Senouci, Aadil Amoura, Helena Krupnova, Gabriele Saucier |
Timing Driven Floorplanning on Programmable Hierarchical Targets. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
|
27 | Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley |
Device-level early floorplanning algorithms for RF circuits. |
ISPD |
1998 |
DBLP DOI BibTeX RDF |
|
27 | Hans Eisenmann, Frank M. Johannes |
Generic Global Placement and Floorplanning. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
verification, timing, design methodology, microprocessor |
27 | John D. Gabbe, P. A. Subrahmanyam |
A Note on Clustering Modules for Floorplanning. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
27 | Somchai Prasitjutrakul, William J. Kubitz |
Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
27 | Hiroyuki Watanabe, Bryan D. Ackland |
Flute - a floorplanning agent for full custom VLSI design. |
DAC |
1986 |
DBLP DOI BibTeX RDF |
|
26 | Juan C. Quiroz, Amit Banerjee, Sushil J. Louis |
IGAP: interactive genetic algorithm peer to peer. |
GECCO |
2008 |
DBLP DOI BibTeX RDF |
collaboration, peer to peer network, floorplanning, interactive genetic algorithm |
26 | Jackey Z. Yan, Chris Chu |
DeFer: deferred decision making enabled fixed-outline floorplanner. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
deferred decision making, floorplanning, fixed outline |
26 | Mark Po-Hung Lin, Shyh-Chang Lin |
Analog placement based on hierarchical module clustering. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
analog placement, floorplanning |
26 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
LEAF: A System Level Leakage-Aware Floorplanner for SoCs. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs |
26 | Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat |
Floorplan repair using dynamic whitespace management. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
VLSI, placement, floorplanning, legalization |
26 | Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran |
Solving hard instances of floorplacement. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
floorplacement, benchmarks, placement, floorplanning, RTL, circuit layout |
26 | Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L. Markov |
Satisfying whitespace requirements in top-down placement. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
placement, physical design, floorplanning |
26 | Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim |
Decoupling capacitor planning and sizing for noise and leakage reduction. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
3D floorplanning, power supply noise, decoupling capacitors, leakage power reduction |
26 | Jin Guo 0001, Antonis Papanikolaou, Pol Marchal, Francky Catthoor |
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture. |
SLIP |
2006 |
DBLP DOI BibTeX RDF |
segmented bus, floorplanning, trade-offs |
26 | Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching |
Block alignment in 3D floorplan using layered TCG. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
3D floorplanning, block alignment |
26 | Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack |
Constraint-driven floorplan repair. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
constraints, floorplanning, legalization |
26 | Dian Zhou, Ruiming Li |
Design and Verification of High-Speed VLSI Physical Design. |
J. Comput. Sci. Technol. |
2005 |
DBLP DOI BibTeX RDF |
floorplanning and placement, order reduction, parameter extraction, VLSI, delay, interconnect, power, physical design, buffer insertion, power grid, clock distribution, wire sizing |
26 | Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov |
Capo: robust and scalable open-source min-cut floorplacer. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
placement, physical design, floorplanning |
26 | Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang |
Joint exploration of architectural and physical design spaces with thermal consideration. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
architectural floorplanning, performance, thermal |
26 | Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh |
Innovate or perish: FPGA physical design. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
FPGA, partitioning, placement, physical design, floorplanning, delay estimation, routing architecture |
26 | Reinaldo A. Bergamaschi |
Early and accurate analysis of SoCs: oxymoron or real? |
SLIP |
2004 |
DBLP DOI BibTeX RDF |
performance, power, design space exploration, floorplanning, design analysis |
26 | Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal |
SEAS: a system for early analysis of SoCs. |
CODES+ISSS |
2003 |
DBLP DOI BibTeX RDF |
performance, power, design space exploration, floorplanning, design analysis |
26 | Parthasarathi Dasgupta, Susmita Sur-Kolay |
Slicible rectangular graphs and their optimal floorplans. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
graph dualization, nonslicible floorplans, slicible floorplans, heuristic search, planar graphs, Floorplanning |
26 | Yangdong Deng, Wojciech Maly |
Interconnect characteristics of 2.5-D system integration scheme. |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
2.5-D system integration, bounded sliceline grid, VLSI, partition, placement, floorplanning, wirelength |
26 | Dinesh P. Mehta, Naveed A. Sherwani |
On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
mixed block and cell designs, floorplanning, rectilinear polygons |
26 | Helena Krupnova, Gabriele Saucier |
FPGA Technology Snapshot: Current Devices and Design Tools. |
IEEE International Workshop on Rapid System Prototyping |
2000 |
DBLP DOI BibTeX RDF |
Configurable Logic Block (CLB), System on a Programmable Chip (SOPC), FPGAs, routing, synthesis, placement, Rapid prototyping, floorplanning, timing optimization, macro block |
26 | Claudia I. Horta, José A. Lima |
Slicing and non-slicing, unified and rotation independent, algebraic representation of floorplans. |
EUROMICRO |
1997 |
DBLP DOI BibTeX RDF |
floorplan area optimization problem, rectangle envelope, nonoverlapping basic rectangles, floorplan topology, formal algebraic specification, SETS notation, VLSI physical design layout, module dimensions, arbitrarily complex composite floorplans, rotation-invariant single-expression formalism, generalized wheels floorplans, slicing representation, nonslicing representation, unified representation, topology-dimensionless description, floorplanning problem algorithms, algebraic specification, line segments, relative positioning |
26 | Kai-Yuan Chao, D. F. Wong 0001 |
Signal integrity optimization on the pad assignment for high-speed VLSI design. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
pad assignment, simultaneous swiching Noise, floorplanning, crosstalk, signal integrity, packaging |
26 | Alexander Dalal, Lavi Lev, Sundari Mitra |
Design of an efficient power distribution network for the UltraSPARC-I microprocessor. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network |
20 | Dipanjan Sengupta, Resve A. Saleh |
Application-driven floorplan-aware voltage island design. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
dynamic programming, energy, floorplan, voltage island |
20 | Jin Guo 0001, Antonis Papanikolaou, H. Zhang, Francky Catthoor |
Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Chen-Wei Liu, Yao-Wen Chang |
Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Andrew B. Kahng, Ion I. Mandoiu, Xu Xu 0001, Alexander Zelikovsky |
Enhanced Design Flow and Optimizations for Multiproject Wafers. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden |
ISPD placement contest updates and ISPD 2007 global routing contest. |
ISPD |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel |
Voltage- and ABB-island optimization in high level synthesis. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, process variation, leakage, voltage islands |
20 | Vyas Krishnan, Srinivas Katkoori |
A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Ali Jahanian 0001, Morteza Saheb Zamani |
Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
Buffer planning, incremental placement, buffer insertion |
20 | Love Singhal, Elaheh Bozorgzadeh |
Physically-aware exploitation of component reuse in a partially reconfigurable architecture. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Krishnan Srinivasan, Karam S. Chatha |
Layout aware design of mesh based NoC architectures. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
network-on-chip, automated design, mesh topology |
20 | Chuan Lin 0002, Hai Zhou 0001, Chris C. N. Chu |
A revisit to floorplan optimization by Lagrangian relaxation. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
floorplan, Lagrangian relaxation |
20 | Chris C. N. Chu, Evangeline F. Y. Young |
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin 0001 |
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel |
Interconnect Driven Low Power High-Level Synthesis. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
20 | François Rémond, Pierre Bricaud |
Set Top Box SoC Design Methodology at STMicroelectronics. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Ravi Varadarajan |
Convergence of placement technology in physical synthesis: is placement really a point tool? |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Stelian Alupoaei, Srinivas Katkoori |
Net-based force-directed macrocell placement for wirelength optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Thomas Brandtner, Robert Weigel |
Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang |
Slicing floorplans with range constraint. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Shantanu Tarafdar, Miriam Leeser |
A data-centric approach to high-level synthesis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Koji Ohashi, Mineo Kaneko, Satoshi Tayu |
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Rajnish K. Prasad, Israel Koren |
The Effect of Placement on Yield for Standard Cell Designs. |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
17 | De-Xuan Zou, Gai-Ge Wang, Arun Kumar Sangaiah, Xiangyong Kong |
A memory-based simulated annealing algorithm and a new auxiliary function for the fixed-outline floorplanning with soft blocks. |
J. Ambient Intell. Humaniz. Comput. |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Yiting Liu, Hai Zhou 0001, Jia Wang 0003, Fan Yang 0001, Xuan Zeng 0001, Li Shang |
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Dayasagar Chowdary S, M. S. Sudhakar 0001 |
Linear programming-based multi-objective floorplanning optimization for system-on-chip. |
J. Supercomput. |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Jian Sun, Huabin Cheng, Jian Wu, Zhanyang Zhu, Yu Chen 0001 |
Floorplanning of VLSI by Mixed-Variable Optimization. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
17 | I-Lun Tseng |
Challenges in Floorplanning and Macro Placement for Modern SoCs. |
ISPD |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Zehua Fang, Jinglin Han, Huaxinyu Wang |
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer. |
Integr. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | B. Srinivasan, R. Venkatesan 0002, Belqasem Aljafari, Ketan Kotecha, V. Indragandhi, Subramaniyaswamy Vairavasundaram |
A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Yuming Zhang, Yimen Zhang |
Thermal-Aware Fixed-Outline 3-D IC Floorplanning: An End-to-End Learning-Based Approach. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Yuming Zhang, Yimen Zhang |
A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Jianwen Luo 0004, Xinzhe Liu, Fupeng Chen, Yajun Ha |
HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Ximeng Li 0005, Keyu Peng, Fuxing Huang, Wenxing Zhu |
PeF: Poisson's Equation-Based Large-Scale Fixed-Outline Floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Naorem Yaipharenba Meitei, Krishna Lal Baishnab, Gaurav Trivedi |
Fast power density aware three-dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithm. |
Int. J. Circuit Theory Appl. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Dayasagar Chowdary S, M. S. Sudhakar 0001 |
Multi-objective Floorplanning optimization engaging dynamic programming for system on chip. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Bo Ding, Jinglei Huang, Qi Xu, Junpeng Wang, Song Chen 0001, Yi Kang |
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. |
ACM Trans. Design Autom. Electr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen 0001, Yi Kang |
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources. |
ACM Trans. Design Autom. Electr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou 0001, Jia Wang 0003, Fan Yang 0001, Xuan Zeng 0001, Li Shang |
GraphPlanner: Floorplanning with Graph Neural Network. |
ACM Trans. Design Autom. Electr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Shan Yu, Yair Censor, Ming Jiang 0001, Guojie Luo |
Per-RMAP: Feasibility-Seeking and Superiorization Methods for Floorplanning with I/O Assignment. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos A. Nicopoulos |
The Case for Asymmetric Systolic Array Floorplanning. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Ignacio Arnaldo, Alfredo Cuesta-Infante, J. Manuel Colmenar, José L. Risco-Martín, José L. Ayala |
Boosting the 3D thermal-aware floorplanning problem through a master-worker parallel MOEA. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Yuanyuan Duan, Xingchen Liu, Zhiping Yu, Hanming Wu, Leilai Shao, Xiaolei Zhu |
RLPlanner: Reinforcement Learning based Floorplanning for Chiplets with Fast Thermal Analysis. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Ke Liu, Jian Gu, Hao Gu, Ziran Zhu |
A Hybrid Reinforcement Learning and Genetic Algorithm for VLSI Floorplanning. |
ICMLC |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Chung-Chia Lee, Yao-Wen Chang |
Floorplanning for Embedded Multi-Die Interconnect Bridge Packages. |
ICCAD |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Fuxing Huang, Duanxiang Liu, Xingquan Li, Bei Yu 0001, Wenxing Zhu |
Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning. |
ICCAD |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Honghong Long, Yu Bai, Yanze Li, Jian Wang, Jinmei Lai |
Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm. |
ASICON |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Wei Li, Fangzhou Wang, José M. F. Moura, R. D. (Shawn) Blanton |
Global Floorplanning via Semidefinite Programming. |
DAC |
2023 |
DBLP DOI BibTeX RDF |
|
17 | J. Shanthi, D. Gracia Nirmala Rani, S. Rajaram 0001 |
An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning. |
Integr. |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Qi Xu, Hao Geng, Song Chen 0001, Bo Yuan 0006, Cheng Zhuo, Yi Kang, Xiaoqing Wen |
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Suchandra Banerjee, Suchismita Roy |
Power aware floorplanning in multiple supply voltage domain. |
Int. J. Circuit Theory Appl. |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Shimin Du, Yang Runping, Yuejun Zhang, Yu Shenglu |
A stable voltage island-driven floorplanning with fixed-outline constraint for low power SoC. |
Microelectron. J. |
2022 |
DBLP DOI BibTeX RDF |
|
17 | J. Shanthi, D. Gracia Nirmala Rani, S. Rajaram 0001 |
A C4.5 decision tree classifier based floorplanning algorithm for System-on-Chip design. |
Microelectron. J. |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Ximeng Li 0005, Keyu Peng, Fuxing Huang, Wenxing Zhu |
PeF: Poisson's Equation Based Large-Scale Fixed-Outline Floorplanning. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen 0001, Yi Kang |
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Danielle Tchuinkou Kwadjo, Erman Nghonda Tchinda, Christophe Bobda |
Coarse-Grained Floorplanning for streaming CNN applications on Multi-Die FPGAs. |
ISPDC |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Yi-Feng Chang, Chuan-Kang Ting |
Multiple Crossover and Mutation Operators Enabled Genetic Algorithm for Non-slicing VLSI Floorplanning. |
CEC |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Summer Yue, Ebrahim M. Songhori, Joe Wenjie Jiang, Toby Boyd, Anna Goldie, Azalia Mirhoseini, Sergio Guadarrama |
Scalability and Generalization of Circuit Training for Chip Floorplanning. |
ISPD |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Haozhe Xu, Siyuan Wei, Nan Qi, Peng Wu, Jian Liu 0021, Nanjian Wu, Liyuan Liu, Shuangming Yu |
Floorplanning and Power/Ground Network Design for A Programmable Vision Chip. |
ICTA |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Yang Hsu, Min-Hsuan Chung, Yao-Wen Chang, Ci-Hong Lin |
Transitive Closure Graph-Based Warpage-Aware Floorplanning for Package Designs. |
ICCAD |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Jianwen Luo 0004, Xinzhe Liu, Fupeng Chen, Yajun Ha |
Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs. |
APCCAS |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou 0001, Jia Wang 0003, Fan Yang 0001, Xuan Zeng 0001, Li Shang |
Floorplanning with graph attention. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Pengli Ji, Kun He 0001, Zhengli Wang, Yan Jin 0005, Jigang Wu |
A Quasi-Newton-based Floorplanner for fixed-outline floorplanning. |
Comput. Oper. Res. |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu |
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC. |
IEEE Trans. Very Large Scale Integr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu |
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Nadir Khan, Jorge Castro-Godínez, Shixiang Xue, Jörg Henkel, Jürgen Becker 0001 |
Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores. |
IEEE Trans. Very Large Scale Integr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske |
Fast Buffer Count Estimation in 3D IC Floorplanning. |
IEEE Trans. Circuits Syst. II Express Briefs |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Suchandra Banerjee, Suchismita Roy |
Thermal-Driven Floorplanning for Fixed Outline Layouts. |
J. Circuits Syst. Comput. |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Jinyu Wang, Yifei Kang, Weiguo Wu, Guoliang Xing, Linlin Tu |
DUPRFloor: Dynamic Modeling and Floorplanning for Partially Reconfigurable FPGAs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2021 |
DBLP DOI BibTeX RDF |
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