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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 838 occurrences of 477 keywords
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Results
Found 1066 publication records. Showing 1066 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke |
Self-calibrating Online Wearout Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 109-122, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Ravi Varadarajan |
Convergence of placement technology in physical synthesis: is placement really a point tool? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 7, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick |
A Genetic Testing Framework for Digital Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI ![In: 14th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2002), 4-6 November 2002, Washington, DC, USA, pp. 521-526, 2002, IEEE Computer Society, 0-7695-1849-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli |
Adaptive least mean square behavioral power modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 404-410, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Franco Fummi, Mariagiovanna Sami, F. Tartarini |
Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 118-123, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal |
Functional test generation for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7), pp. 831-843, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Sachin S. Sapatnekar, Rahul B. Deokar |
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10), pp. 1237-1248, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs |
Circuit-level dictionaries of CMOS bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5), pp. 596-603, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Irith Pomeranz, Sudhakar M. Reddy |
On achieving complete fault coverage for sequential machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3), pp. 378-386, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Niraj K. Jha |
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3), pp. 332-336, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu |
Automated Test Model Generation from Switch Level Custom Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 184-189, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Uwe Gläser, Heinrich Theodor Vierhaus |
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4), pp. 410-423, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Debashis Bhattacharya, John P. Hayes |
A hierarchical test generation methodology for digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(2), pp. 103-123, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
high-level circuit models, test generation, fault modeling, digital circuits, hierarchical testing |
15 | Lijuan Zhu, Gilbert Chen, Boleslaw K. Szymanski, Carl Tropper, Tong Zhang 0002 |
Parallel Logic Simulation of Million-Gate VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 13th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2005), 27-29 September 2005, Atlanta, GA, USA, pp. 521-524, 2005, IEEE Computer Society, 0-7695-2458-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Jonathan R. Carter, Sule Ozev, Daniel J. Sorin |
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 300-305, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang |
Verification of asynchronous interface circuits with bounded wire delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(1-2), pp. 161-182, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
15 | Cho W. Moon, Paul R. Stephan, Robert K. Brayton |
Specification, synthesis, and verification of hazard-free asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(1-2), pp. 85-100, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
15 | Peter M. Maurer, Alexander D. Schapira |
A logic-to-logic comparator for VLSI layout verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 897-907, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
15 | Anmol Mathur, Qi Wang |
Power Reduction Techniques and Flows at RTL and System Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 28-29, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Liang Zhang 0012, Indradeep Ghosh, Michael S. Hsiao |
Efficient Sequential ATPG for Functional RTL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 290-298, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Silvia Chiusano, Fulvio Corno, Paolo Prinetto |
RT-level TPG Exploiting High-Level Synthesis Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 341-353, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Bapiraju Vinnakota, Jason Andrews |
Fast fault translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(1), pp. 122-133, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Samvel K. Shoukourian |
A Unified Design Methodology for Offline and Online Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 15(2), pp. 73-79, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
Fast true delay estimation during high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9), pp. 1088-1105, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
15 | Reiner Hähnle, Werner Kernig |
Verification of Switch-Level Designs with Many-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LPAR ![In: Logic Programming and Automated Reasoning,4th International Conference, LPAR'93, St. Petersburg, Russia, July 13-20, 1993, Proceedings, pp. 158-169, 1993, Springer, 3-540-56944-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
15 | Tyh-Song Hwang, Chung Len Lee 0001, Wen-Zen Shen, Ching Ping Wu |
A Parallel Pattern Mixed-Level Fault Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 716-719, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
14 | Michal Bidlo, Zdenek Vasícek |
Development of combinational circuits using non-uniform cellular automata: initial results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2009, Proceedings, Montreal, Québec, Canada, July 8-12, 2009, pp. 1839-1840, 2009, ACM, 978-1-60558-325-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
evolutionary algorithm, combinational circuit, development, cellular automaton |
14 | Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang 0001, Alexander Taubin, Mark G. Karpovsky |
Asynchronous balanced gates tolerant to interconnect variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3190-3193, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Shuguang Zhao, Licheng Jiao |
Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Genet. Program. Evolvable Mach. ![In: Genet. Program. Evolvable Mach. 7(3), pp. 195-210, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Evolutionary design of circuits, Knowledge discovery, Evolvable hardware, Multi-objective genetic algorithm, Adaptive genetic algorithm |
14 | Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer |
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 36-41, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung |
A hybridized genetic parallel programming based logic circuit synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2006, Proceedings, Seattle, Washington, USA, July 8-12, 2006, pp. 839-846, 2006, ACM, 1-59593-186-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FlowMap, a hybridized genetic parallel programming logic circuit synthesizer, genetic parallel programming, field programmable gate array, technology mapping, LookUp table |
14 | Ashok K. Murugavel, N. Ranganathan |
Petri net modeling of gate and interconnect delays for power estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(5), pp. 921-927, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Peter M. Maurer |
Efficient event-driven simulation by exploiting the output observability of gate clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11), pp. 1471-1486, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Lu Xiao 0003, Howard M. Heys |
Hardware Design and Analysisof Block Cipher Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2002, 5th International Conference Seoul, Korea, November 28-29, 2002, Revised Papers, pp. 164-181, 2002, Springer, 3-540-00716-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Florentin Dartu, Lawrence T. Pileggi |
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 46-51, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò |
Fault simulation of unconventional faults in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5), pp. 677-682, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
14 | Masayuki Miyoshi, Yoshiharu Kazama, Osamu Tada, Yasuo Nagura, Nobutaka Amano |
Speed up techniques of logic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 812-815, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
logic design, logic simulation, design verification |
14 | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 131-136, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi |
Error Tolerance of DNA Self-Healing Assemblies by Puncturing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 400-408, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman |
Extraction error modeling and automated model debugging in high-performance custom designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(7), pp. 763-776, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Xiushan Feng, Alan J. Hu |
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1063-1068, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cutpoints, formal equivalence checking, software, RTL |
14 | Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas |
Functional Test Generation Remote Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 192-195, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo |
Automatic Partitioner for Behavior Level Distributed Logic Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORTE ![In: Formal Techniques for Networked and Distributed Systems - FORTE 2005, 25th IFIP WG 6.1 International Conference, Taipei, Taiwan, October 2-5, 2005, Proceedings, pp. 525-528, 2005, Springer, 3-540-29189-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RTL level partitioner, behavior level partitioner, distributed simulation, parallel simulation |
14 | Oskar Mencer |
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 67-76, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero |
Automatic Test Program Generation from RT-Level Microprocessor Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 120-125, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Wendy Belluomini, Chris J. Myers, H. Peter Hofstee |
Timed circuit verification using TEL structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), pp. 129-146, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero |
Effective Techniques for High-Level ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 225-, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero |
ARPIA: A High-Level Evolutionary Test Signal Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2001: EvoCOP, EvoFlight, EvoIASP, EvoLearn, and EvoSTIM, Como, Italy, April 18-20, 2001, Proceedings, pp. 298-306, 2001, Springer, 3-540-41920-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin |
Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 256-259, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer |
Static timing analysis for self resetting circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 119-126, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
14 | Madhukar K. Reddy, Sudhakar M. Reddy, Prathima Agrawal |
Transistor level test generation for MOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 825-828, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
13 | Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa |
Hardware-Trojan Detection at Gate-Level Netlists Using a Gradient Boosting Decision Tree Model and Its Extension Using Trojan Probability Propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1), pp. 63-74, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Dmytro Mishagli, Eugene Koskin, Elena Blokhina |
Gate-Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.03588, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Ryotaro Negishi, Nozomu Togawa |
Evaluation of Ensemble Learning Models for Hardware-Trojan Identification at Gate-level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2024, Las Vegas, NV, USA, January 6-8, 2024, pp. 1-6, 2024, IEEE, 979-8-3503-2413-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor |
FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11), pp. 3613-3627, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Dong Chen, Chen Dong 0002, Wenwu He, Zhenyi Chen, Ximeng Liu, Hao Zhang |
A fine-grained detection method for gate-level hardware Trojan base on bidirectional Graph Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. King Saud Univ. Comput. Inf. Sci. ![In: J. King Saud Univ. Comput. Inf. Sci. 35(10), pp. 101822, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic |
Impact of gate-level clustering on automated system partitioning of 3D-ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 139, pp. 105896, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic |
Impact of gate-level clustering on automated system partitioning of 3D-ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2307.09308, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu |
TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2301.11804, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Weijie Fang, Yanggeng Fu, Jiaquan Gao, Longkun Guo, Gregory Z. Gutin, Xiaoyan Zhang 0001 |
Acceleration for Timing-Aware Gate-Level Logic Simulation with One-Pass GPU Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.13398, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Rui Cheng, Lin-Zi Yin, Zhao-Hui Jiang, Xue-Mei Xu |
Gate-Level Circuit Partitioning Algorithm Based on Clustering and an Improved Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Entropy ![In: Entropy 25(4), pp. 597, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Georg Land, Adrian Marotzke, Jan Richter-Brockmann, Tim Güneysu |
Gate-Level Masking of Streamlined NTRU Prime Decapsulation in Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2023, pp. 105, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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13 | Haichuan Hu, Zichen Xu 0001, Yuhao Wang, Fangming Liu |
Fast and Scalable Gate-Level Simulation in Massively Parallel Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023, pp. 1-9, 2023, IEEE, 979-8-3503-2225-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Nils Quetschlich, Lukas Burgholzer, Robert Wille |
Reducing the Compilation Time of Quantum Circuits Using Pre-Compilation on the Gate Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QCE ![In: IEEE International Conference on Quantum Computing and Engineering, QCE 2023, Bellevue, WA, USA, September 17-22, 2023, pp. 757-767, 2023, IEEE, 979-8-3503-4323-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Peiheng Zhan, Haihua Shen, Shan Li, Huawei Li |
BGNN-HT: Bidirectional Graph Neural Network for Hardware Trojan Cells Detection at Gate Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu |
TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Amartuvshin Bayasgalan, Makoto Ikeda |
A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: International Conference on IC Design and Technology, ICICDT 2023, Tokyo, Japan, September 25-28, 2023, pp. 20-24, 2023, IEEE, 979-8-3503-1931-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Sofiane Takarabt, Javad Bahrami, Mohammad Ebrahimabadi, Sylvain Guilley, Naghmeh Karimi |
Security Order of Gate-Level Masking Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2023, San Jose, CA, USA, May 1-4, 2023, pp. 57-67, 2023, IEEE, 979-8-3503-0062-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang |
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez 0002, Antonio J. Acosta 0001 |
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 14(2), pp. 99-102, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Hassan Salmani |
Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(4), pp. 515-525, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Naveen Kumar Macha, Bhavana Tejaswini Repalle, Md Arif Iqbal, Mostafizur Rahman |
Crosstalk-Computing-Based Gate-Level Reconfigurable Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(8), pp. 1073-1083, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Zhao Huang, Changjian Xie, Zeyu Li, Maofan Du, Quan Wang 0006 |
A Hardware Trojan Detection and Diagnosis Method for Gate-Level Netlists Based on Different Machine Learning Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(7), pp. 2250135:1-2250135:25, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Naeem Maroof, Ali Y. Al-Zahrani |
A Double Bit Approximate Adder Providing a New Design Perspective for Gate-Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(4), pp. 2250065:1-2250065:21, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Lilas Alrahis, Abhrajit Sengupta, Johann Knechtel, Satwik Patnaik, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu |
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8), pp. 2435-2448, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Siang-Yun Lee, Heinz Riener, Giovanni De Micheli |
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.13487, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Yanqing Zhang 0002, Haoxing Ren, Akshay Sridharan, Brucek Khailany |
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2203.06117, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Pantea Kiaei, Yuan Yao, Zhenyuan Liu, Nicole Fern, Cees-Bart Breunesse, Jasper Van Woudenberg, Kate Gillis, Alex Dich, Peter Grossmann, Patrick Schaumont |
Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2204.11972, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor |
FSMx-Ultra: Finite State Machine Extraction from Gate-Level Netlist for Security Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 1582, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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13 | Anuradha Chathuranga Ranasinghe, Sabih H. Gerez |
Gate-Level RTL Description of the Glitch Optimized Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2022 |
DOI RDF |
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13 | Chi-Wei Chen, Pei-Yu Lo, Wei-Ting Hsu, Chih-Wei Chen, Chin-Wei Tien, Sy-Yen Kuo |
A Hardware Trojan Insertion Framework against Gate-Level Netlist Structural Feature-based and SCOAP-based Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022, Fukuoka, Japan, August 7-10, 2022, pp. 1-5, 2022, IEEE, 978-1-6654-0279-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Xi Li, Min Pan, Tong Liu, Peter A. Beerel |
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022, pp. 62-67, 2022, IEEE, 978-1-6654-6605-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa |
Hardware-Trojan Detection at Gate-level Netlists using Gradient Boosting Decision Tree Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-Berlin ![In: 12th IEEE International Conference on Consumer Electronics, ICCE-Berlin 2022, Berlin, Germany, September 2-6, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5676-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Daniela Kaufmann, Paul Beame, Armin Biere, Jakob Nordström |
Adding Dual Variables to Algebraic Reasoning for Gate-Level Multiplier Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, pp. 1431-1436, 2022, IEEE, 978-3-9819263-6-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Brunno A. Abreu, Guilherme Paim, Jorge Castro-Godínez, Mateus Grellert, Sergio Bampi |
On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 13th IEEE Latin America Symposium on Circuits and System, LASCAS 2022, Puerto Varas, Chile, March 1-4, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-2008-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Rakesh M. B., Sai Pranav K. R, Pabitra Das, Amit Acharyya |
GLAAPE: Graph Learning Assisted Average Power Estimation for Gate-level Combinational Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS 2022 ![In: 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022, Glasgow, United Kingdom, October 24-26, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-8823-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu |
2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022, pp. 93:1-93:4, 2022, ACM, 978-1-4503-9217-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Vidya A. Chhabria, Ben Keller, Yanqing Zhang 0002, Sandeep Vollala, Sreedhar Pratty, Haoxing Ren, Brucek Khailany |
XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MLCAD ![In: 2022 ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2022, Virtual Event, China, September 12-13, 2022, pp. 63-69, 2022, ACM / IEEE, 978-1-4503-9486-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Kazuki Yamashita, Tomohiro Kato, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Nozomu Togawa |
Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 28th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2022, Torino, Italy, September 12-14, 2022, pp. 1-7, 2022, IEEE, 978-1-6654-7355-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud, George I. Stamoulis |
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022, pp. 77-83, 2022, ACM, 978-1-4503-9322-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Hassan Salmani |
The Improved COTD Technique for Hardware Trojan Detection in Gate-level Netlist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022, pp. 449-454, 2022, ACM, 978-1-4503-9322-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Kattekola Naresh, Y. Padma Sai, Shubhankar Majumdar |
Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, VLSID 2022, Bangalore, India, February 26 - March 2, 2022, pp. 269-274, 2022, IEEE, 978-1-6654-8505-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Yanqing Zhang 0002, Haoxing Ren, Akshay Sridharan, Brucek Khailany |
GATSPI: GPU accelerated gate-level simulation for power improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 1231-1236, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Michael Zuzak |
Designing Effective Logic Obfuscation: Exploring Beyond Gate-Level Boundaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2022 |
RDF |
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13 | Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa |
Generating Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Process. ![In: J. Inf. Process. 29, pp. 236-246, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin |
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2104.01900, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin |
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2104.01812, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | P. Balasubramanian 0001, Raunaq Nayar, Douglas L. Maskell |
Gate-Level Static Approximate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2112.09320, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer 0001 |
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2103.05106, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Gregor Leander, Thorben Moos, Amir Moradi 0001, Shahram Rasoolzadeh |
The SPEEDY Family of Block Ciphers Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(4), pp. 510-545, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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