Search results for "gate-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke	Self-calibrating Online Wearout Detection.	MICRO	2007	DBLP DOI BibTeX RDF
16	Ravi Varadarajan	Convergence of placement technology in physical synthesis: is placement really a point tool?	ISPD	2003	DBLP DOI BibTeX RDF
16	Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick	A Genetic Testing Framework for Digital Integrated Circuits.	ICTAI	2002	DBLP DOI BibTeX RDF
16	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli	Adaptive least mean square behavioral power modeling.	ED&TC	1997	DBLP DOI BibTeX RDF
16	Franco Fummi, Mariagiovanna Sami, F. Tartarini	Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
16	Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal	Functional test generation for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
16	Sachin S. Sapatnekar, Rahul B. Deokar	Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
16	Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs	Circuit-level dictionaries of CMOS bridging faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
16	Irith Pomeranz, Sudhakar M. Reddy	On achieving complete fault coverage for sequential machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
16	Niraj K. Jha	Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
16	Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu	Automated Test Model Generation from Switch Level Custom Circuits.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
16	Uwe Gläser, Heinrich Theodor Vierhaus	Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
16	Debashis Bhattacharya, John P. Hayes	A hierarchical test generation methodology for digital circuits.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	high-level circuit models, test generation, fault modeling, digital circuits, hierarchical testing
15	Lijuan Zhu, Gilbert Chen, Boleslaw K. Szymanski, Carl Tropper, Tong Zhang 0002	Parallel Logic Simulation of Million-Gate VLSI Circuits.	MASCOTS	2005	DBLP DOI BibTeX RDF
15	Jonathan R. Carter, Sule Ozev, Daniel J. Sorin	Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown.	DATE	2005	DBLP DOI BibTeX RDF
15	Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang	Verification of asynchronous interface circuits with bounded wire delays.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
15	Cho W. Moon, Paul R. Stephan, Robert K. Brayton	Specification, synthesis, and verification of hazard-free asynchronous circuits.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
15	Peter M. Maurer, Alexander D. Schapira	A logic-to-logic comparator for VLSI layout verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
15	Anmol Mathur, Qi Wang	Power Reduction Techniques and Flows at RTL and System Level.	VLSI Design	2009	DBLP DOI BibTeX RDF
15	Liang Zhang 0012, Indradeep Ghosh, Michael S. Hsiao	Efficient Sequential ATPG for Functional RTL Circuits.	ITC	2003	DBLP DOI BibTeX RDF
15	Silvia Chiusano, Fulvio Corno, Paolo Prinetto	RT-level TPG Exploiting High-Level Synthesis Information.	VTS	1999	DBLP DOI BibTeX RDF
15	Bapiraju Vinnakota, Jason Andrews	Fast fault translation.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
15	Samvel K. Shoukourian	A Unified Design Methodology for Offline and Online Testing.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
15	Subhrajit Bhattacharya, Sujit Dey, Franc Brglez	Fast true delay estimation during high level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
15	Reiner Hähnle, Werner Kernig	Verification of Switch-Level Designs with Many-Valued Logic.	LPAR	1993	DBLP DOI BibTeX RDF
15	Tyh-Song Hwang, Chung Len Lee 0001, Wen-Zen Shen, Ching Ping Wu	A Parallel Pattern Mixed-Level Fault Simulator.	DAC	1990	DBLP DOI BibTeX RDF
14	Michal Bidlo, Zdenek Vasícek	Development of combinational circuits using non-uniform cellular automata: initial results.	GECCO	2009	DBLP DOI BibTeX RDF	evolutionary algorithm, combinational circuit, development, cellular automaton
14	Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang 0001, Alexander Taubin, Mark G. Karpovsky	Asynchronous balanced gates tolerant to interconnect variability.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Shuguang Zhao, Licheng Jiao	Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm.	Genet. Program. Evolvable Mach.	2006	DBLP DOI BibTeX RDF	Evolutionary design of circuits, Knowledge discovery, Evolvable hardware, Multi-objective genetic algorithm, Adaptive genetic algorithm
14	Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer	Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
14	Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung	A hybridized genetic parallel programming based logic circuit synthesizer.	GECCO	2006	DBLP DOI BibTeX RDF	FlowMap, a hybridized genetic parallel programming logic circuit synthesizer, genetic parallel programming, field programmable gate array, technology mapping, LookUp table
14	Ashok K. Murugavel, N. Ranganathan	Petri net modeling of gate and interconnect delays for power estimation.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
14	Peter M. Maurer	Efficient event-driven simulation by exploiting the output observability of gate clusters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
14	Lu Xiao 0003, Howard M. Heys	Hardware Design and Analysisof Block Cipher Components.	ICISC	2002	DBLP DOI BibTeX RDF
14	Florentin Dartu, Lawrence T. Pileggi	Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling.	DAC	1997	DBLP DOI BibTeX RDF
14	Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò	Fault simulation of unconventional faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
14	Masayuki Miyoshi, Yoshiharu Kazama, Osamu Tada, Yasuo Nagura, Nobutaka Amano	Speed up techniques of logic simulation.	DAC	1985	DBLP DOI BibTeX RDF	logic design, logic simulation, design verification
14	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.	ETS	2007	DBLP DOI BibTeX RDF
14	Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi	Error Tolerance of DNA Self-Healing Assemblies by Puncturing.	DFT	2007	DBLP DOI BibTeX RDF
14	Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman	Extraction error modeling and automated model debugging in high-performance custom designs.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
14	Xiushan Feng, Alan J. Hu	Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification.	DAC	2006	DBLP DOI BibTeX RDF	cutpoints, formal equivalence checking, software, RTL
14	Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas	Functional Test Generation Remote Tool.	DSD	2005	DBLP DOI BibTeX RDF
14	Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo	Automatic Partitioner for Behavior Level Distributed Logic Simulation.	FORTE	2005	DBLP DOI BibTeX RDF	RTL level partitioner, behavior level partitioner, distributed simulation, parallel simulation
14	Oskar Mencer	PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs.	FCCM	2002	DBLP DOI BibTeX RDF
14	Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero	Automatic Test Program Generation from RT-Level Microprocessor Descriptions.	ISQED	2002	DBLP DOI BibTeX RDF
14	Wendy Belluomini, Chris J. Myers, H. Peter Hofstee	Timed circuit verification using TEL structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
14	Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero	Effective Techniques for High-Level ATPG.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
14	Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero	ARPIA: A High-Level Evolutionary Test Signal Generator.	EvoWorkshops	2001	DBLP DOI BibTeX RDF
14	Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin	Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations.	VLSI Design	1999	DBLP DOI BibTeX RDF
14	Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer	Static timing analysis for self resetting circuits.	ICCAD	1996	DBLP DOI BibTeX RDF
14	Madhukar K. Reddy, Sudhakar M. Reddy, Prathima Agrawal	Transistor level test generation for MOS circuits.	DAC	1985	DBLP DOI BibTeX RDF
13	Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa	Hardware-Trojan Detection at Gate-Level Netlists Using a Gradient Boosting Decision Tree Model and Its Extension Using Trojan Probability Propagation.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2024	DBLP DOI BibTeX RDF
13	Dmytro Mishagli, Eugene Koskin, Elena Blokhina	Gate-Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms.	CoRR	2024	DBLP DOI BibTeX RDF
13	Ryotaro Negishi, Nozomu Togawa	Evaluation of Ensemble Learning Models for Hardware-Trojan Identification at Gate-level Netlists.	ICCE	2024	DBLP DOI BibTeX RDF
13	Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor	FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
13	Dong Chen, Chen Dong 0002, Wenwu He, Zhenyi Chen, Ximeng Liu, Hao Zhang	A fine-grained detection method for gate-level hardware Trojan base on bidirectional Graph Neural Networks.	J. King Saud Univ. Comput. Inf. Sci.	2023	DBLP DOI BibTeX RDF
13	Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic	Impact of gate-level clustering on automated system partitioning of 3D-ICs.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic	Impact of gate-level clustering on automated system partitioning of 3D-ICs.	CoRR	2023	DBLP DOI BibTeX RDF
13	Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu	TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection.	CoRR	2023	DBLP DOI BibTeX RDF
13	Weijie Fang, Yanggeng Fu, Jiaquan Gao, Longkun Guo, Gregory Z. Gutin, Xiaoyan Zhang 0001	Acceleration for Timing-Aware Gate-Level Logic Simulation with One-Pass GPU Parallelism.	CoRR	2023	DBLP DOI BibTeX RDF
13	Rui Cheng, Lin-Zi Yin, Zhao-Hui Jiang, Xue-Mei Xu	Gate-Level Circuit Partitioning Algorithm Based on Clustering and an Improved Genetic Algorithm.	Entropy	2023	DBLP DOI BibTeX RDF
13	Georg Land, Adrian Marotzke, Jan Richter-Brockmann, Tim Güneysu	Gate-Level Masking of Streamlined NTRU Prime Decapsulation in Hardware.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
13	Haichuan Hu, Zichen Xu 0001, Yuhao Wang, Fangming Liu	Fast and Scalable Gate-Level Simulation in Massively Parallel Systems.	ICCAD	2023	DBLP DOI BibTeX RDF
13	Nils Quetschlich, Lukas Burgholzer, Robert Wille	Reducing the Compilation Time of Quantum Circuits Using Pre-Compilation on the Gate Level.	QCE	2023	DBLP DOI BibTeX RDF
13	Peiheng Zhan, Haihua Shen, Shan Li, Huawei Li	BGNN-HT: Bidirectional Graph Neural Network for Hardware Trojan Cells Detection at Gate Level.	ISCAS	2023	DBLP DOI BibTeX RDF
13	Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu	TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection.	ISCAS	2023	DBLP DOI BibTeX RDF
13	Amartuvshin Bayasgalan, Makoto Ikeda	A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit.	ICICDT	2023	DBLP DOI BibTeX RDF
13	Sofiane Takarabt, Javad Bahrami, Mohammad Ebrahimabadi, Sylvain Guilley, Naghmeh Karimi	Security Order of Gate-Level Masking Schemes.	HOST	2023	DBLP DOI BibTeX RDF
13	Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang	General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.	DAC	2023	DBLP DOI BibTeX RDF
13	Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez 0002, Antonio J. Acosta 0001	Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs.	IEEE Embed. Syst. Lett.	2022	DBLP DOI BibTeX RDF
13	Hassan Salmani	Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
13	Naveen Kumar Macha, Bhavana Tejaswini Repalle, Md Arif Iqbal, Mostafizur Rahman	Crosstalk-Computing-Based Gate-Level Reconfigurable Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
13	Zhao Huang, Changjian Xie, Zeyu Li, Maofan Du, Quan Wang 0006	A Hardware Trojan Detection and Diagnosis Method for Gate-Level Netlists Based on Different Machine Learning Algorithms.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
13	Naeem Maroof, Ali Y. Al-Zahrani	A Double Bit Approximate Adder Providing a New Design Perspective for Gate-Level Design.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
13	Lilas Alrahis, Abhrajit Sengupta, Johann Knechtel, Satwik Patnaik, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu	GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
13	Siang-Yun Lee, Heinz Riener, Giovanni De Micheli	An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications.	CoRR	2022	DBLP DOI BibTeX RDF
13	Yanqing Zhang 0002, Haoxing Ren, Akshay Sridharan, Brucek Khailany	GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement.	CoRR	2022	DBLP DOI BibTeX RDF
13	Pantea Kiaei, Yuan Yao, Zhenyuan Liu, Nicole Fern, Cees-Bart Breunesse, Jasper Van Woudenberg, Kate Gillis, Alex Dich, Peter Grossmann, Patrick Schaumont	Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis.	CoRR	2022	DBLP DOI BibTeX RDF
13	Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor	FSMx-Ultra: Finite State Machine Extraction from Gate-Level Netlist for Security Assessment.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
13	Anuradha Chathuranga Ranasinghe, Sabih H. Gerez	Gate-Level RTL Description of the Glitch Optimized Multipliers.		2022	DOI RDF
13	Chi-Wei Chen, Pei-Yu Lo, Wei-Ting Hsu, Chih-Wei Chen, Chin-Wei Tien, Sy-Yen Kuo	A Hardware Trojan Insertion Framework against Gate-Level Netlist Structural Feature-based and SCOAP-based Detection.	MWSCAS	2022	DBLP DOI BibTeX RDF
13	Xi Li, Min Pan, Tong Liu, Peter A. Beerel	Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic.	ISVLSI	2022	DBLP DOI BibTeX RDF
13	Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa	Hardware-Trojan Detection at Gate-level Netlists using Gradient Boosting Decision Tree Models.	ICCE-Berlin	2022	DBLP DOI BibTeX RDF
13	Daniela Kaufmann, Paul Beame, Armin Biere, Jakob Nordström	Adding Dual Variables to Algebraic Reasoning for Gate-Level Multiplier Verification.	DATE	2022	DBLP DOI BibTeX RDF
13	Brunno A. Abreu, Guilherme Paim, Jorge Castro-Godínez, Mateus Grellert, Sergio Bampi	On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators.	LASCAS	2022	DBLP DOI BibTeX RDF
13	Rakesh M. B., Sai Pranav K. R, Pabitra Das, Amit Acharyya	GLAAPE: Graph Learning Assisted Average Power Estimation for Gate-level Combinational Designs.	ICECS 2022	2022	DBLP DOI BibTeX RDF
13	Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu	2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level Circuit.	ICCAD	2022	DBLP DOI BibTeX RDF
13	Vidya A. Chhabria, Ben Keller, Yanqing Zhang 0002, Sandeep Vollala, Sreedhar Pratty, Haoxing Ren, Brucek Khailany	XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning.	MLCAD	2022	DBLP DOI BibTeX RDF
13	Kazuki Yamashita, Tomohiro Kato, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Nozomu Togawa	Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists.	IOLTS	2022	DBLP DOI BibTeX RDF
13	Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud, George I. Stamoulis	Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
13	Hassan Salmani	The Improved COTD Technique for Hardware Trojan Detection in Gate-level Netlist.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
13	Kattekola Naresh, Y. Padma Sai, Shubhankar Majumdar	Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor.	VLSID	2022	DBLP DOI BibTeX RDF
13	Yanqing Zhang 0002, Haoxing Ren, Akshay Sridharan, Brucek Khailany	GATSPI: GPU accelerated gate-level simulation for power improvement.	DAC	2022	DBLP DOI BibTeX RDF
13	Michael Zuzak	Designing Effective Logic Obfuscation: Exploring Beyond Gate-Level Boundaries.		2022	RDF
13	Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa	Generating Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists.	J. Inf. Process.	2021	DBLP DOI BibTeX RDF
13	Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin	The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications.	CoRR	2021	DBLP BibTeX RDF
13	Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin	Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors.	CoRR	2021	DBLP BibTeX RDF
13	P. Balasubramanian 0001, Raunaq Nayar, Douglas L. Maskell	Gate-Level Static Approximate Adders.	CoRR	2021	DBLP BibTeX RDF
13	Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer 0001	Representing Gate-Level SET Faults by Multiple SEU Faults at RTL.	CoRR	2021	DBLP BibTeX RDF
13	Gregor Leander, Thorben Moos, Amir Moradi 0001, Shahram Rasoolzadeh	The SPEEDY Family of Block Ciphers Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2021	DBLP DOI BibTeX RDF