Search results for "hSpice"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Shu-Hui Tu, J. Neil Ross	Low sensitivity single-ended-input OTA and grounded capacitor elliptic filter structure with the minimum components.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
10	Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada	Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
10	Chua-Chin Wang, Ching-Li Lee, Li-Ping Lin, Yih-Long Tseng	Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
10	Hashem Zare-Hoseini, Omid Shoaei, Izzet Kale	A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
10	Wing-Hung Ki, Feng Su, Chi-Ying Tsui	Charge redistribution loss consideration in optimal charge pump design.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
10	Chengjun Zhang, Chunyan Wang 0004, M. Omair Ahmad	A VLSI architecture for a high-speed computation of the 1D discrete wavelet transform.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
10	G. M. Howard, Pedram Mokrian, Majid Ahmadi, William C. Miller	Power and delay analysis of 4: 2 compressor cells.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
10	Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo, Chia-Wei Su	A phase-detect synchronous mirror delay for clock skew-compensation circuits.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
10	Minoru Watanabe, Fuminori Kobayashi	A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
10	B. Afkal, Ali Afzali-Kusha, Mahmoud El Nokali	Efficient power model for crossbar interconnects.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
10	Yarallah Koolivand, Omid Shoaei, Ali Zahabi, Hossein Shamsi, Parviz Jabedar Maralani	A new technique for design CMOS LNA for multi-standard receivers.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
10	Jesús Ruiz-Amaya, José M. de la Rosa 0001, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez	Behavioral modeling simulation and high-level synthesis of pipeline A/D converters.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
10	Morteza Gholipour, Hamid Shojaee, Ali Afzali-Kusha, Ahmad Khademzadeh, Mehrdad Nourani	An efficient model for performance analysis of asynchronous pipeline design methods.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
10	Brian P. Ginsburg, Anantha P. Chandrakasan	An energy-efficient charge recycling approach for a SAR converter with capacitive DAC.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
10	José Manuel Cazeaux, Daniele Rossi 0001, Martin Omaña 0001, Cecilia Metra, Abhijit Chatterjee	On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.	IOLTS	2005	DBLP DOI BibTeX RDF
10	Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy 0001	Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology.	IOLTS	2005	DBLP DOI BibTeX RDF
10	Zhihao Xu, Dongming Jin, Zhijian Li	Design of an Analog Adaptive Fuzzy Logic Controller.	FSKD (1)	2005	DBLP DOI BibTeX RDF
10	Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu	An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
10	Jaehong Ko, Wookwan Lee, Soo-Won Kim	2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	jitter, PLL, output buffer, charge-pump
10	Srivathsan Krishnamohan, Nihar R. Mahapatra	An analysis of the robustness of CMOS delay elements.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	delay element, process variation, yield, Monte Carlo simulation
10	Tian Xia, Peilin Song, Hao Zheng 0001	Characterizing the VCO jitter due to the digital simultaneous switching noise.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	buffer, jitter, VCO, simultaneous switching noise
10	Shaolei Quan, Meng-Yao Liu, Chin-Long Wey	Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress.	DFT	2005	DBLP DOI BibTeX RDF
10	Ali Zahabi, Omid Shoaei, Yarallah Koolivand	Design of a Band-Pass Pseudo-2-Path Switched Capacitor Ladder Filter.	ISQED	2005	DBLP DOI BibTeX RDF
10	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Dual-Edge Triggered Static Pulsed Flip-Flops.	VLSI Design	2005	DBLP DOI BibTeX RDF
10	Suvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran	Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs.	VLSI Design	2005	DBLP DOI BibTeX RDF
10	Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001, Wenping Wang	Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
10	M. M. Tabriz, Nasser Masoumi	A New Topology for Power Control of High Efficiency Class-E Switched Mode Power Amplifier.	IWSOC	2005	DBLP DOI BibTeX RDF
10	Yanjie Wang, Yanbin Wang, Garry Tarr, Kris Iniewski	A Temperature, Supply Voltage Compensated Floating-Gate MOS Dosimeter Using V_TH Extractor.	IWSOC	2005	DBLP DOI BibTeX RDF
10	Chun-Yueh Huang, Tsung-Tien Hou, Chi-Chieh Chuang, Hung-Yu Wang	Design of 12-bit 100-MHz Current-Steering DAC for SoC Applications.	IWSOC	2005	DBLP DOI BibTeX RDF
10	Amir Khatibzadeh, Kaamran Raahemifar	A Novel Design of a 6-GHz 8 X 8-b Pipelined Multiplier.	IWSOC	2005	DBLP DOI BibTeX RDF
10	Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu	Fitted Elmore delay: a simple and accurate interconnect delay model.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
10	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001	A circuit-compatible model of ballistic carbon nanotube field-effect transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Model for Transient Fault Susceptibility of Combinational Circuits.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	transient fault modeling, transient fault susceptibility, alpha-particle, soft error, transient fault
10	Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson	Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.	PATMOS	2004	DBLP DOI BibTeX RDF
10	Geoff V. Merrett, Bashir M. Al-Hashimi	Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.	PATMOS	2004	DBLP DOI BibTeX RDF
10	Joohee Kim, Conrad H. Ziesler	Fixed-Load Energy Recovery Memory for Low Power.	ISVLSI	2004	DBLP DOI BibTeX RDF
10	Shu-Shin Chin, Sangjin Hong, Suhwan Kim	Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units.	ISVLSI	2004	DBLP DOI BibTeX RDF
10	José Luis Rosselló, Jaume Segura 0001	A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk.	DATE	2004	DBLP DOI BibTeX RDF
10	Turgay Temel, Avni Morgül, Nizamettin Aydin	A Novel Signed Higher-Radix Full-Adder Algorithm and Implementation with Current-Mode Multi-Valued Logic Circuits.	DSD	2004	DBLP DOI BibTeX RDF
10	Nisrine Saadallah, Xiaohua Kong, Radu Negulescu	High-Speed Reduced Stack Dual Lock Circuits.	ASYNC	2004	DBLP DOI BibTeX RDF
10	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Analysis of MOS cross-coupled LC-tank oscillators using short-channel device equations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
10	Zhong Wang, Jianwen Zhu	Piecewise quadratic waveform matching with successive chord iteration.	ASP-DAC	2004	DBLP DOI BibTeX RDF
10	Lei Wang, Sandeep K. Gupta 0001, Melvin A. Breuer	Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
10	Jaime Martínez-Castillo, Alejandro Díaz-Sánchez, Alfonso Torres-Jácome, Roberto S. Murphy-Arteaga, Jesús L. Finol	Bi-CMOS Opto-Electronic Reception System for Application in High-Frequencies.	CONIELECOMP	2004	DBLP DOI BibTeX RDF	OEIC receiver, transimpedance amplifier, low-noise amplifier, BiCMOS, TIA
10	Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim	Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit.	ISMVL	2004	DBLP DOI BibTeX RDF
10	Arijit Raychowdhury, Kaushik Roy 0001	A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs.	ISMVL	2004	DBLP DOI BibTeX RDF
10	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
10	Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge	Microarchitectural power modeling techniques for deep sub-micron microprocessors.	ISLPED	2004	DBLP DOI BibTeX RDF	power modeling, deep sub-micron
10	Yi Zou, Yici Cai, Qiang Zhou 0001, Xianlong Hong, Sheldon X.-D. Tan	A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.	ICCD	2004	DBLP DOI BibTeX RDF
10	Yao Guo 0001, Saurabh Chheda, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz	Energy Characterization of Hardware-Based Data Prefetching.	ICCD	2004	DBLP DOI BibTeX RDF
10	Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma	XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs.	ICCD	2004	DBLP DOI BibTeX RDF
10	Masayuki Tsukisaka, Masashi Imai, Takashi Nanya	Asynchronous Scan-Latch controller for Low Area Overhead DFT.	ICCD	2004	DBLP DOI BibTeX RDF
10	Nima Maghari, Mohammad Yavari, Omid Shoaei	An analytical model for the slewing behavior of CMOS two-stage operational transconductance amplifiers.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
10	Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao	A wide-range and fast-locking clock synthesizer IP based on delay-locked loop.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
10	Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo	A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
10	Zhan Xu, Ezz I. El-Masry	Synthesis of log-domain filter with well-defined operating point.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
10	Pedro M. Figueiredo, João C. Vital	Low kickback noise techniques for CMOS latched comparators.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
10	Yarallah Koolivand, Ali Zahabi, Nasser Masoumi	Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching technique.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	polysilicide gate resistance, short circuit power, performance degradation, propagation delay
10	Edward K. S. Au, Wing-Hung Ki, Wai Ho Mow, Silas T. Hung, Catherine Y. Wong	A binary--search switched--current sensing scheme for 4-state MRAM.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	magneto-resistive random access memory, switched-current
10	Mohamed Abbas, Makoto Ikeda, Kunihiro Asada	Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime.	DFT	2004	DBLP DOI BibTeX RDF
10	Shabbir H. Batterywala, Narendra V. Shenoy	Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Suvodeep Gupta, Srinivas Katkoori	Intra-Bus Crosstalk Estimation Using Word-Level Statistics.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Chong Zhao, Xiaoliang Bai, Sujit Dey	A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits.	DAC	2004	DBLP DOI BibTeX RDF	compound noise effect, nano-meter technology, softness distribution, robustness
10	Yen-Jen Chang, Shanq-Jang Ruan, Feipei Lai	Design and analysis of low-power cache using two-level filter scheme.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	A true single-phase energy-recovery multiplier.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Li Ding 0002, Pinaki Mazumder	Simultaneous switching noise analysis using application specific device modeling.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Bibhudatta Sahoo 0002, Keshab K. Parhi	A Low Power Correlator for CDMA Wireless Systems.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	low-power, correlator, CDMA, incrementer
10	Sampo Tuuna, Jouni Isoaho	Estimation of Crosstalk Noise for On-Chip Buses.	PATMOS	2003	DBLP DOI BibTeX RDF
10	José Luis Rosselló, Jaume Segura 0001	A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates.	PATMOS	2003	DBLP DOI BibTeX RDF
10	Peter M. Kelly, C. J. Thompson, T. Martin McGinnity, Liam P. Maguire	A Binary Multiplier Using RTD Based Threshold Logic Gates.	IWANN (2)	2003	DBLP DOI BibTeX RDF
10	Srividya Srinivasaraghavan, Wayne P. Burleson	Interconnect Effort - A Unification of Repeater Insertion and Logical Effort.	ISVLSI	2003	DBLP DOI BibTeX RDF
10	Chandramouli Gopalakrishnan, Srinivas Katkoori	An Architectural Leakage Power Simulator for VHDL Structural Datapaths.	ISVLSI	2003	DBLP DOI BibTeX RDF
10	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	High Speed and Highly Testable Parallel Two-Rail Code Checker.	DATE	2003	DBLP DOI BibTeX RDF
10	Li-Da Huang, Hung-Ming Chen, D. F. Wong 0001	Global Wire Bus Configuration with Minimum Delay Uncertainty.	DATE	2003	DBLP DOI BibTeX RDF
10	Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li 0001	Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	stack effect, leakage current simulation, propagation of signal probability, macromodeling
10	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001	Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.	ICCAD	2003	DBLP DOI BibTeX RDF	SPICE
10	Xuning Chen, Li-Shiuan Peh	Leakage power modeling and optimization in interconnection networks.	ISLPED	2003	DBLP DOI BibTeX RDF	interconnection networks, leakage power, power optimization
10	Z. Q. Li, Xiaowei Sun, W. Fan, G. J. Qi	Bias-adaptive cross-coupled CMOS MAGFET pair for bipolar magnetic field detection.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
10	Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyounghoon Yang	Performance modeling of resonant tunneling based RAMs.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
10	Taeik Kim, Xiaoyong Li 0001, David J. Allstot	Accurate compact model extraction for on-chip coplanar waveguides.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
10	Surachet Khucharoensin, Varakorn Kasemsuwan	High performance CMOS current-mode precision full-wave rectifier (PFWR).	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu	A mixed-mode delay-locked loop for wide-range operation and multiphase outputs.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
10	Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu	Low-power and low-voltage fully parallel content-addressable memory.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Qinwei Xu, Pinaki Mazumder	Efficient interconnect modeling by Finite Difference Quadrature methods.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
10	Shuenn-Yuh Lee, Shyh-Chyang Lee, Jia-Jin Jason Chen	VLSI implementation of wireless bi-directional communication circuits for micro-stimulator.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Tetsuya Fujiwara, Yoshihiko Horio, Kazuyuki Aihara	An integrated multi-scroll circuit with floating-gate MOSFETs.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
10	Rola A. Baki, Mourad N. El-Gamal	A new CMOS charge pump for low-voltage (1V) high-speed PLL applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Pedro M. Figueiredo, João C. Vital	Analysis of the averaging technique in flash ADCs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Amorn Jiraseree-amornkun, Nobuo Fujii, Wanlop Surakampontorn	Realization of electronically tunable ladder filters using multi-output current controlled conveyors.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Jianjun Guo, Waisiu Law, Charles T. Peach, Ward J. Helms, David J. Allstot	A mixed-signal calibration technique for low-voltage CMOS 1.5-bit/stage pipeline data converters.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Surachet Khucharoensin, Varakorn Kasemsuwan	High-speed low input impedance CMOS current comparator.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Boonchai Boonchu, Wanlop Surakampontorn	A CMOS current-mode squarer/rectifier circuit.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Sei Hyung Jang	A new synchronous mirror delay with an auto-skew-generation circuit.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Kuo-Hsing Cheng, Yung-Hsiang Lin	A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi	Noise tolerant low voltage XOR-XNOR for fast arithmetic.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	XOR-XNOR circuits, multipliers, noise tolerant, deep submicron, nanometer technology
10	Aiyappan Natarajan, David Jasinski, Wayne P. Burleson, Russell Tessier	A hybrid adiabatic content addressable memory for ultra low-power applications.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	adiabatic switching, ultra-low power, energy recovery
10	Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota	Test Vector Generation Based on Correlation Model for Ratio-Iddq.	ITC	2003	DBLP DOI BibTeX RDF
10	Rahul Kundu, R. D. (Shawn) Blanton	Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk.	ITC	2003	DBLP DOI BibTeX RDF
10	Shabbir H. Batterywala, Narendra V. Shenoy	A Method to Estimate Slew and Delay in Coupled Digital Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
10	Li Ding 0002, Pinaki Mazumder	The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance.	VLSI Design	2003	DBLP DOI BibTeX RDF