Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Lieven Eeckhout, Dirk Stroobandt, Koenraad De Bosschere	Efficient Microprocessor Design Space Exploration through Statistical Simulatio.	Annual Simulation Symposium	2003	DBLP DOI BibTeX RDF
24	Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva Silva	X4CP32: A Coarse Grain General Purpose Reconfigurable Microprocessor.	IPDPS	2003	DBLP DOI BibTeX RDF
24	Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger	Microprocessor pipeline energy analysis.	ISLPED	2003	DBLP DOI BibTeX RDF	alpha 21264, over-provisioning, power, energy, speculation
24	Tao Li 0006, Lizy Kurian John	Routine based OS-aware microprocessor resource adaptation for run-time operating system power saving.	ISLPED	2003	DBLP DOI BibTeX RDF	adaptive processor, low power, operating system
24	Noriyuki Ito, Hiroaki Komatsu, Yoshiyasu Tanamura, Ryoichi Yamashita, Hiroyuki Sugiyama, Yaroku Sugiyama, Hirofumi Hamamura	A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor.	ICCD	2003	DBLP DOI BibTeX RDF
24	Paul I. Pénzes, Alain J. Martin	An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor.	DATE	2002	DBLP DOI BibTeX RDF
24	Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero	Evolutionary Test Program Induction for Microprocessor Design Verification.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
24	William C. Athas, Lynn Youngs, Andrew Reinhart	Compact models for estimating microprocessor frequency and power.	ISLPED	2002	DBLP DOI BibTeX RDF	VLSI, low-power, microprocessors, ASIC, power estimation, curve-fitting, delay modeling
24	Chee How Lim, W. Robert Daasch, George Cai	A Thermal-Aware Superscalar Microprocessor (invited).	ISQED	2002	DBLP DOI BibTeX RDF
24	Don Douglas Josephson	The Manic Depression of Microprocessor Debug.	ITC	2002	DBLP DOI BibTeX RDF
24	Christopher T. Weaver, Todd M. Austin	A Fault Tolerant Approach to Microprocessor Design.	DSN	2001	DBLP DOI BibTeX RDF
24	Per Bjesse, Tim Leonard, Abdel Mokkedem	Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers.	CAV	2001	DBLP DOI BibTeX RDF
24	Paul Kartschoke, Shervin Hojat	Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor.	ISQED	2001	DBLP DOI BibTeX RDF
24	Magdy S. Abadir, Juhong Zhu, Li-C. Wang	Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor.	VTS	2001	DBLP DOI BibTeX RDF
24	T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Gregory S. Spirakis, Naveed A. Sherwani, Craig Peterson	EDA challenges facing future microprocessor design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
24	Rolf Hakenes, Yiannos Manoli	A Novel Low-Power Microprocessor Architecture.	ICCD	2000	DBLP DOI BibTeX RDF
24	Michael T. Niemier, Michael J. Kontz, Peter M. Kogge	A design of and design tools for a novel quantum dot based microprocessor.	DAC	2000	DBLP DOI BibTeX RDF	quantum cellular automata, nanotechnology
24	Li-C. Wang, Magdy S. Abadir	Experience in Validation of PowerPCTM Microprocessor Embedded Arrays.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	assertion test generation, assertion, array, design error, logic verification, symbolic trajectory evaluation
24	Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda	FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems.	SAFECOMP	1999	DBLP DOI BibTeX RDF
24	Cheng-Ta Hsieh, Massoud Pedram	Microprocessor power estimation using profile-driven program synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
24	Li-C. Wang, Magdy S. Abadir, Jing Zeng	On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	assertion test generation, design error model, validation, ATPG, logic verification, symbolic trajectory evaluation
24	Craig Hunter, Justin Gaither	Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core.	ITC	1998	DBLP DOI BibTeX RDF
24	Michael K. Gowan, Larry L. Biro, Daniel B. Jackson	Power Considerations in the Design of the Alpha 21264 Microprocessor.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
24	Chien-Kuo V. Tien, Kelvin Lewis, Hans J. Greub, Tom Tsen, John F. McDonald 0001	Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
24	Jun Sawada, Warren A. Hunt Jr.	Trace Table Based Approach for Pipeline Microprocessor Verification.	CAV	1997	DBLP DOI BibTeX RDF
24	Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano	Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
24	Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima	Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic.	CAV	1992	DBLP DOI BibTeX RDF
24	Nikitas J. Dimopoulos, Kin F. Li, Eric G. Manning	DAME: a rule based designer of microprocessor based systems.	IEA/AIE (1)	1989	DBLP DOI BibTeX RDF	MYCIN, Prolog, LISP
24	Robert Cohn, Thomas R. Gross, Monica Lam 0001, P. S. Tseng	Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor.	ASPLOS	1989	DBLP DOI BibTeX RDF
24	Louis C. Guillou, Jean-Jacques Quisquater	A Practical Zero-Knowledge Protocol Fitted to Security Microprocessor Minimizing Both Transmission and Memory.	EUROCRYPT	1988	DBLP DOI BibTeX RDF
24	Omri Serlin	New microprocessor-based computer architectures.	AFIPS National Computer Conference	1984	DBLP DOI BibTeX RDF
24	John J. Fallin	The iRAM: an innovative approach to microprocessor memory solutions.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF
24	Alan D. Berenbaum, Michael W. Condry, Priscilla M. Lu	The Operating System and Language Support Features of the BELLMAC-32 Microprocessor.	ASPLOS	1982	DBLP DOI BibTeX RDF
24	Hoo-Min D. Toong, Svein O. Strommen, Earl R. Goodrich II	A Gemeral Multi-Microprocessor Interconnection Mechanism for Non-Numeric Processing.	Computer Architecture for Non-Numeric Processing	1980	DBLP DOI BibTeX RDF
24	Bruce E. Stock, Miguel A. Ulloa	Development of a microprocessor support facility for large organizations.	AFIPS National Computer Conference	1980	DBLP DOI BibTeX RDF
24	Ryoichi Yoshikawa, Tatsuo Kimura, Yasuhiro Nara, Hideo Aiso	A multi-microprocessor approach to a high-speed and low-cost continuous-system simulation.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
24	Thomas L. Boardman Jr.	A microprocessor architecture for digital device implementation.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
24	Chetas Mapara, Jerrin Jose	Automated Test Picker for Complex Microprocessor Verification Environment.	MTV	2019	DBLP DOI BibTeX RDF
24	Lukás Charvát, Ales Smrcka, Tomás Vojnar	Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description.	MTV	2012	DBLP DOI BibTeX RDF
24	Robert de B. Johnston, Ouiza Dahmoune	Overview of Applying Reachability Analysis to Verifying a Physical Microprocessor.	MTV	2011	DBLP DOI BibTeX RDF
24	Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda	A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores.	MTV	2008	DBLP DOI BibTeX RDF
24	Matthew W. Heath, Ian G. Harris	A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture.	MTV	2003	DBLP DOI BibTeX RDF
24	David Levitan, Thomas Thomas, Paul Tu	The PowerPC 620 Microprocessor: A High Performance Superscalar RISC Microprocessor.	COMPCON	1995	DBLP DOI BibTeX RDF
24	Brad Burgess, Mike Alexander, Ying-wai Ho, Suzanne Plummer Litch, Soummya Mallick, Deene Ogden, Sung-Ho Park, Jeff Slaton	The PowerPC 603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor.	COMPCON	1994	DBLP DOI BibTeX RDF
19	Greg James, Barry Silverman, Brian Silverman	Visualizing a classic CPU in action: the 6502.	SIGGRAPH Talks	2010	DBLP DOI BibTeX RDF	MOS 6502, simulation, visualization, microprocessor, integrated circuit, computer history
19	Carl J. Anderson	Beyond innovation: dealing with the risks and complexity of processor design in 22nm.	DAC	2009	DBLP DOI BibTeX RDF	microprocessor design, VLSI technology
19	Stanley Mazor	Intel 8080 CPU Chip Development.	IEEE Ann. Hist. Comput.	2007	DBLP DOI BibTeX RDF	Intel 8080, microchip, microprocessor, history, CPU, microcomputer
19	Zbigniew Stachniak	Intel SIM8-01: A Proto-PC.	IEEE Ann. Hist. Comput.	2007	DBLP DOI BibTeX RDF	microprocessor development system, Intel 8008, personal computer, microcomputer
19	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
19	Wangyuan Zhang, Xin Fu, Tao Li 0006, José A. B. Fortes	An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture
19	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
19	Sven Beyer, Christian Jacobi 0002, Daniel Kröning, Dirk Leinenbach, Wolfgang J. Paul	Putting it all together - Formal verification of the VAMP.	Int. J. Softw. Tools Technol. Transf.	2006	DBLP DOI BibTeX RDF	Complete microprocessor verification, Tomasulo scheduler, Cache memory interface, Model checking, Formal methods, Theorem proving, Floating point unit
19	Markus Levy	Evaluating Digital Entertainment System Performance.	Computer	2005	DBLP DOI BibTeX RDF	DENBench suite, digital media benchmarks, digital device performance, EEMBC, microprocessor systems, benchmarks, MPSoCs
19	André Seznec, Roger Espasa	Conflict-Free Accesses to Strided Vectors on a Banked Cache.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Vector microprocessor, strided vectors, conflict free access, L2 caches
19	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A highly configurable cache for low energy embedded systems.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, memory hierarchy, low energy, architecture tuning
19	Kubilay Atasu, Luca Breveglieri, Marco Macchetti	Efficient AES implementations for ARM based platforms.	SAC	2004	DBLP DOI BibTeX RDF	ARM microprocessor, AES, cache memories, code optimisation
19	Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De	Design optimizations for microprocessors at low temperature.	DAC	2004	DBLP DOI BibTeX RDF	electrothermal modeling, low temperature, refrigeration, power, microprocessor, CMOS, frequency, cooling
19	Roope Kaivola, Katherine R. Kohatsu	Proof engineering in the large: formal verification of Pentium?4 floating-point divider.	Int. J. Softw. Tools Technol. Transf.	2003	DBLP DOI BibTeX RDF	Formal verification, Microprocessor, Arithmetic
19	Jason Sungtae Kim, Michael Bedford Taylor, Jason E. Miller, David Wentzlaff	Energy characterization of a tiled architecture processor with on-chip networks.	ISLPED	2003	DBLP DOI BibTeX RDF	raw microprocessor, scalar operand network, power, tile
19	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A Highly-Configurable Cache Architecture for Embedded Systems.	ISCA	2003	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, low energy, architecture tuning
19	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.	VTS	2002	DBLP DOI BibTeX RDF	Microprocessor, Delay Testing
19	Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz	Difficult-Path Branch Prediction Using Subordinate Microthreads.	ISCA	2002	DBLP DOI BibTeX RDF	high performance microprocessor, SSMT, microthread, branch prediction, microarchitecture, SMT, helper thread
19	Kanji Hirabayashi	An Algebraic Approach to Formal Verification of Microprocessors.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	formal verification, microprocessor
19	Érika F. Cota, Fernanda Lima 0001, Sana Rezgui, Luigi Carro, Raoul Velazco, Marcelo Lubaszewski, Ricardo Reis 0001	Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	integrated circuits radiation effects, aerospace testing, built-in-testing, microprocessor testing
19	J Strother Moore	Rewriting for Symbolic Execution of State Machine Models.	CAV	2001	DBLP DOI BibTeX RDF	microprocessor simulation, pipelined machine, verification, theorem proving, Hardware modeling
19	Pradip Bose	Testing for Function and Performance: Towards an Integrated Processor Validation Methodology.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	performance test cases, bounds modeling, performance validation, integrated methodology, test generation, microprocessor testing
19	Fabian Vargas 0001, Alexandre M. Amory	Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transient-fault tolerant VHDL descriptions, area overhead analysis, reliable complex circuit design, harmful environments, reliability level, early-estimation, maximum area overhead, redundancy insertion, application minimum reliability requirement, FT-PRO tool, fault tolerant computing, redundancy, microprocessor, integrated circuit design, circuit CAD, CAD tool, transients, reliability estimation, memory elements, integrated circuit reliability, fault-tolerant circuit
19	Vivek De, Shekhar Borkar	Low power and high performance design challenges in future technologies.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	low-power design, memory, microprocessor, VLSI design
19	Li Chen, Sujit Dey	DEFUSE: A Deterministic Functional Self-Test Methodology for Processors.	VTS	2000	DBLP DOI BibTeX RDF	microprocessor, self-test, instructions, structural testing, At-speed testing
19	Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, Victor Boyadzhyan, Brent R. Blaes, Wai-Chi Fang	Novel Design for Testability of a Mixed-Signal VLSI IC.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Mixed-signal VLSI, verification, microprocessor, testability, RF
19	Steven Wallace, Nader Bagherzadeh	Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	performance analysis, Computer architecture, instruction fetching, branch target buffer, superscalar microprocessor
19	Nitzan Weinberg, David Nagle	Dynamic Elimination of Pointer-Expressions.	IEEE PACT	1998	DBLP DOI BibTeX RDF	pointer-expression, sphinx, sub-expression, SPECint95, memory address, performance analysis, compiler, locality, speech recognition, dynamic, microprocessor, mpeg, cache memory, microarchitecture, jpeg, value, spatial, memory bandwidth, data reuse, temporal, pointer, conditional execution
19	Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith	MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems.	MICRO	1997	DBLP DOI BibTeX RDF	MediaBench, SPEC benchmark suite, benchmark suite, compilation technology, experimental measurement, general-purpose computing, general-purpose systems, inner-loops, optimization, multimedia systems, instruction-level parallelism, SIMD, VLIW, communications systems, embedded applications, microprocessor architectures
19	Frédéric Pétrot, Denis Hommais, Alain Greiner	Cycle precise core based hardware/software system simulation with predictable event propagation.	EUROMICRO	1997	DBLP DOI BibTeX RDF	hardware software system simulation, predictable event propagation, cycle precise core based system simulator, digital embedded systems, Mealy signals, combinational signals, MIPS R3000, microprocessor core, PI-Bus, Pentium 120, communication, graph, C, high level synthesis, memories, directed graph, FSM, topological sort, compile-time, communicating finite state machines
19	Peter Wohl, John A. Waicukauski	Using ATPG for clock rules checking in complex scan design.	VTS	1997	DBLP DOI BibTeX RDF	clock rules checking, complex scan designs, structured DFT, automated design-rules-checking, robust set of rules, clock-rule-violation detection, fast clock verification, large microprocessor design, topological circuit analysis, zero delay, user controlled verification, capture ability, port contention, cone tracing, equivalent sources, ATPG, race conditions, computer testing, timing verification
19	Hidehiko Tanaka	Toward more advanced usage of instruction level parallelism by a very large data path processor architecture.	ISPAN	1997	DBLP DOI BibTeX RDF	very large data path processor, instruction analysis, parallel gain, parallel architectures, microprocessor, instruction level parallelism, processor architecture, performance gain
19	Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh	Efficient Testing of Clock Regenerator Circuits in Scan Designs.	DAC	1997	DBLP DOI BibTeX RDF	clock regenerators, fault simulation, test pattern generation, clocks, microprocessor testing
19	Robert Yung	Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture.	MICRO	1996	DBLP DOI BibTeX RDF	UltraSPARC, fast cycle time, in-cache prediction, instruction fetch architecture, instruction fetch unit, lower cycle-per-instruction, predictive set-associative cache, prefetch and dispatch unit, trade-off decisions, computer architecture, microprocessor
19	Keishi Sakamoto, Naoki Niihara, Toshifumi Tanaka, Kumiyo Nakakoji, Kouichi Kishida	Analysis of Software Process Improvement Experience Using the Project Visibility Index.	APSEC	1996	DBLP DOI BibTeX RDF	project visibility index, OMRON, Japanese microprocessor manufacturer, project predictability, timely delivery, review-effort ratios, project visibility, performance, quality, software process improvement, productivity, accuracy, variability, cost, capability maturity model, human resource management, qualitative analysis
19	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
19	Peter Soderquist, Miriam Leeser	An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	Newton-Raphson method, Goldschmidt's algorithm, microprocessor, Floating-point, division, square root, SRT
19	Jay K. Adams, Donald E. Thomas	Multiple-process behavioral synthesis for mixed hardware-software systems.	ISSS	1995	DBLP DOI BibTeX RDF	automated iterative improvement technique, concurrency optimization, concurrency tradeoffs, cost/performance ratio, hardware-software tradeoffs, mixed hardware-software systems, multiple-process behavioral synthesis, software engineering, resource allocation, concurrency control, controllers, optimisation, high level synthesis, logic design, multiprocessing systems, microprocessors, ASICs, application specific integrated circuits, ASIC, microprocessor chips, cost-benefit analysis
19	Marc Tremblay, Bill Joy 0001, Ken Shin	A three dimensional register file for superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows
19	Chuck Monahan, Forrest Brewer	Symbolic execution of data paths.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	combinational switching, data-path model, path constraints, bus hazards, register constraints, control encoding limitations, path-constrained model, DSP microprocessor, switching logic, connection constraints, operand constraints, scheduling, Boolean functions, Boolean functions, logic design, combinational circuits, data flow analysis, processor scheduling, symbolic execution, data flow graphs, digital signal processing chips, constraint handling, combinational logic, dataflow graphs, hazards and race conditions, memory elements
19	Egon Börger, Giuseppe Del Castillo	A formal method for provably correct composition of a real-life processor out of basic components. (The APE100 Reverse Engineering Study.	ICECCS	1995	DBLP DOI BibTeX RDF	real-life processor, APE100 Reverse Engineering, modular structuring, microprocessor zCPU, APE100 massively parallel machine, provably correct composition, formal specification, formal method, reverse engineering, parallel architectures
19	Alexander D. Stoyenko, V. Carl Hamacher, Richard C. Holt	Analyzing Hard-Real-Time Programs For Guaranteed Schedulability.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	language-independent schedulability analysis, hardware-dependent information, table-driven fashion, worst-case time bounds, prototype schedulability analyzer, partially language-dependent front-end, real-time Euclid, schedulability analysis provisions, language-dependent back-end, realistic real-time programs, multiple-microprocessor system, scheduling, real-time systems, program verification, systems analysis, high level languages, program performance, real-time language
18	Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi	CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.	HPCA	2009	DBLP DOI BibTeX RDF
18	Diana Bautista, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato	Dynamic task set partitioning based on balancing memory requirements to reduce power consumption.	ICS	2009	DBLP DOI BibTeX RDF	scheduling, real-time, multithreaded, multicore, power-aware, coarse-grain
18	Raj Amirtharajah, John R. Mashey	Guest Editors' Introduction: Hot Chips 19.	IEEE Micro	2008	DBLP DOI BibTeX RDF	wireless HD, fault tolerance, mobile computing, low-power, GPU, computer architecture, microprocessors, mainframe computing, Hot Chips 19
18	Seda Ogrenci Memik, Rajarshi Mukherjee, Min Ni, Jieyi Long	Optimizing Thermal Sensor Allocation for Microprocessors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
18	Michael Katelman, José Meseguer 0001, Santiago Escobar 0001	Directed-Logical Testing for Functional Verification of Microprocessors.	MEMOCODE	2008	DBLP DOI BibTeX RDF
18	Alexander Klimm, Oliver Sander, Jürgen Becker 0001, Sylvain Subileau	A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA.	ARCS	2008	DBLP DOI BibTeX RDF	Hyperelliptic Curve Cryptography (HECC), FPGA, embedded systems, Public Key Cryptography (PKC), reconfigurable hardware
18	Todd J. Foster, Dennis L. Lastor, Padmaraj Singh	First Silicon Functional Validation and Debug of Multicore Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
18	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
18	Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis	Speedups in embedded systems with a high-performance coprocessor datapath.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	coprocessor datapath, synthesis, kernels, Performance improvements, design flow, chaining
18	Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke	Self-calibrating Online Wearout Detection.	MICRO	2007	DBLP DOI BibTeX RDF
18	Subhomoy Chattopadhyay	Low power design techniques for nanometer design processes: 65 nm and smaller.	SBCCI	2007	DBLP DOI BibTeX RDF	65 nm, low power, embedded design
18	Charles H.-P. Wen, Li-C. Wang, Jayanta Bhadra	An incremental learning framework for estimating signal controllability in unit-level verification.	ICCAD	2007	DBLP DOI BibTeX RDF
18	Proshanta Saha, Tarek A. El-Ghazawi	Applications of Heterogeneous Computing in Hardware/Software Co-Scheduling.	AICCSA	2007	DBLP DOI BibTeX RDF
18	Subhomoy Chattopadhyay, Rakesh Patel	Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller.	VLSI Design	2007	DBLP DOI BibTeX RDF