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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 3723 publication records. Showing 3723 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
23 | Andy J. Wellings |
Multiprocessors and the Real-Time Specification for Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008), 5-7 May 2008, Orlando, Florida, USA, pp. 255-261, 2008, IEEE Computer Society, 978-0-7695-3132-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multiprocessors, SMP, RTSJ |
23 | Alex Bobrek, JoAnn M. Paul, Donald E. Thomas |
Event-based re-training of statistical contention models for heterogeneous multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 69-74, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
statistical contention modeling, simulation, performance modeling, heterogeneous multiprocessors |
23 | Karl Fürlinger, Michael Gerndt, Jack J. Dongarra |
Scalability Analysis of the SPEC OpenMP Benchmarks on Large-Scale Shared Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (2) ![In: Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27 - 30, 2007, Proceedings, Part II, pp. 815-822, 2007, Springer, 978-3-540-72585-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Shared Memory Multiprocessors, SPEC |
23 | Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis |
Comparing memory systems for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 358-368, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches |
23 | Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez |
Core fusion: accommodating software diversity in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 186-197, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
chip multiprocessors, reconfigurable architectures, software diversity |
23 | Neal K. Bambha, Shuvra S. Bhattacharyya |
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(2), pp. 99-112, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, task graphs, interconnect synthesis, Embedded multiprocessors |
23 | JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy |
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(3), pp. 431-461, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
schedulers, Computer-aided design, performance modeling, system modeling, heterogeneous multiprocessors |
23 | Guilin Chen, Mahmut T. Kandemir |
Optimizing inter-processor data locality on embedded chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings, pp. 227-236, 2005, ACM, 1-59593-091-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
chip multiprocessors, data locality, stencil computation |
23 | Corey Goldfeder |
Frequency-based code placement for embedded multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 696-699, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
frequent code, embedded systems, caching, multiprocessors, memory, code placement |
23 | Wlodzimierz M. Zuberek |
Enhanced Interleaved Multithreaded Multiprocessors and Their Performance Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 16-18 June 2004, Hamilton, Canada, pp. 7-15, 2004, IEEE Computer Society, 0-7695-2077-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Interleaved multithreaded architectures, performance analysis, timed Petri nets, distributed-memory multiprocessors, event-driven simulation |
23 | Mahmut T. Kandemir, Ozcan Ozturk 0001, Mustafa Karaköy |
Dynamic on-chip memory management for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 14-23, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
chip multiprocessors, optimizing compiler, memory bank |
23 | Gene Eu Jan, Yuan-Shin Hwang |
An Efficient Algorithm for Perfect Load Balancing on Hypercube Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 25(1), pp. 5-15, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
dimension exchange, regular distributions, token distribution problem, load balancing, multiprocessors, hypercube |
23 | Sanjoy K. Baruah, Joël Goossens |
Rate-Monotonic Scheduling on Uniform Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(7), pp. 966-970, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Uniform multiprocessors, periodic tasks, global scheduling, rate-monotonic algorithm, static priorities |
23 | Mainak Chaudhuri, Mark A. Heinrich, Chris Holt, Jaswinder Pal Singh, Edward Rothberg, John L. Hennessy |
Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(7), pp. 862-880, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
flexible node controller, latency, bandwidth, queuing model, Occupancy, distributed shared memory multiprocessors, communication controller |
23 | Shaz Qadeer |
Verifying Sequential Consistency on Shared-Memory Multiprocessors by Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(8), pp. 730-741, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
specifying and verifying and reasoning about programs, model checking, verification, multiprocessors, Logic design |
23 | Tong Li 0003, Alvin R. Lebeck, Daniel J. Sorin |
Quantifying instruction criticality for shared memory multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 7-9, 2003, San Diego, California, USA (part of FCRC 2003), pp. 128-137, 2003, ACM, 1-58113-661-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
shared memory multiprocessors, slack, critical path analysis |
23 | Wlodzimierz M. Zuberek |
Approximate Simulation of Distributed-Memory Multithreaded Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 35th Annual Simulation Symposium (ANSS-35 2002), San Diego, California, USA, 14-18 April 2002, pp. 107-114, 2002, IEEE Computer Society, 0-7695-1552-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
performance analysis, discrete-event simulation, timed Petri nets, distributed-memory multiprocessors, block multithreading, approximate models |
23 | Iffat H. Kazi, David J. Lilja |
Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(9), pp. 952-966, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Runtime parallelization, thread pipelining, superthreaded architecture, shared-memory multiprocessors, speculative execution, coarse-grained parallelization |
23 | Wai-Sum Lin, Rynson W. H. Lau, Kai Hwang 0001, Xiaola Lin, Paul Y. S. Cheung |
Adaptive Parallel Rendering on Multiprocessors and Workstation Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(3), pp. 241-258, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
polygon rasterization, MPI programming, speedup and efficiency and scalable performance, load balancing, Computer graphics, symmetric multiprocessors, parallel rendering, cluster of workstations, supersampling |
23 | Po-Jen Chuang, Chih-Ming Wu |
An Efficient Recognition-Complete Processor Allocation Strategy for k-ary n-cube Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(5), pp. 485-490, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Full subcube recognition, internal and external fragmentation, k-ary n-cube multiprocessors, performance evaluation, time complexity, processor allocation |
23 | Yeimkuan Chang, Laxmi N. Bhuyan |
An Efficient Tree Cache Coherence Protocol for Distributed Shared Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(3), pp. 352-360, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
tree-based directory protocols, shared memory, Cache coherence, execution-driven simulation, large scale multiprocessors |
23 | Yu-Kwong Kwok, Ishfaq Ahmad |
FASTEST: A Practical Low-Complexity Algorithm for Compile-Time Assignment of Parallel Programs to Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 10(2), pp. 147-159, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
random neighborhood search, parallel algorithm, parallel processing, multiprocessors, Automatic parallelization, task graphs, compile-time scheduling, parallel programming tool |
23 | Yu-Kwong Kwok, Ishfaq Ahmad |
Static scheduling algorithms for allocating directed task graphs to multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 31(4), pp. 406-471, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
parallel processing, software tools, multiprocessors, DAG, automatic parallelization, task graphs, static scheduling |
23 | Jim Nilsson, Fredrik Dahlgren |
Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the International Conference on Parallel Processing 1999, ICPP 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 246-257, 1999, IEEE Computer Society, 0-7695-0350-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
load-store sequences, performance evaluation, databases, operating systems, multiprocessors, computer architecture, transaction processing, cache coherence protocols |
23 | Fredrik Dahlgren, Michel Dubois 0001, Per Stenström |
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(10), pp. 1041-1055, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
competitive-update protocols, write caches, performance evaluation, prefetching, Shared-memory multiprocessors, cache-coherence protocols |
23 | Lars Lundberg, Håkan Lennerstad |
Using Recorded Values for Bounding the Minimum Completion Time in Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(4), pp. 346-358, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Parallel program scheduling, optimal performance bounds, multiprocessors with clusters, synchronizing processes, information from previous executions |
23 | Abdul Waheed, Jerry C. Yan |
Performance Modeling and Measurement of Parallelized Code for Distributed Shared Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 1998, Proceedings of the Sixth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 19-24 July, 1998, Montreal, Canada, pp. 161-166, 1998, IEEE Computer Society, 0-8186-8566-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
shared memory multiprocessors and cache performance, parallelization, Performance modeling, performance measurement |
23 | Yu-Kwong Kwok, Ishfaq Ahmad |
A Parallel Algorithm for Compile-Time Scheduling of Parallel Programs on Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 90-101, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
parallel randomized algorithm, PFAST algorithm, parallel fast assignment, parallel random search technique, computer-aided parallelization, computer-aided scheduling tool, CASCH tool, running time constraints, parallel programming, parallel programs, multiprocessors, time complexity, directed acyclic graphs, execution times, linear-time algorithm, Intel Paragon, compile-time scheduling |
23 | Ramakrishnan Rajamony, Alan L. Cox |
Optimally Synchronizing DOACROSS Loops on Shared Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 214-224, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
synchronization, shared memory multiprocessors, Doacross loops |
23 | Jonas Skeppstedt |
Overcoming Limitations of Prefetching in Multiprocessors by Compiler-Initiated Coherence Actions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 272-, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
compiler-initiated coherence, CC-NUMA multiprocessor, compiler-controlled prefetching, read-stall time, write-latency, read-latency, memory access latency reduction, migratory sharing, parallel architectures, multiprocessors, prefetching, prefetch, compiler-analysis |
23 | Anand Sivasubramaniam |
Reducing the Communication Overhead of Dynamic Applications on Shared Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 194-203, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
dynamic communication behavior, invalidation-based protocols, receiver-initiated communication, write overheads, redundant updates, intelligent sender-initiated data transfer mechanisms, competitive update mechanism, scalability, geographical information systems, shared memory multiprocessors, shared memory systems, data transfer, communication overhead, temporal locality, spatial locality, shared memory architectures, shared address space, performance benefits, dynamic applications |
23 | Liuxi Yang, Josep Torrellas |
Speeding up the Memory Hierarchy in Flat COMA Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 4-13, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
cache-only memory architectures, cache coherence protocols, cache hierarchies, scalable shared-memory multiprocessors |
23 | Nectarios Koziris, George K. Papakonstantinou, Panayotis Tsanakas |
Mapping nested loops onto distributed memory multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 11-13 December 1997, Seoul, Korea, Proceedings, pp. 35-, 1997, IEEE Computer Society, 0-8186-8227-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Chain grouping, low complexity method, index space partitioning, intercommunication requirements, distributed mesh connected architectures, minimum time displacement, discrete groups, optimal makespan, uniform chain, dependence vector, optimal hyperplane scheduling, intragroup computations, partitioned groups, processor utilisation, optimal hyperplane time schedule, distributed memory systems, communication delays, nested loops, distributed memory multiprocessors, loop iterations, space mapping, hyperplane method |
23 | Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu, Wei Shu |
Automatic Parallelization and Scheduling of Programs on Multiprocessors using CASCH. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 288-291, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Task Graphs Multiprocessors, Scheduling, Compiler, Software Tool, Code Generation, Program Parallelization |
23 | Po-Jen Chuang, Chih-Ming Wu |
Processor Allocation in k-ary n-cube Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 211-214, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Full subcube recognition, internal and external fragmentations, k-ary n-cube multiprocessors, performance evaluation, processor allocation |
23 | Dannie Durand, Thierry Montaut, Lionel Kervella, William Jalby |
Impact of Memory Contention on Dynamic Scheduling on NUMA Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(11), pp. 1201-1214, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
NUMA multiprocessors, load balancing, Dynamic scheduling, memory performance, self-scheduling |
23 | Manuel Mollar, Vicente Hernández |
Computing the Singular Values of the Product of Two Matrices in Distributed Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 15-21, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
product singular value decomposition, Kogbetliantz algorithm, plane rotations, Control theory, PVM, transputer, distributed memory multiprocessors, Parallel C |
23 | Xiaotie Deng, Binhai Zhu |
A Randomized Algorithm for Voronoi Diagram of Line Segments on Coarse-Grained Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 192-198, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
coarse grained multiprocessors, randomized parallel algorithm, local operations, global-operations, messages per processor, global data dependency, communication phases, parallel algorithms, computational complexity, computational geometry, probability, randomized algorithm, Voronoi diagram, parallel machines, computation time, line segments, randomised algorithms, random-access storage, CRCW PRAM model |
23 | Ricardo Bianchini, Thomas J. LeBlanc, Jack E. Veenstra |
Categorizing Network Traffic in Update-Based Protocols on Scalable Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 142-151, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Shared-memory multiprocessors, Network traffic, Coherence protocols |
23 | Christoph Siegelin, Ciaran O'Donnell, Ulrich Finger |
Efficient Simulation of Multiprocessors through Finite State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 202-206, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
event-driven multiprocessor simulators, memory behaviour, cache behaviour, simulation, multiprocessors, finite state machines, finite state machines |
23 | Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina |
A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 207-214, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
software approach, user references, virtual-to-physical address translation, kernel reference stream, general-purpose machine, multitasking operating system, performance evaluation, performance evaluation, shared-memory multiprocessor, process scheduling, hybrid approach, trace generation, shared-bus multiprocessors |
23 | Qiang Li, David B. Gustavson |
Fat-tree for local area multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 32-36, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
local area multiprocessors, LAMP, high-performance low-cost parallel computing, LAN-size area, remote data cache, high performance multiprocessor, point-to-point physical connections, high system throughput, fat-tree topology, cable length, link clock speeds, biCMOS chips, performance evaluation, parallel architectures, parallel architecture, multiprocessor interconnection networks, local area networks, latency, packet switching, packet switch, CMOS, shared memory systems, distributed memory systems, simulation results, cache storage, system buses, SCI, buffer requirements, distributed-shared-memory multiprocessor, scalable coherent interface |
23 | Markus Schwiegershausen, Peter Pirsch |
A system level design methodology for the optimization of heterogeneous multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 162-169, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
parametrizable processor modules, programmable processors, system level design methodology, optimization, real-time systems, image processing, linear programming, optimisation, integer programming, multiprocessing systems, heterogeneous systems, mixed integer linear programming, CAD tool, image processing algorithms, heterogeneous multiprocessors, mathematical framework |
23 | Farnaz Mounes-Toussi, David J. Lilja |
Write buffer design for cache-coherent shared-memory multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 506-511, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
write-buffer configurations, one word per buffer entry, one block per buffer entry, write-through, write-back, competitive-performance, shared-memory multiprocessors, shared memory systems, cache-coherent, memory architecture, buffer storage, cache storage, execution-driven simulator, write policies |
23 | Alexandre E. Eichenberger, Santosh G. Abraham |
Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 262-271, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fuzzy barriers, overall execution time, parallel region, nondeterministic load imbalance modelling, random replacement policy, processor caches, cyclic access stream, interprocessor synchronization, 64-processor KSR system, Kendall Square Research system, random first-level caches, performance evaluation, resource allocation, concurrency control, synchronisation, shared memory systems, cache storage, variance, performance improvement, network contention, hit ratio, scalable shared-memory multiprocessors |
23 | Prasant Mohapatra, Chita R. Das, Tse-Yun Feng |
Performance Analysis of Cluster-Based Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(1), pp. 109-114, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
cluster-based multiprocessors, M/D/1/L queues, finite buffer behavior, system level analysis, results validation, buffer length, bottleneck centre identification, design configurations, simulation, simulation, performance evaluation, performance analysis, interconnection network, throughput, multiprocessor interconnection networks, queueing theory, multiprocessing systems, buffer storage, queueing model, design alternatives, decomposition technique, subsystems, processor utilization, average delay, deterministic service time |
23 | Syed Masud Mahmud |
Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(7), pp. 789-805, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
multilevel bus networks, hierarchical multiprocessors, partial multiple bus system, bus architecture, hierarchical multiprocessor design, synchronous multilevel bus systems, asynchronous multilevel bus systems, hierarchical reference model, MVA algorithm, performance evaluation, fault tolerance, performance analysis, parallel architectures, connections, queueing theory, multiprocessing systems, analytical models, bandwidth, queueing networks, switches, simulation models, memory bandwidth, packet-switched networks, cost-effectiveness, system buses, local computations, memory modules |
23 | David M. Koppelman |
Reducing PE/Memory Traffic in Multiprocessors by the Difference Coding of Memory Addresses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(11), pp. 1156-1168, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
memory traffic, difference coding, memory addresses, shared memory parallel computer, trace-drivensimulation, traffic volume, lower cost, lower latency network, networklatency, virtual machines, multiprocessors, message passing, multiprocessor interconnection networks, memories, shared memory systems, storage management, buffer storage, processing elements, coherent cache |
23 | Alvin R. Lebeck, Gurindar S. Sohi |
Request Combining in Multiprocessors with Arbitrary Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(11), pp. 1140-1155, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
arbitrary interconnection networks, shared memory location, combining set, processor elements, simulationresults, parallel architectures, virtual machines, multiprocessors, message passing, multiprocessor interconnection networks, shared memory systems, design space, hot spots, message routing, parallel access, classification scheme, combining strategies |
23 | C. Selvakumar, C. Siva Ram Murthy |
Scheduling Precedence Constrained Task Graphs with Non-Negligible Intertask Communication onto Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(3), pp. 328-336, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
precedence constrained task graphs, scheduling, parallel algorithms, computational complexity, parallel program, graph theory, multiprocessors, multiprocessing systems, heuristic algorithm, heuristic programming, list scheduling, communication channels, multiprocessing programs, completion time, multiprocessor interconnectionnetworks, intertask communication, multiprocessor scheduling problem |
23 | Sibabrata Ray, Hong Jiang, Jitender S. Deogun |
A parallel algorithm for mapping a special class of task graphs onto linear array multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 1994 ACM Symposium on Applied Computing, SAC'94, Phoenix, AZ, USA, March 6-8, 1994, pp. 473-477, 1994, ACM, 0-89791-647-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
task graph partitioning, parallel algorithms, computational complexity, load balancing, multiprocessors |
23 | Bülent Abali, Füsun Özgüner, Abdulla Bataineh |
Balanced Parallel Sort on Hypercube Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(5), pp. 572-581, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
parallel selection algorithm, conflict-free routing, 16-node hypercube, hypercubenetworks, parallel algorithms, computational complexity, hypercube, sorting, parallel sort, hypercube multiprocessors |
23 | Siddhartha Chatterjee |
Compiling Nested Data-Parallel Programs for Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 15(3), pp. 400-462, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
compilers, shared-memory multiprocessors, data parallelism |
23 | Anoop Gupta, Wolf-Dietrich Weber |
Cache Invalidation Patterns in Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(7), pp. 794-810, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
cache invalidation patterns, high-level objects, conceptual tool, invalidation patterns, directory-based schemes, simulations, parallel programs, parallel programming, multiprocessing systems, shared-memory multiprocessors, digital simulation, buffer storage, data objects, classification scheme |
23 | MenChow Chiang, Gurindar S. Sohi |
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(3), pp. 297-317, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
throughput-oriented environment, overall throughput, design choices, mean value analysis analytical models, trace-driven simulation analysis, cache block sizes, cache set associativity, multiprocessor throughput, performance evaluation, performance, multiprocessing systems, digital simulation, shared bus multiprocessors |
23 | Shantanu Dutt, John P. Hayes |
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(5), pp. 588-598, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
node-covering design, covering graphs, VLSI layout area minimization, distributed reconfiguration, software recovery, local spares, parallel algorithms, computational complexity, VLSI, graph theory, fault tolerant computing, multiprocessing systems, circuit layout CAD, incremental design, state information, fault-tolerant multiprocessors |
23 | Chien-Min Wang, Sheng-De Wang |
Efficient Processor Assignment Algorithms and Loop Transformations for Executing Nested Parallel Loops on Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(1), pp. 71-82, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
processor assignment algorithms, nested parallel loops, performance, parallel algorithms, parallel programming, multiprocessors, program compilers, loop transformations, parallel processors, parallel execution |
23 | Ravi Ganesan, Shlomo Weiss |
Scalar Memory References in Pipelined Multiprocessors: A Performance Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 18(1), pp. 78-86, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
scalar memory references, pipelined multiprocessors, high memory bandwidth, memory cycle, processor cycle time, bank reservation time, bank busy time, performance evaluation, probability, Markov chain, Markov processes, parallel machines, Markov models, storage management, simulation results, pipeline processing, state space, transition probabilities, pipelined computers, memory bank |
23 | Krishnan Padmanabhan |
Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 2(4), pp. 385-397, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
control tags, traffic capacity, binary shuffle-exchange networks, distributed tag-based controlalgorithm, stochastic environment, buffercapacity, performance evaluation, performance, architecture, multiprocessors, connectivity, multiprocessor interconnection networks, multiprocessing systems, structural properties, destination, source, dynamic properties, parallelarchitectures |
23 | Ming-Syan Chen, Kang G. Shin, Dilip D. Kandlur |
Addressing, Routing, and Broadcasting in Hexagonal Mesh Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(1), pp. 10-18, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
hexagonal mesh multiprocessors, six-regular graphs, H-meshes, square meshes, routing, graph theory, broadcasting, hypercubes, multiprocessor interconnection network, multiprocessor interconnection networks, trees, addressing |
23 | Vijay Balasubramanian, Prithviraj Banerjee |
Compiler-Assisted Synthesis of Algorithm-Based Checking in Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(4), pp. 436-446, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
compiler assisted synthesis, algorithm-based checking, Fortran DO loops, LINPACK routine, DGEFA, fault tolerant computing, concurrency control, multiprocessors, multiprocessing systems, matrix multiplication, linear transformations, nonlinear transformations |
23 | Ming-Syan Chen, Kang G. Shin |
Subcube Allocation and Task Migration in Hypercube Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(9), pp. 1146-1155, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
binary reflected Gray code, BRGC, GC strategy, subcube recognition, extended binary code, EBC, extended Gray code, EGC, multiprocessing systems, task migration, hypercube multiprocessors, binary code, subcubes |
23 | David Kotz, Carla Schlatter Ellis |
Prefetching in File Systems for MIMD Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(2), pp. 218-230, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
concurrent OS, disc caching, MIMD multiprocessors, interleaved file system, Butterfly Plus multiprocessor, I/O requests, performance evaluation, performance, parallel computation, caching, prefetching, multiprocessing systems, file systems, buffer storage, execution time, file organisation, hit ratio |
23 | Donald F. Towsley, C. Gary Rommel, John A. Stankovic |
Analysis of Fork-Join Program Response Times on Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(3), pp. 286-303, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
fork-join program response times, task scheduling processor sharing, job scheduling processor sharing, system parameter values, performance evaluation, performance, multiprocessors, multiprocessing systems |
23 | Prithviraj Banerjee, Mark Howard Jones, Jeff S. Sargent |
Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(1), pp. 91-106, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
cell placement, two-dimensional area, n-dimensional hypercube, cell exchanges, cell displacements, parallel cost evaluation, tree broadcasting strategy, dynamic parallel annealing schedule, heuristic cell coloring, adaptive sequence control, Intel iPSC-2/D4/MX hypercube, performance evaluation, parallel algorithms, parallel algorithms, synchronization, simulated annealing, message passing, optimisation, errors, circuit layout CAD, distributed memory, cost function, distributed data structure, hypercube multiprocessors |
23 | Kun-Lung Wu, W. Kent Fuchs, Janak H. Patel |
Error Recovery in Shared Memory Multiprocessors Using Private Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(2), pp. 231-240, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
processor transient faults, user-transparent checkpointing, checkpointed computation state, recovery stacks, rollback propagation, rapidrecovery, fault tolerance, fault tolerant computing, multiprocessor interconnection networks, multiprocessing systems, shared memory multiprocessors, system recovery, buffer storage, cache coherence protocols, performance degradation, processor utilization, private caches, error latency |
23 | Vijay Balasubramanian, Prithviraj Banerjee |
Tradeoffs in the Design of Efficient Algorithm-Based Error Detection Schemes for Hypercube Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 16(2), pp. 183-196, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
algorithm-based error detection, 16-processor Intel iPSC-2/D4/MX, software engineering, multiprocessing systems, error detection, encoding, encoding, linear algebra, QR factorization, numerical linear algebra, hypercube multiprocessors, sum-of-squares, checksum |
23 | Bohdan L. Bodnar, A. C. Liu |
Modeling and Performance Analysis of Single-Bus Tightly-Coupled Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(3), pp. 465-470, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
global performance metrics, single-bus tightly-coupled multiprocessors, hierarchical stochastic queuing model, single queue/server pair, probabilistic task migration, CPU sensitivity analysis, performance evaluation, modelling, performance analysis, shared memory, multiprocessing systems, processing elements |
23 | Jih-Kwon Peir, Ron Cytron |
Minimum Distance: A Method for Partitioning Recurrences for Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(8), pp. 1203-1211, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
partitioning recurrences, nonvectorizable uniform recurrences, totally independent computations, clusters, multiprocessors, computer networks, multiprocessing systems, parallel execution, numerical stability, minimum distance |
23 | Seth Abraham, Krishnan Padmanabhan |
Performance of the Direct Binary n-Cube Network for Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(7), pp. 1000-1011, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
direct binary n-cube network, equiprobable distribution, message destinations, simulations, performance evaluation, broadcasts, multiprocessors, multiprocessor interconnection networks, packet switching, performance prediction, inferences, mathematical model, hot spots, crossbar |
23 | Thomas E. Anderson, Edward D. Lazowska, Henry M. Levy |
The Performance Implications of Thread Management Alternatives for Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(12), pp. 1631-1644, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
performance implications, thread management, critical resource waiting, performance evaluation, data structure, data structures, latency, multiprocessing systems, shared-memory multiprocessors, locking, operating systems (computers), fine-grained parallelism |
23 | P. Sadayappan, V. Visvanathan |
Circuit Simulation on Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(12), pp. 1634-1642, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
vector multiprocessor, sparse matrix solution, parallel processing, parallelization, shared-memory multiprocessors, digital simulation, circuit CAD, circuit simulator, parallel implementation |
23 | Michel Dubois 0001 |
Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(1), pp. 58-70, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
shared interleaved memory, cache-based multiprocessors, general-purpose computing, dynamic instruction mix statistics, performance evaluation, performance, throughput, multiprocessing systems, buffer storage, multitasking, private cache, multiple buses |
23 | Tomás Lang, Mateo Valero, Ignacio Alegre |
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(12), pp. 1227-1234, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
multiprocessors, shared memory, memory bandwidth, Bus arbitration, multiple buses |
22 | Daniel R. Johnson, Matthew R. Johnson 0003, John H. Kelm, William Tuohy, Steven S. Lumetta, Sanjay J. Patel |
Rigel: A 1, 024-Core Single-Chip Accelerator Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 31(4), pp. 30-41, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Multiple data-stream architectures (multiprocessors), multiple data processors, single-chip multiprocessors, parallel architectures, multicore, parallel processors, multiple instruction |
22 | James R. Larus |
Compiling for Shared-Memory and Message-Passing Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LOPLAS ![In: LOPLAS 2(1-4), pp. 165-180, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
directory protocols, message-passing multiprocessors, compilers, shared-memory multiprocessors, cache coherence, memory systems, parallel programming languages |
20 | Peter Sewell |
Memory, an elusive abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 9th International Symposium on Memory Management, ISMM 2010, Toronto, Ontario, Canada, June 5-6, 2010, pp. 51-52, 2010, ACM, 978-1-4503-0054-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
semantics, relaxed memory models |
20 | Seungrok Jung, Jungsoo Kim, Sangkwon Na, Chong-Min Kyung |
Energy-aware instruction-set customization for real-time embedded multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 335-338, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
DVFS, instruction set extensions, configurable processors |
20 | Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksrishnan |
Energy Based Design Space Exploration of Multiprocessor VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 307-310, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke |
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 25-36, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Andrew A. Chien |
Pervasive parallel computing: an historic opportunity for innovation in programming and architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2007, San Jose, California, USA, March 14-17, 2007, pp. 160, 2007, ACM, 978-1-59593-602-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Riad Ben Mouhoub, Omar Hammami |
Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Abhik Roychoudhury |
Formal Reasoning about Hardware and Software Memory Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods, ICFEM 2002 Shanghai, China, October 21-25, 2002, Proceedings, pp. 423-434, 2002, Springer, 3-540-00029-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Panagiotis E. Hadjidoukas, Eleftherios D. Polychronopoulos, Theodore S. Papatheodorou |
Integrating MPI and Nanothreads Programming Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 10th Euromicro Workshop on Parallel, Distributed and Network-Based Processing (PDP 2002), 9-11 January 2002, Canary Islands, Spain, pp. 309-, 2002, IEEE Computer Society, 0-7695-1444-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Clusters, MPI, Multithreading, OpenMP, Runtime Systems |
20 | Sandhya Dwarkadas, Kourosh Gharachorloo, Leonidas I. Kontothanassis, Daniel J. Scales, Michael L. Scott, Robert Stets |
Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 260-269, 1999, IEEE Computer Society, 0-7695-0004-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Donald Yeung, John Kubiatowicz, Anant Agarwal |
MGS: A Multigrain Shared Memory System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 44-55, 1996, ACM, 0-89791-786-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
20 | Phillip B. Gibbons, Ephraim Korach |
On Testing Cache-Coherent Shared Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: Proceedings of the 6th Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA '94, Cape May, New Jersey, USA, June 27-29, 1994, pp. 177-188, 1994, ACM, 0-89791-671-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
20 | J. Gregory Morrisett, Andrew P. Tolmach |
Procs and Locks: A Portable Multiprocessing Platform for Standard ML of New Jersey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the Fourth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), San Diego, California, USA, May 19-22, 1993, pp. 198-207, 1993, ACM, 0-89791-589-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Standard ML |
20 | Hsin-Chu Chen |
Parallel SAS multicluster algorithms for solving linear systems with reflexive coefficient matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 6th international conference on Supercomputing, ICS 1992, Washington, DC, USA, July 19-24, 1992, pp. 447-455, 1992, ACM, 0-89791-485-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
20 | Pradeep K. Dubey, George B. Adams III, Michael J. Flynn |
Spectrum of choices: superpipelined, superscalar, or multiprocessor? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPDP ![In: Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, SPDP 1991, 2-5 December 1991, Dallas, Texas, USA, pp. 233-240, 1991, IEEE Computer Society, 0-8186-2310-1. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
20 | Richard P. LaRowe Jr., Carla Schlatter Ellis, Laurence S. Kaplan |
The Robustness of NUMA Memory Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOSP ![In: Proceedings of the Thirteenth ACM Symposium on Operating System Principles, SOSP 1991, Asilomar Conference Center, Pacific Grove, California, USA, October 13-16, 1991, pp. 137-151, 1991, ACM, 0-89791-447-3. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
20 | Anant Agarwal, Mathews Cherian |
Adaptive Backoff Synchronization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 396-406, 1989, ACM, 0-89791-319-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
20 | David L. Black 0001, Richard F. Rashid, David B. Golub, Charles R. Hill, Robert V. Baron |
Translation Lookaside Buffer Consistency: A Software Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 113-122, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
UNIX |
20 | Ralph Butler, Nicholas T. Karonis |
Exploitation of Parallelism in Prototypical Deduction Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CADE ![In: 9th International Conference on Automated Deduction, Argonne, Illinois, USA, May 23-26, 1988, Proceedings, pp. 333-343, 1988, Springer, 3-540-19343-X. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
20 | Richard F. Rashid, Avadis Tevanian, Michael Young, David B. Golub, Robert V. Baron, David L. Black 0001, William J. Bolosky, Jonathan Chew |
Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 31-39, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
18 | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
Energy-efficient redundant execution for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 143-146, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
redundant execution, microarchitecture, transient faults, permanent faults |
18 | Abhishek Bhattacharjee, Margaret Martonosi |
Inter-core cooperative TLB for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 359-370, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parallelism, prefetching, translation lookaside buffer |
18 | Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang |
SHARP control: controlled shared cache management in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 517-528, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk 0001 |
Optimizing shared cache behavior of chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 505-516, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim |
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 45-55, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adaptive, GPU, mapping, heterogeneous, multicore, dynamic compilation |
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