Search results for "processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	A. Duksu Oh, Hyeong-Ah Choi	Generalized Measures of Fault Tolerance in n-Cube Networks.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	n-cube network, nonfaulty processor, fault tolerance, multiprocessor interconnection networks, processor failures, fault tolerantcomputing
23	Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda	Measurement of power supply noise tolerance of self-timed processor.	DDECS	2009	DBLP DOI BibTeX RDF
23	Abdulah Abdulah Zadeh	High performance synchronized dual elliptic curve crypto-processor.	CCECE	2009	DBLP DOI BibTeX RDF
23	Vimal K. Reddy, Eric Rotenberg	Coverage of a microarchitecture-level fault check regimen in a superscalar processor.	DSN	2008	DBLP DOI BibTeX RDF
23	Ying Zhang 0032, Xuejun Yang, Guibin Wang, Ian Rogers, Gen Li 0002, Yu Deng 0001, Xiaobo Yan	Scientific Computing Applications on a Stream Processor.	ISPASS	2008	DBLP DOI BibTeX RDF
23	Meilian Xu, Parimala Thulasiraman	Finite-difference time-domain on the cell/B.E. processor.	IPDPS	2008	DBLP DOI BibTeX RDF
23	Xunying Zhang, Xubang Shen	A Power-Efficient Floating-Point Co-processor Design.	CSSE (4)	2008	DBLP DOI BibTeX RDF
23	Ming-che Lai, Jianjun Guo, Zhuxi Zhang, Zhiying Wang	Using an Automated Approach to Explore and Design a High-Efficiency Processor Element for the Multimedia Domain.	CISIS	2008	DBLP DOI BibTeX RDF
23	Guilin Chen, Mahmut T. Kandemir	An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF
23	Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao	Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
23	Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger	Implementation and Evaluation of a Dynamically Routed Processor Operand Network.	NOCS	2007	DBLP DOI BibTeX RDF
23	Hossein Pourreza, Peter Graham	On the Programming Impact ofMulti-Core, Multi-Processor Nodes inMPI Clusters.	HPCS	2007	DBLP DOI BibTeX RDF
23	Tai-Yi Huang, Yu-Che Tsai, Edward T.-H. Chu	A Near-optimal Solution for the Heterogeneous Multi-processor Single-level Voltage Setup Problem.	IPDPS	2007	DBLP DOI BibTeX RDF
23	Götz Kappen, S. el Bahri, O. Priebe, Tobias G. Noll	Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers.	ASAP	2007	DBLP DOI BibTeX RDF
23	Ming-che Lai, Jianjun Guo, Lv Yasuai, Kui Dai, Zhiying Wang 0003	The Research of an Embedded Processor Element for Multimedia Domain.	MCAM	2007	DBLP DOI BibTeX RDF
23	Pavel Krcál, Martin Stigge, Wang Yi 0001	Multi-processor Schedulability Analysis of Preemptive Real-Time Tasks with Variable Execution Times.	FORMATS	2007	DBLP DOI BibTeX RDF
23	Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt	Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths.	MICRO	2006	DBLP DOI BibTeX RDF
23	Christopher Kachris, Stamatis Vassiliadis	Analysis of a reconfigurable network processor.	IPDPS	2006	DBLP DOI BibTeX RDF
23	Weiwei Ma, M. E. Kaye, D. M. Luke, R. Doraiswami	An FPGA-Based Singular Value Decomposition Processor.	CCECE	2006	DBLP DOI BibTeX RDF
23	Cristian Constantinescu	Dependability evaluation of a fault-tolerant processor by GSPN modeling.	IEEE Trans. Reliab.	2005	DBLP DOI BibTeX RDF
23	Emre Özer 0001, Thomas M. Conte	High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	Multithreaded processors, VLIW architectures, modeling of computer architecture
23	Julita Corbalán, Xavier Martorell, Jesús Labarta	Performance-Driven Processor Allocation.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	Operating system algorithms, performance analysis, OpenMP, multiprocessor scheduling, runtime analysis
23	Alexandre E. Eichenberger, Kathryn M. O'Brien, Kevin O'Brien, Peng Wu 0001, Tong Chen 0001, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind	Optimizing Compiler for the CELL Processor.	IEEE PACT	2005	DBLP DOI BibTeX RDF
23	Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura	A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection.	IPDPS	2005	DBLP DOI BibTeX RDF
23	Min Li, Xiaobo Wu, Zihua Guo, Richard Yao, Xiaolang Yan	Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction.	ICME	2005	DBLP DOI BibTeX RDF
23	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-based delay fault self-testing of pipelined processor cores.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
23	Ahmet Bindal, Silvio Brugada, T. Ha, Willie Sana, Mandeep Singh, Vinilkant Tejaswi, David Wyland	A Simple Micro-Threaded Data-Driven Processor.	DSD	2004	DBLP DOI BibTeX RDF
23	Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas	Hiding Synchronization Delays in a GALS Processor Microarchitecture.	ASYNC	2004	DBLP DOI BibTeX RDF
23	Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki	Instruction set and functional unit synthesis for SIMD processor cores.	ASP-DAC	2004	DBLP DOI BibTeX RDF
23	Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta, Leonard Rarick, Shreyas Sundaram	A Public-Key Cryptographic Processor for RSA and ECC.	ASAP	2004	DBLP DOI BibTeX RDF
23	Maya B. Gokhale, Janette Frigo, Kevin McCabe, James Theiler, Christophe Wolinski, Dominique Lavenier	Experience with a Hybrid Processor: K-Means Clustering.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	configurable system on a chip, CSOC, Excalibur, FPGA, image processing, k-means clustering
23	Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Low-Cost Software-Based Self-Testing of RISC Processor Cores.	DATE	2003	DBLP DOI BibTeX RDF
23	Minoru Fujishima, Kaoru Saito, M. Onouchi, Koichiro Hoh	High-speed processor for quantum-computing emulation and its applications.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
23	Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar	Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.	VLSI Design	2003	DBLP DOI BibTeX RDF
23	Christopher W. Milner, Jack W. Davidson	Quick piping: a fast, high-level model for describing processor pipelines.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	embedded systems, pipelines, modeling of computer architecture
23	Fan Zhang 0097, Samuel T. Chanson	Processor Voltage Scheduling for Real-Time Tasks with Non-Preemptible Sections.	RTSS	2002	DBLP DOI BibTeX RDF
23	David Parello, Olivier Temam, Jean-Marie Verdun	On increasing architecture awareness in program optimizations to bridge the gap between peak and sustained processor performance: matrix-multiply revisited.	SC	2002	DBLP DOI BibTeX RDF
23	Craig B. Zilles, Gurindar S. Sohi	A Programmable Co-Processor for Profiling.	HPCA	2001	DBLP DOI BibTeX RDF
23	S.-M. Kim, Sathiamoorthy Manoharan	A Parallel Processor Architecture for Prefetching.	ISPAN	2000	DBLP DOI BibTeX RDF
23	Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki	A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing.	ASP-DAC	1999	DBLP DOI BibTeX RDF
23	Roberto Sarmiento, V. de Armas, José Francisco López, Juan A. Montiel-Nelson, Antonio Núñez	A CORDIC processor for FFT computation and its implementation using gallium arsenide technology.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
23	Koray Öner, Michel Dubois 0001	Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF	SPARC
23	Andrew Wolfe, John Paul Shen	Flexible processors: a promising application-specific processor design approach.	MICRO	1988	DBLP BibTeX RDF
23	Richard W. Moulton	Measurement of processor occupancy in a cyclic non-preemptive real-time control system.	ACM Conference on Computer Science	1985	DBLP DOI BibTeX RDF
23	Mikiko Sato, Yuji Sato, Mitaro Namiki	Proposal of a multi-core processor architecture for effective evolutionary computation.	GECCO	2010	DBLP DOI BibTeX RDF	genegic algorithms, parallel computing, evolutionary computation, multi-core processor
23	Tanya René Beelders, Pieter J. Blignaut, Theo McDonald, Engela Dednam	Measuring User Performance for Different Interfaces Using a Word Processor Prototype.	HCI (1)	2009	DBLP DOI BibTeX RDF	word processor, text buttons, Usability, localization, icons
23	Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani	An architecture framework for an adaptive extensible processor.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Reconfigurable functional unit, Profiling, Temporal partitioning, Custom instruction, Extensible processor, Similarity detection
23	Jih-Woei Huang, Chih-Ping Chu	A flexible processor mapping technique toward data localization for block-cyclic data redistribution.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	MPI, Data distribution, HPF, Distributed memory multicomputers, Data-parallel programming, Processor mapping
23	Carsten Albrecht, Philipp Roß, Roman Koch, Thilo Pionteck, Erik Maehle	Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform.	PDP	2008	DBLP DOI BibTeX RDF	Network Co-processor, SoC Interconnect, Run-Time Reconfiguration
23	Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee	A hybrid software-based self-testing methodology for embedded processor.	SAC	2008	DBLP DOI BibTeX RDF	embedded processor testing, fault coverage, functional testing, software-based self-test
23	Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Petrini	Exact multi-pattern string matching on the cell/b.e. processor.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	matching, string, cell processor
23	Yeim-Kuan Chang, Ming-Li Tsai, Yu-Ru Chung	Multi-Character Processor Array for Pattern Matching in Network Intrusion Detection System.	AINA	2008	DBLP DOI BibTeX RDF	intrusion detection, pattern matching, processor array, Snort
23	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.	DAC	2008	DBLP DOI BibTeX RDF	dynamic resizing, performance, embedded processor, register file
23	Donghyun Kim, Kwanho Kim, Joo-Young Kim 0001, Seungjin Lee 0001, Hoi-Jun Yoo	Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor.	DAC	2008	DBLP DOI BibTeX RDF	object recognition, network-on-chip, multi-processor SoC
23	Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Liang-Gee Chen	iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.	DAC	2008	DBLP DOI BibTeX RDF	vision processor, VLSI, video analysis, SIMD, intelligent sensor
23	Xian-He Sun, Surendra Byna, Yong Chen 0001	Server-Based Data Push Architecture for Multi-Processor Environments.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	modeling, evaluation, performance measurement, cache memory, simulation of multiple-processor system
23	G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas	Aegis: A Single-Chip Secure Processor.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	Aegis, FPGA, architecture, secure processor, single chip
23	Jing Fu 0003, Olof Hagsand, Gunnar Karlsson	Queuing Behavior and Packet Delays in Network Processor Systems.	MASCOTS	2007	DBLP DOI BibTeX RDF	queueing behavior, network processor, router
23	ZhiLei Chai, Wenke Zhao, Wenbo Xu 0001	Real-time Java processor optimized for RTSJ.	SAC	2007	DBLP DOI BibTeX RDF	Real-time Java platform, Real-time Java processor, Java Virtual Machine (JVM), Real-time specification for Java (RTSJ), Worst Case Execution Time (WCET)
23	Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho	Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture.	ARC	2007	DBLP DOI BibTeX RDF	adaptive pipeline, processor, Asynchronous design
23	Vivienne Sze, Anantha P. Chandrakasan	A 0.4-V UWB baseband processor.	ISLPED	2007	DBLP DOI BibTeX RDF	baseband processor, parallelism, ultra-wideband, ultra-low voltage
23	Ying Zhang 0032, Tao Tang 0001, Gen Li 0002, Xuejun Yang	Implementation and Optimization of Dense LU Decomposition on the Stream Processor.	PPAM	2007	DBLP DOI BibTeX RDF	producer-consumer locality, stream, scientific computing, kernels, stream processor, LU decomposition
23	Ying Zhang 0032, Gen Li 0002, Xuejun Yang	Implementing and Optimizing a Data-Intensive Hydrodynamics Application on the Stream Processor.	ICCSA (3)	2007	DBLP DOI BibTeX RDF	data-intensive scientific computing, kernel join, loop-carried stream reusing, stream transpose, stream processor
23	Xin Li 0020, Reinhard von Hanxleden	A concurrent reactive Esterel processor based on multi-threading.	SAC	2006	DBLP DOI BibTeX RDF	multithreading, processor architecture, synchronous languages, esterel
23	Sanket Shah, Tularam M. Bansod, Amit Singh	Design and Implementation of a Network Processor Based 10Gbps Network Traffic Generator.	ICDCN	2006	DBLP DOI BibTeX RDF	Network Processor, System Testing, High Throughput, Traffic Generator
23	Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami	REDEFIS: a system with a redefinable instruction set processor.	SBCCI	2006	DBLP DOI BibTeX RDF	ISA customization, dynamically reconfigurable processor, low power, SoC, high performance
23	Raj Varada, Mysore Sriram, Kris Chou, James Guzzo	Design and integration methods for a multi-threaded dual core 65nm Xeon® processor.	ICCAD	2006	DBLP DOI BibTeX RDF	Xeon®, Integration, Design Methods, processor
23	Seiji Maeda, Shigehiro Asano, Tomofumi Shimada, Koichi Awazu, Haruyuki Tago	A Real-Time Software Platform for the Cell Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	real-time resource scheduler, Scalability, Consumer electronics, Cell processor
23	Jan-Willem van de Waerdt, Gerrit A. Slavenburg, Jean-Paul van Itegem, Stamatis Vassiliadis	Motion estimation performance of the TM3270 processor.	SAC	2005	DBLP DOI BibTeX RDF	motion estimation, software implementation, media processor
23	BoonPing Lim, Md. Safi Uddin	Statistical-Based SYN-Flooding Detection Using Programmable Network Processor.	ICITA (2)	2005	DBLP DOI BibTeX RDF	non-parametric CUSUM, token bucket filtering, network security, network processor, SYN-flooding
23	Xianghui Hu, Bei Hua, Xinan Tang	TrieC: A High-Speed IPv6 Lookup with Fast Updates Using Network Processor.	ICESS	2005	DBLP DOI BibTeX RDF	IPv6 lookup, prefix expansion, routing, parallel programming, Network processor, embedded system design
23	Thomas Bonald, Alexandre Proutière	On Stochastic Bounds for Monotonic Processor Sharing Networks.	Queueing Syst. Theory Appl.	2004	DBLP DOI BibTeX RDF	processor sharing networks, stochastic bounds, monotonicity, balance, insensitivity
23	Rashindra Manniesing, Richard P. Kleihorst, André van der Avoird, Emile A. Hendriks	Power Analysis of a General Convolution Algorithm Mapped on a Linear Processor Array.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	parallel processing, VLSI design, power estimation, linear processor array
23	Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang	Application-specific instruction generation for configurable processor architectures.	FPGA	2004	DBLP DOI BibTeX RDF	binate covering, compilation, ASIP, technology mapping, configurable processor
23	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	Understanding the effects of wrong-path memory references on processor performance.	WMPI	2004	DBLP DOI BibTeX RDF	processor performance analysis, wrong path modeling, wrong-path memory references, speculative execution, data prefetching, execution-driven simulation, cache pollution
23	Toshiyuki Ito, Kentaro Ono, Mayumi Ichikawa, Yuichi Okuyama, Kenichi Kuroda	Reconfigurable Instruction-Level Parallel Processor Architecture.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF	ILP Processor, PCA, dynamical reconfigurability, VLIW, self-reconfigurability
23	Chih-Jen Yen, Mely Chen Chi, Wen-Yaw Chung, Shing-Hao Lee	A 0.75-mW analog processor IC for wireless biosignal monitor.	ISLPED	2003	DBLP DOI BibTeX RDF	analog processor, biosignal monitor, wireless, IC
23	Byung S. Yoo, Chita R. Das	A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Allocation overhead, complete submesh recognition ability, stack-based allocation algorithm, processor allocation, mesh-connected multicomputers
23	Piia Simonen, Ilkka Saastamoinen, Mika Kuulusa, Jari Nurmi	Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor.	DELTA	2002	DBLP DOI BibTeX RDF	instruction memory, memory compression, ISA, DSP processor
23	Jiyang Kang, Jongbok Lee, Wonyong Sung	A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	code converter, compiler-friendly, performance evaluation, digital signal processor, architecture synthesis
23	Itsuo Takanami	Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement.	DFT	2001	DBLP DOI BibTeX RDF	built-in selft-reconfiguration, digital neural circuit, direct spare replacement, fault-tolerance, mesh-connected processor array
23	Keqin Li 0001, Yi Pan 0001	Probabilistic Analysis of Scheduling Precedence Constrained Parallel Tasks on Multicomputers with Contiguous Processor Allocation.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Average-case performance ratio, binary system partitioning, contiguous processor allocation, largest-task-first, task scheduling, probabilistic analysis, precedence constraint, parallel task
23	Vera P. Behar, Christo A. Kabakchiev, Lyubka Doukovska	Adaptive CFAR PI Processor for Radar Target Detection in Pulse Jamming.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	CFAR API processor, detection in pulse jamming, target detection performance calculation, parallel algorithms, systolic architecture
23	Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas	Verification of configurable processor cores.	DAC	2000	DBLP DOI BibTeX RDF	configurable processor cores, system-on-chip, test generation, design verification, co-simulation, coverage analysis
23	Virginia Mary Lo, Kurt J. Windisch, Wanqian Liu, Bill Nitzberg	Noncontiguous Processor Allocation Algorithms for Mesh-Connected Multicomputers.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	noncontiguous, scheduling, Resource management, mesh, fragmentation, processor allocation
23	Kumar N. Ganapathy, Benjamin W. Wah, Chien-Wei Li	Designing a Scalable Processor Array for Recurrent Computations.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Access unit, affine dependencies, area index, clock-rate reduction, multimesh graph, uniform dependencies, scheduling, partitioning, memory bandwidth, processor array, dependence graph
23	Dileep Bhandarkar, Jianxun Jason Ding	Performance Characterization of the Pentium(r) Pro Processor.	HPCA	1997	DBLP DOI BibTeX RDF	Pentium® Pro processor, SPEC CPU95, SYSmark/NT, performance evaluation, computer architecture, workload characterization, speculative execution, out of order execution
23	Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya	A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor.	CODES	1997	DBLP DOI BibTeX RDF	hardware/software co-operation, a computer architecture using FPGA, bus-based reconfigurable co-processor architecture, high-level synthesis and optimization, C compiler to hardware modules
23	Georg Färber, Franz Fischer, Thomas Kolloch, Annette Muth	Improving processor utilization with a task classification model based application specific hard real-time architecture.	RTCSA	1997	DBLP DOI BibTeX RDF	task classification model, application specific hard real-time architecture, real-time architecture, target architecture framework, tightly coupled heterogeneous multiprocessor system, rapid prototyping platform, caches, pipelines, microprocessors, templates, schedulability analysis, execution times, software prototyping, hard real time systems, processor utilization
23	Adam Postula, David Abramson 0001, Paul Logothetis	The Design of a Specialised Processor for the Simulation of Sintering A. Postula.	EUROMICRO	1996	DBLP DOI BibTeX RDF	specialised processor, sintering simulation, metallurgical sintering, commercially available gate array technology, Xilinx FPGA, Aptix FPIC switch technology, FPGAs, Monte-Carlo simulation, special purpose computers
23	Joseph A. Fernando, Jack S. N. Jean	Interfacing FPGA/VLSI Processor Arrays.	ASAP	1995	DBLP DOI BibTeX RDF	VLSI Processor Array, FPGA Board, Array Compiler, Algorithm Mapping
23	Michael J. Schulte, Earl E. Swartzlander Jr.	A Processor for Staggered Interval Arithmetic.	ASAP	1995	DBLP DOI BibTeX RDF	computer arithmetic, hardware, processor, Interval arithmetic, precision, application specific, numerical computations
23	Giuseppe Ascia, Giuseppe Ficili, Daniela Panno	Design of a VLSI fuzzy processor for ATM traffic sources management.	LCN	1995	DBLP DOI BibTeX RDF	VLSI fuzzy processor, ATM traffic sources management, traffic arrival, policing mechanism, fuzzy logic, Fuzzy Logic, asynchronous transfer mode, ATM networks, inference mechanisms, traffic control, fuzzy inferences, telecommunication congestion control, bottleneck, policing
23	Prathima Agrawal, Antony Ng	Computing Network Flow on a Multiple Processor Pipeline.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	multiple processor pipeline, Goldberg-Tarjan algorithm, network graph, six processors, distributed algorithms, graph theory, network flow, pipeline processing, parallel implementations, performance estimates, maximum flow, partitioned algorithm, message-passing multicomputer
23	Chris J. Scheiman, Peter R. Cappello	A Period-Processor-Time-Minimal Schedule for Cubical Mesh Algorithms.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	period-processor-time-minimal schedule, cubical mesh algorithms, precedence-constrained multiprocessor schedules, toroidally connected mesh, scheduling, parallel algorithms, computational complexity, multiprocessor interconnection networks, directed graphs, systolic arrays, systolic array, directed acyclic graph, matrix algebra, matrix product, computationalcomplexity
23	Jens Braband	Waiting Time Distributions for Processor Sharing Queues with State-Dependent Arrival and Service Rates.	Computer Performance Evaluation	1994	DBLP DOI BibTeX RDF	multiple server queues, Processor sharing, waiting time distributions
23	Yinong Chen, Winfried Bücken, Klaus Echtle	Efficient Algorithms for System Diagnosis with Both Processor and Comparator Faults.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	processor faults, comparison-based self-diagnosis, multiprocessorsystems, comparator faults, O(mod E mod)/sup 2/ algorithm, computational complexity, fault tolerant computing, multiprocessing systems, system diagnosis
23	Chien-Min Wang, Sheng-De Wang	Efficient Processor Assignment Algorithms and Loop Transformations for Executing Nested Parallel Loops on Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	processor assignment algorithms, nested parallel loops, performance, parallel algorithms, parallel programming, multiprocessors, program compilers, loop transformations, parallel processors, parallel execution
23	Biing-Feng Wang, Gen-Huey Chen	Constant Time Algorithms for the Transitive Closure and Some Related Graph Problems on Processor Arrays with Reconfigurable Bus Systems.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	related graph problems, reconfigurable bus systems, parallel algorithms, graph theory, minimum spanning trees, bipartite graphs, transitive closure, transitive closure, connected components, processor arrays, undirected graph, bridges, biconnected components, graph problems, articulation points
23	Robert F. Cmelik, Narain H. Gehani, William D. Roome	Experience with Multiple Processor Versions of Concurrent C.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	multiple processor versions, uniprocessor version, parallel programming, parallel programming, local area network, local area networks, multiprocessing systems, shared-memory multiprocessor, execution times, C language, Concurrent C, multiprocessing programs