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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2555 occurrences of 1182 keywords
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Results
Found 2526 publication records. Showing 2526 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Joan L. Mitchell, Arianne T. Hinds |
Enhanced Parallel Processing in Wide Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley |
Improving Program Efficiency by Packing Instructions into Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 260-271, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Josef Makolm |
Registers as Part of Back Office Integration: The Austrian Experience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EGOV ![In: Electronic Government: Third International Conference, EGOV 2004, Zaragoza, Spain, August 30 - September 3, 2004, Proceedings, pp. 521-524, 2004, Springer, 3-540-22916-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Andreas Larsson, Anders Gidenstam, Phuong Hoai Ha, Marina Papatriantafilou, Philippas Tsigas |
Multi-word Atomic Read/Write Registers on Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Algorithms - ESA 2004, 12th Annual European Symposium, Bergen, Norway, September 14-17, 2004, Proceedings, pp. 736-748, 2004, Springer, 3-540-23025-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus |
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(5), pp. 501-510, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
cross-parity check, on-line BIST, multiple soft-error detection, self-repair |
22 | Ali Kanso |
Clock-Controlled Shrinking Generator of Feedback Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACISP ![In: Information Security and Privacy, 8th Australasian Conference, ACISP 2003, Wollongong, Australia, July 9-11, 2003, Proceedings, pp. 443-451, 2003, Springer, 3-540-40515-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Chien-In Henry Chen, Kiran George |
Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 521-524, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Chien-In Henry Chen, Kiran George |
Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 111-116, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Carole Delporte-Gallet, Hugues Fauconnier, Rachid Guerraoui |
Failure Detection Lower Bounds on Registers and Consensus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 16th International Conference, DISC 2002, Toulouse, France, October 28-30, 2002 Proceedings, pp. 237-251, 2002, Springer, 3-540-00073-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Markus Feldbach, Klaus D. Tönnies |
Segmentation of the Date in Entries of Historical Church Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAGM-Symposium ![In: Pattern Recognition, 24th DAGM Symposium, Zurich, Switzerland, September 16-18, 2002, Proceedings, pp. 403-410, 2002, Springer, 3-540-44209-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Handwriting recognition, document image processing, word segmentation |
22 | Gautam Doshi, Rakesh Krishnaiyer, Kalyan Muthukumar |
Optimizing Software Data Prefetches with Rotating Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 257-267, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Alexander Kholosha |
Clock-Controlled Shift Registers and Generalized Geffe Key-Stream Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDOCRYPT ![In: Progress in Cryptology - INDOCRYPT 2001, Second International Conference on Cryptology in India, Chennai, India, December 16-20, 2001, Proceedings, pp. 287-296, 2001, Springer, 3-540-43010-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
key-stream generator, clock-controlled shift register, Geffe generator, cryptography |
22 | Sandeepan Chowdhury, Subhamoy Maitra |
Efficient Software Implementation of Linear Feedback Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDOCRYPT ![In: Progress in Cryptology - INDOCRYPT 2001, Second International Conference on Cryptology in India, Chennai, India, December 16-20, 2001, Proceedings, pp. 297-307, 2001, Springer, 3-540-43010-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Block Oriented LFSR, Connection Polynomials, Stream Cipher |
22 | Wei-Kai Cheng, Youn-Long Lin |
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 4(3), pp. 231-256, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
code generation, DSP |
22 | Ting-Lu Huang |
Fast Mutual Exclusion Algorithms Using Read-Modify-Write and Atomic Read/Write Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: International Conference on Parallel and Distributed Systems, ICPADS '98, Tainan, Taiwan, December 14-16, 1998, pp. 292-299, 1998, IEEE Computer Society, 0-8186-8603-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Vladimír R. Buzek, Mark Hillery |
Universal Optimal Cloning of Qubits and Quantum Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QCQC ![In: Quantum Computing and Quantum Communications, First NASA International Conference, QCQC'98, Palm Springs, California, USA, February 17-20, 1998, Selected Papers, pp. 235-246, 1998, Springer, 3-540-65514-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
quantum cloning, quantum logic networks, inseparability |
22 | Dusan Suvakovic, C. André T. Salama |
Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 26-29, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power, DSP, energy consumption, switching, multiplexer, low voltage, register, datapath |
22 | Luis Villa, Roger Espasa, Mateo Valero |
Effective Usage of Vector Registers in Advanced Vector Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 250-260, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Willi Geiselmann, Dieter Gollmann |
Correlation Attacks on Cascades of Clock Controlled Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIACRYPT ![In: Advances in Cryptology - ASIACRYPT '96, International Conference on the Theory and Applications of Cryptology and Information Security, Kyongju, Korea, November 3-7, 1996, Proceedings, pp. 346-359, 1996, Springer, 3-540-61872-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
22 | Jovan Dj. Golic |
Towards Fast Correlation Attacks on Irregularly Clocked Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '95, International Conference on the Theory and Application of Cryptographic Techniques, Saint-Malo, France, May 21-25, 1995, Proceeding, pp. 248-262, 1995, Springer, 3-540-59409-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Michiko Inoue, Wei Chen 0003 |
Linear-Time Snapshot Using Multi-writer Multi-reader Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WDAG ![In: Distributed Algorithms, 8th International Workshop, WDAG '94, Terschelling, The Netherlands, September 29 - October 1, 1994, Proceedings, pp. 130-140, 1994, Springer, 3-540-58449-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
atomic snapshot, lattice agreement problem, shared memory system, linearizability, wait-free algorithm |
22 | Jovan Dj. Golic, Luke O'Connor |
Embedding and Probabilistic Correlation Attacks on Clock-Controlled Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '94, Workshop on the Theory and Application of Cryptographic Techniques, Perugia, Italy, May 9-12, 1994, Proceedings, pp. 230-243, 1994, Springer, 3-540-60176-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Thyagaraju R. Damarla, Avinash Sathaye |
Applications of one-dimensional cellular automata and linear feedback shift registers for pseudo-exhaustive testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10), pp. 1580-1591, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Kazuhiko Iwasaki, Fumio Arakawa |
An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4), pp. 427-438, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Martin Rudolph |
Feedback-testing by using multiple input signature registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(3), pp. 213-219, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Bult-in self-test, design for testability, test-pattern generation, testability analysis, MISR |
22 | Yves Roggeman |
Varying Feedback Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '89, Workshop on the Theory and Application of of Cryptographic Techniques, Houthalen, Belgium, April 10-13, 1989, Proceedings, pp. 670-679, 1989, Springer, 3-540-53433-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Paul A. Karger |
Using Registers to Optimize Cross-Domain Call Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 194-204, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
RISC |
21 | Richard Hughey, Andrea Di Blas |
Finding the Next Computational Model: Experience with the UCSC Kestrel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 171-186, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
biological sequence comparison, VLSI system design, application-specific array processor, parallel processing, parallel programming, computer architecture, systolic array, SIMD, sequence analysis, shared registers |
21 | Craig A. Burton |
A thin client for networked access to a central register and electronic voting terminal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEGOV ![In: Proceedings of the 2nd International Conference on Theory and Practice of Electronic Governance, ICEGOV 2008, Cairo, Egypt, December 1-4, 2008, pp. 281-286, 2008, ACM, 978-1-60558-386-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multi-channel voting, multi-modal voting, systems pilots, voter registers, voter rolls, electronic voting, elections, internet voting |
21 | Andrew Klapper |
The Asymptotic Behavior of pi-Adic Complexity with pi2 = - 2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSC ![In: Sequences, Subsequences, and Consequences, International Workshop, SSC 2007, Los Angeles, CA, USA, May 31 - June 2, 2007, Revised Invited Papers, pp. 134-146, 2007, Springer, 978-3-540-77403-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
N-adic complexity, Stream ciphers, Sequences, shift registers |
21 | Anthony A. Philippakis, Aaron M. Qureshi, Michael F. Berger, Martha L. Bulyk |
Design of Compact, Universal DNA Microarrays for Protein Binding Microarray Experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RECOMB ![In: Research in Computational Molecular Biology, 11th Annual International Conference, RECOMB 2007, Oakland, CA, USA, April 21-25, 2007, Proceedings, pp. 430-443, 2007, Springer, 3-540-71680-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
de Bruijn sequences, protein binding microarrays, linear feedback shift registers, motif, transcription factor |
21 | Sanjay Burman, Debdeep Mukhopadhyay, Kamakoti Veezhinathan |
LFSR Based Stream Ciphers Are Vulnerable to Power Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDOCRYPT ![In: Progress in Cryptology - INDOCRYPT 2007, 8th International Conference on Cryptology in India, Chennai, India, December 9-13, 2007, Proceedings, pp. 384-392, 2007, Springer, 978-3-540-77025-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Linear Feed Back Shift Registers, Dynamic Power Dissipation, Side Channel Attacks, Power Analysis, Hamming Distance |
21 | Bin Zhang 0003, Dengguo Feng |
Security analysis of a new stream cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 49(3), pp. 286-301, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
divide-and-conquer attack, non-linear feedback shift registers (NLFSR), stream cipher, chaotic sequence |
21 | Guilin Chen, Mahmut T. Kandemir, Mary Jane Irwin, J. Ramanujam |
Reducing code size through address register assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(1), pp. 225-258, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Software compilation, address registers, DSP, register assignment |
21 | Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers |
Offset assignment using simultaneous variable coalescing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(4), pp. 864-883, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation |
21 | Hong Xu 0008, Wen-Feng Qi 0001 |
On the Distinctness of Decimations of Generalized l-Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2006, 4th International Conference, Beijing, China, September 24-28, 2006, Proceedings, pp. 313-322, 2006, Springer, 3-540-44523-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Feedback-with-carry shift registers (FCSRs), l-sequences, generalized l-sequences, integer residue ring, primitive sequences, 2-adic numbers |
21 | Konstantinos Limniotis, Nicholas Kolokotronis, Nicholas Kalouptsidis |
Nonlinear Complexity of Binary Sequences and Connections with Lempel-Ziv Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2006, 4th International Conference, Beijing, China, September 24-28, 2006, Proceedings, pp. 168-179, 2006, Springer, 3-540-44523-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Lempel-Ziv compression, nonlinear complexity, Cryptography, sequences, nonlinear feedback shift registers |
21 | Nicholas Kolokotronis, Konstantinos Limniotis, Nicholas Kalouptsidis |
Lower Bounds on Sequence Complexity Via Generalised Vandermonde Determinants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2006, 4th International Conference, Beijing, China, September 24-28, 2006, Proceedings, pp. 271-284, 2006, Springer, 3-540-44523-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
filter functions, linear feedbak shift registers, Vandermonde determinants, linear complexity, Binary sequences, symmetric functions |
21 | Dimitri Kagaris |
Phase Shifter Merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(2), pp. 161-168, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Built-in Self-Test (BIST), cellular automata, linear feedback shift registers, Test Pattern Generation (TPG), phase shifters |
21 | Maneli Noorkami, Faramarz Fekri |
A Fast Correlation Attack via Unequal Error Correcting LDPC Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2004, The Cryptographers' Track at the RSA Conference 2004, San Francisco, CA, USA, February 23-27, 2004, Proceedings, pp. 54-66, 2004, Springer, 3-540-20996-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cryptanalysis, Stream ciphers, linear feedback shift registers, fast correlation attacks, LDPC codes |
21 | Håvard Molland, Tor Helleseth |
An Improved Correlation Attack Against Irregular Clocked and Filtered Keystream Generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO 2004, 24th Annual International CryptologyConference, Santa Barbara, California, USA, August 15-19, 2004, Proceedings, pp. 373-389, 2004, Springer, 3-540-22668-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Irregular clocked shift registers, Boolean functions, Stream cipher, Correlation attack |
21 | Dimitri Kagaris |
Multiple-Seed TPG Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(12), pp. 1633-1639, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Built-In Self-Test (BIST), Linear Feedback Shift Registers (LFSRs), Test Pattern Generation (TPG) |
21 | Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos |
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(3), pp. 315-332, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
test-per-clock schemes, accumulator-based test pattern generators, built-in self-test, linear feedback shift registers, reseeding |
21 | Paul Camion, Miodrag J. Mihaljevic, Hideki Imai |
Two Alerts for Design of Certain Stream Ciphers: Trapped LFSR and Weak Resilient Function over GF(q). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Selected Areas in Cryptography ![In: Selected Areas in Cryptography, 9th Annual International Workshop, SAC 2002, St. John's, Newfoundland, Canada, August 15-16, 2002. Revised Papers, pp. 196-213, 2002, Springer, 3-540-00622-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
linear feedback shift registers over GF(), nonlinear combination generator, cryptanalysis, resilient functions, keystream generators |
21 | Philippe Chose, Antoine Joux, Michel Mitton |
Fast Correlation Attacks: An Algorithmic Point of View. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT 2002, International Conference on the Theory and Applications of Cryptographic Techniques, Amsterdam, The Netherlands, April 28 - May 2, 2002, Proceedings, pp. 209-221, 2002, Springer, 3-540-43553-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
match-and-sort, algorithmics, cryptanalysis, Stream ciphers, linear feedback shift registers, fast correlation attacks, parity-checks |
21 | Palash Sarkar 0001 |
The Filter-Combiner Model for Memoryless Synchronous Stream Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO 2002, 22nd Annual International Cryptology Conference, Santa Barbara, California, USA, August 18-22, 2002, Proceedings, pp. 533-548, 2002, Springer, 3-540-44050-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
synchronous stream ciphers, nonlinear filter model, nonlinear combiner model, filter-combiner model, cellular automata, linear feedback shift registers |
21 | Miodrag J. Mihaljevic, Marc P. C. Fossorier, Hideki Imai |
Fast Correlation Attack Algorithm with List Decoding and an Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSE ![In: Fast Software Encryption, 8th International Workshop, FSE 2001 Yokohama, Japan, April 2-4, 2001, Revised Papers, pp. 196-210, 2001, Springer, 3-540-43869-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
nonlinear combiner, cryptanalysis, Stream ciphers, linear feedback shift registers, nonlinear filter, keystream generators |
21 | Palash Sarkar 0001, Subhamoy Maitra |
Efficient Implementation of "Large" Stream Cipher Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings, pp. 319-332, 2001, Springer, 3-540-42521-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Boolean functions, Stream Ciphers, Cellular Automata, Linear Feedback Shift Registers, Reconfigurable Hardware, Pipelined Architecture |
21 | Gianni Conte, Stefano Tommesani, Francesco Zanichelli |
The Long And Winding Road to High-Performance Image Processing with MMX/SSE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 302-310, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SIMD on registers, high-performance image processing, image processing, image processing, instruction sets, real-time image processing, multimedia processing |
21 | Miodrag J. Mihaljevic, Marc P. C. Fossorier, Hideki Imai |
A Low-Complexity and High-Performance Algorithm for the Fast Correlation Attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSE ![In: Fast Software Encryption, 7th International Workshop, FSE 2000, New York, NY, USA, April 10-12, 2000, Proceedings, pp. 196-212, 2000, Springer, 3-540-41728-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
stream ciphers, decoding, linear feedback shift registers, fast correlation attack, keystream generators |
21 | Ondrej Novák |
Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-3, Third European Dependable Computing Conference, Prague, Czech Republic, September 15-17, 1999, Proceedings, pp. 303-320, 1999, Springer, 3-540-66483-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
linear cyclic codes, hardware test pattern generators, weighted random testing, Cellular automata, BIST, linear feedback shift registers, pseudoexhaustive testing |
21 | Alessandro Panconesi, Marina Papatriantafilou, Philippas Tsigas, Paul M. B. Vitányi |
Randomized Naming Using Wait-Free Shared Variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 11(3), pp. 113-124, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Naming problem, Unique process ID, Asynchronous distributed protocols, Wait-free read/write registers, Test-and-set objects, Fault-tolerance, Randomized algorithms, Shared memory, Atomicity, Symmetry breaking, Adaptive adversary |
21 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu |
A comprehensive estimation technique for high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 122-127, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area |
21 | Eun-Hee Hyun, Sung-Hee Kim |
Real-time mobile data management using a minimal MMDB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 2nd International Workshop on Real-Time Computing Systems and Applications, October 25 - 27, 1995, Tokyo, Japan, pp. 125-, 1995, IEEE Computer Society, 0-8186-7106-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
real-time mobile data management, minimal MMDB, main memory database system, mobile computational viewpoint, location registers, fast access methods, digital cellular system, real-time systems, middleware, database management systems, relational data model, client/server architecture, design considerations |
21 | Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa |
A superscalar RISC processor with pseudo vector processing feature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 102-109, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
superscalar RISC processor, pseudo vector processing, architectural extension, floating-point registers, scoreboard-based dependency check, pipeline stage optimization, 267 MFLOPS, 1.2 Gbyte/s, performance evaluation, performance, computer architecture, memory access, reduced instruction set computing, vector processor systems |
21 | Marc Tremblay, Bill Joy 0001, Ken Shin |
A three dimensional register file for superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 191-201, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows |
21 | Siamak Arya, Howard Sachs, Sreeram Duvvuru |
An architecture for high instruction level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 153-162, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution |
21 | Nadime Zacharia, Janusz Rajski, Jerzy Tyszer |
Decompression of test data using variable-length seed LFSRs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 426-433, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
test data decompression, variable-length seed LFSRs, deterministic test vectors, scan circuits, multiple polynomial LFSR, encoding efficiency, logic testing, built-in self test, integrated circuit testing, encoding, automatic testing, polynomials, linear feedback shift register, shift registers, modular design, digital integrated circuits |
21 | Kwang-Ting Cheng |
Partial scan designs without using a separate scan clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 277-282, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock |
21 | Andrew Klapper, Mark Goresky |
Cryptanalysis Based on 2-Adic Rational Approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO '95, 15th Annual International Cryptology Conference, Santa Barbara, California, USA, August 27-31, 1995, Proceedings, pp. 262-273, 1995, Springer, 3-540-60221-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cryptanalysis, Binary sequences, rational approximation, feedback with carry shift registers, 2-adic numbers |
21 | Chunming Qiao, Rami G. Melhem |
Reconfiguration with Time Division Multiplexed MIN's for Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(4), pp. 337-352, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
MIN's, multiprocessor communications, TDM-MIN's, N time slots, n-dimensional hypercubes, Markov analysis, partition of connection requests, partitioning, mappings, reconfiguration, multiprocessor interconnection networks, embedding, meshes, NP-hard, multistage interconnection networks, optical interconnects, rings, binary trees, shift registers, time division multiplexing, time division multiplexed, round-robin, cube-connected-cycles |
21 | Miodrag J. Mihaljevic, Jovan Dj. Golic |
Convergence of a Bayesian Iterative Error-Correction Procedure on a Noisy Shift register Sequence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '92, Workshop on the Theory and Application of of Cryptographic Techniques, Balatonfüred, Hungary, May 24-28, 1992, Proceedings, pp. 124-137, 1992, Springer, 3-540-56413-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Algorithms, Cryptanalysis, Convergence, Decoding, Shift registers, Fast correlation attack |
21 | Hussein M. Alnuweiri, Viktor K. Prasanna |
Fast Image Labeling Using Local Operators on Mesh-Connected Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 13(2), pp. 202-207, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
bit-serial processors, local operators, asymptotic time complexity, very fast shift registers, parallel algorithm, parallel algorithms, computational complexity, computational complexity, parallel architectures, parallel architectures, computerised picture processing, computerised picture processing, stacks, communication links, mesh-connected computers, image labeling |
21 | Vicki H. Allan, Robert A. Mueller |
Compaction with General Timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 14(5), pp. 595-599, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
general synchronous timing, microcode generation systems, branch delays, volatile registers, microoperations, multiple microinstructions, clocked microarchitectures, compilers, synchronisation, program compilers, microprogramming, target architecture, data-dependency graphs |
19 | Weifeng Xu, Russell Tessier |
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(3), pp. 11:1-11:40, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure |
19 | Minwook Ahn, Yunheung Paek |
Register coalescing techniques for heterogeneous register architecture with copy sifting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(2), pp. 16:1-16:37, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
heterogeneous register architecture, compiler, Register allocation, embedded processors, register coalescing |
19 | Guang Zeng, Yang Yang, Wenbao Han, Shuqin Fan |
Word Oriented Cascade Jump sigma-LFSR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAECC ![In: Applied Algebra, Algebraic Algorithms and Error-Correcting Codes, 18th International Symposium, AAECC-18 2009, Tarragona, Catalonia, Spain, June 8-12, 2009. Proceedings, pp. 127-136, 2009, Springer, 978-3-642-02180-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Cascade Jump LFSR, ??LFSR, Fast Software Encryption, Stream Cipher, Linear Feedback Shift Register(LFSR) |
19 | Praveen Raghavan, Francky Catthoor |
SARA: StreAm register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 41-50, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
stream register, low power, register allocation, spatial locality |
19 | Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu |
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 174-181, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
Improving testability and soft-error resilience through retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 508-513, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
testability, soft errors, retiming |
19 | Suhyun Kim, Soo-Mook Moon |
Rotating register allocation with multiple rotating branches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 235-244, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
rotating register, register allocation, software pipelining |
19 | Yehuda Afek, Iftah Gamzu, Irit Levy, Michael Merritt, Gadi Taubenfeld |
Group Renaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 12th International Conference, OPODIS 2008, Luxor, Egypt, December 15-18, 2008. Proceedings, pp. 58-72, 2008, Springer, 978-3-540-92220-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Xuan Guan, Yunsi Fei |
Reducing power consumption of embedded processors through register file partitioning and compiler support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 269-274, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Viswanathan Subramanian, Arun K. Somani |
Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan, pp. 9-16, 2008, IEEE Computer Society, 978-0-7695-3448-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Haluk Rahmi Topcuoglu, Betül Demiröz, Mahmut T. Kandemir |
Solving the Register Allocation Problem for Embedded Systems Using a Hybrid Evolutionary Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 11(5), pp. 620-634, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Minwook Ahn, Jooyeon Lee, Yunheung Paek |
Optimistic coalescing for heterogeneous register architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 93-102, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
heterogeneous register architecture, register coalesing, compiler, register allocation, embedded processors |
19 | Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001 |
Early Register Release for Out-of-Order Processors with RegisterWindows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 225-234, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Dirk Stegemann |
Extended BDD-Based Cryptanalysis of Keystream Generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Selected Areas in Cryptography ![In: Selected Areas in Cryptography, 14th International Workshop, SAC 2007, Ottawa, Canada, August 16-17, 2007, Revised Selected Papers, pp. 17-35, 2007, Springer, 978-3-540-77359-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
F-FCSR, cryptanalysis, Stream cipher, BDD, Trivium, Grain |
19 | JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally |
Register pointer architecture for efficient embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 600-605, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Xingwu Liu, Zhiwei Xu 0002, Juhua Pu |
Revisiting the Impossibility for Boosting Service Resilience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TAMC ![In: Theory and Applications of Models of Computation, 4th International Conference, TAMC 2007, Shanghai, China, May 22-25, 2007, Proceedings, pp. 715-727, 2007, Springer, 978-3-540-72503-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Neng-Fa Zhou |
A Register-Free Abstract Prolog Machine with Jumbo Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICLP ![In: Logic Programming, 23rd International Conference, ICLP 2007, Porto, Portugal, September 8-13, 2007, Proceedings, pp. 455-457, 2007, Springer, 978-3-540-74608-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Faith Ellen, Panagiota Fatourou, Eric Ruppert |
The Space Complexity of Unbounded Timestamps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 21st International Symposium, DISC 2007, Lemesos, Cyprus, September 24-26, 2007, Proceedings, pp. 223-237, 2007, Springer, 978-3-540-75141-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
lower bounds, anonymous, shared memory, timestamps |
19 | Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
A low power VLIW processor generation method by means of extracting non-redundant activation conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 227-232, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
low power, ASIP, clock gating, VLIW processor |
19 | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 172-179, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Yong Ki Lee, Ingrid Verbauwhede |
A Compact Architecture for Montgomery Elliptic Curve Scalar Multiplication Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISA ![In: Information Security Applications, 8th International Workshop, WISA 2007, Jeju Island, Korea, August 27-29, 2007, Revised Selected Papers, pp. 115-127, 2007, Springer, 978-3-540-77534-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Compact Elliptic Curve Processor, Montgomery Scalar Multiplication |
19 | Yukihide Kohira, Atsushi Takahashi 0001 |
A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1795-1798, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Mallik Kandala, Wei Zhang 0002, Laurence Tianruo Yang |
An Area-Efficient Approach to Improving Register File Reliability against Transient Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA Workshops (1) ![In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007), Workshops Proceedings, Volume 1, May 21-23, 2007, Niagara Falls, Canada, pp. 798-803, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | James Aspnes, Faith Ellen Fich, Eric Ruppert |
Relationships between broadcast and shared memory in reliable anonymous distributed systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 18(3), pp. 209-219, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Simulations, Robustness, Broadcast, Anonymous, Shared memory |
19 | Cheng-Yi Xiong, Jin-Wen Tian, Jian Liu 0011 |
A note on "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet Transform". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 54(5), pp. 1910-1916, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Jiachun Wu, Hao Zhang, Jianxin Liao, Xiaomin Zhu 0002, Bo Yang |
Modeling and Analysis for an Enhanced Three-Tier Dynamic Location Management in 3G. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WASA ![In: Wireless Algorithms, Systems, and Applications, First International Conference, WASA 2006, Xi'an, China, August 15-17, 2006, Proceedings, pp. 652-663, 2006, Springer, 3-540-37189-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Bakhtiar Affendi Rosdi, Atsushi Takahashi 0001 |
Low area pipelined circuits by multi-clock cycle paths and clock scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 260-265, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Philipp Rohde |
On the µ-Calculus Augmented with Sabotage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FoSSaCS ![In: Foundations of Software Science and Computation Structures, 9th International Conference, FOSSACS 2006, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2006, Vienna, Austria, March 25-31, 2006, Proceedings, pp. 142-156, 2006, Springer, 3-540-33045-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Abhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu |
Issues and Support for Dynamic Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 351-358, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Shih-Hsu Huang, Chia-Ming Chang 0002, Yow-Tyng Nieh |
State re-encoding for peak current minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 33-38, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
peak current, sequential circuit synthesis, finite state machine |
19 | Sultan Al-Hinai, Lynn Margaret Batten, Bernard D. Colbert, Kenneth Koon-Ho Wong |
Algebraic Attacks on Clock-Controlled Stream Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACISP ![In: Information Security and Privacy, 11th Australasian Conference, ACISP 2006, Melbourne, Australia, July 3-5, 2006, Proceedings, pp. 1-16, 2006, Springer, 3-540-35458-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
irregular clocking, stream cipher, linear feedback shift register, algebraic attack, clock control |
19 | Panagiota Fatourou, Nikolaos D. Kallimanis |
Single-scanner multi-writer snapshot implementations are fast! ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Twenty-Fifth Annual ACM Symposium on Principles of Distributed Computing, PODC 2006, Denver, CO, USA, July 23-26, 2006, pp. 228-237, 2006, ACM, 1-59593-384-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
atomic objects, multi-writer, single-scanner, shared memory systems, asynchronous, wait-free, snapshot |
19 | Florent Bouchez, Alain Darte, Christophe Guillon, Fabrice Rastello |
Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006. Revised Papers, pp. 283-298, 2006, Springer, 978-3-540-72520-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Burkhard Englert |
On the Cost of Uniform Protocols Whose Memory Consumption Is Adaptive to Interval Contention. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 10th International Conference, OPODIS 2006, Bordeaux, France, December 12-15, 2006, Proceedings, pp. 64-80, 2006, Springer, 3-540-49990-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter |
Recovery Mechanisms for Dual Core Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 380-388, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Panagiota Fatourou, Faith Ellen Fich, Eric Ruppert |
Time-space tradeoffs for implementations of snapshots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 38th Annual ACM Symposium on Theory of Computing, Seattle, WA, USA, May 21-23, 2006, pp. 169-178, 2006, ACM, 1-59593-134-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
anonymous processes, distributed computing, lower bound, shared memory, wait-free, snapshot, time-space tradeoff |
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