Search results for "registers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Joan L. Mitchell, Arianne T. Hinds	Enhanced Parallel Processing in Wide Registers.	IPDPS	2005	DBLP DOI BibTeX RDF
22	Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley	Improving Program Efficiency by Packing Instructions into Registers.	ISCA	2005	DBLP DOI BibTeX RDF
22	Josef Makolm	Registers as Part of Back Office Integration: The Austrian Experience.	EGOV	2004	DBLP DOI BibTeX RDF
22	Andreas Larsson, Anders Gidenstam, Phuong Hoai Ha, Marina Papatriantafilou, Philippas Tsigas	Multi-word Atomic Read/Write Registers on Multiprocessor Systems.	ESA	2004	DBLP DOI BibTeX RDF
22	Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus	On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	cross-parity check, on-line BIST, multiple soft-error detection, self-repair
22	Ali Kanso	Clock-Controlled Shrinking Generator of Feedback Shift Registers.	ACISP	2003	DBLP DOI BibTeX RDF
22	Chien-In Henry Chen, Kiran George	Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].	ISCAS (5)	2003	DBLP DOI BibTeX RDF
22	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
22	Carole Delporte-Gallet, Hugues Fauconnier, Rachid Guerraoui	Failure Detection Lower Bounds on Registers and Consensus.	DISC	2002	DBLP DOI BibTeX RDF
22	Markus Feldbach, Klaus D. Tönnies	Segmentation of the Date in Entries of Historical Church Registers.	DAGM-Symposium	2002	DBLP DOI BibTeX RDF	Handwriting recognition, document image processing, word segmentation
22	Gautam Doshi, Rakesh Krishnaiyer, Kalyan Muthukumar	Optimizing Software Data Prefetches with Rotating Registers.	IEEE PACT	2001	DBLP DOI BibTeX RDF
22	Alexander Kholosha	Clock-Controlled Shift Registers and Generalized Geffe Key-Stream Generator.	INDOCRYPT	2001	DBLP DOI BibTeX RDF	key-stream generator, clock-controlled shift register, Geffe generator, cryptography
22	Sandeepan Chowdhury, Subhamoy Maitra	Efficient Software Implementation of Linear Feedback Shift Registers.	INDOCRYPT	2001	DBLP DOI BibTeX RDF	Block Oriented LFSR, Connection Polynomials, Stream Cipher
22	Wei-Kai Cheng, Youn-Long Lin	Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	code generation, DSP
22	Ting-Lu Huang	Fast Mutual Exclusion Algorithms Using Read-Modify-Write and Atomic Read/Write Registers.	ICPADS	1998	DBLP DOI BibTeX RDF
22	Vladimír R. Buzek, Mark Hillery	Universal Optimal Cloning of Qubits and Quantum Registers.	QCQC	1998	DBLP DOI BibTeX RDF	quantum cloning, quantum logic networks, inseparability
22	Dusan Suvakovic, C. André T. Salama	Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	low power, DSP, energy consumption, switching, multiplexer, low voltage, register, datapath
22	Luis Villa, Roger Espasa, Mateo Valero	Effective Usage of Vector Registers in Advanced Vector Architectures.	IEEE PACT	1997	DBLP DOI BibTeX RDF
22	Willi Geiselmann, Dieter Gollmann	Correlation Attacks on Cascades of Clock Controlled Shift Registers.	ASIACRYPT	1996	DBLP DOI BibTeX RDF
22	Jovan Dj. Golic	Towards Fast Correlation Attacks on Irregularly Clocked Shift Registers.	EUROCRYPT	1995	DBLP DOI BibTeX RDF
22	Michiko Inoue, Wei Chen 0003	Linear-Time Snapshot Using Multi-writer Multi-reader Registers.	WDAG	1994	DBLP DOI BibTeX RDF	atomic snapshot, lattice agreement problem, shared memory system, linearizability, wait-free algorithm
22	Jovan Dj. Golic, Luke O'Connor	Embedding and Probabilistic Correlation Attacks on Clock-Controlled Shift Registers.	EUROCRYPT	1994	DBLP DOI BibTeX RDF
22	Thyagaraju R. Damarla, Avinash Sathaye	Applications of one-dimensional cellular automata and linear feedback shift registers for pseudo-exhaustive testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
22	Kazuhiko Iwasaki, Fumio Arakawa	An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
22	Martin Rudolph	Feedback-testing by using multiple input signature registers.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	Bult-in self-test, design for testability, test-pattern generation, testability analysis, MISR
22	Yves Roggeman	Varying Feedback Shift Registers.	EUROCRYPT	1989	DBLP DOI BibTeX RDF
22	Paul A. Karger	Using Registers to Optimize Cross-Domain Call Performance.	ASPLOS	1989	DBLP DOI BibTeX RDF	RISC
21	Richard Hughey, Andrea Di Blas	Finding the Next Computational Model: Experience with the UCSC Kestrel.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	biological sequence comparison, VLSI system design, application-specific array processor, parallel processing, parallel programming, computer architecture, systolic array, SIMD, sequence analysis, shared registers
21	Craig A. Burton	A thin client for networked access to a central register and electronic voting terminal.	ICEGOV	2008	DBLP DOI BibTeX RDF	multi-channel voting, multi-modal voting, systems pilots, voter registers, voter rolls, electronic voting, elections, internet voting
21	Andrew Klapper	The Asymptotic Behavior of pi-Adic Complexity with pi2 = - 2.	SSC	2007	DBLP DOI BibTeX RDF	N-adic complexity, Stream ciphers, Sequences, shift registers
21	Anthony A. Philippakis, Aaron M. Qureshi, Michael F. Berger, Martha L. Bulyk	Design of Compact, Universal DNA Microarrays for Protein Binding Microarray Experiments.	RECOMB	2007	DBLP DOI BibTeX RDF	de Bruijn sequences, protein binding microarrays, linear feedback shift registers, motif, transcription factor
21	Sanjay Burman, Debdeep Mukhopadhyay, Kamakoti Veezhinathan	LFSR Based Stream Ciphers Are Vulnerable to Power Attacks.	INDOCRYPT	2007	DBLP DOI BibTeX RDF	Linear Feed Back Shift Registers, Dynamic Power Dissipation, Side Channel Attacks, Power Analysis, Hamming Distance
21	Bin Zhang 0003, Dengguo Feng	Security analysis of a new stream cipher.	Sci. China Ser. F Inf. Sci.	2006	DBLP DOI BibTeX RDF	divide-and-conquer attack, non-linear feedback shift registers (NLFSR), stream cipher, chaotic sequence
21	Guilin Chen, Mahmut T. Kandemir, Mary Jane Irwin, J. Ramanujam	Reducing code size through address register assignment.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Software compilation, address registers, DSP, register assignment
21	Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers	Offset assignment using simultaneous variable coalescing.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation
21	Hong Xu 0008, Wen-Feng Qi 0001	On the Distinctness of Decimations of Generalized l-Sequences.	SETA	2006	DBLP DOI BibTeX RDF	Feedback-with-carry shift registers (FCSRs), l-sequences, generalized l-sequences, integer residue ring, primitive sequences, 2-adic numbers
21	Konstantinos Limniotis, Nicholas Kolokotronis, Nicholas Kalouptsidis	Nonlinear Complexity of Binary Sequences and Connections with Lempel-Ziv Compression.	SETA	2006	DBLP DOI BibTeX RDF	Lempel-Ziv compression, nonlinear complexity, Cryptography, sequences, nonlinear feedback shift registers
21	Nicholas Kolokotronis, Konstantinos Limniotis, Nicholas Kalouptsidis	Lower Bounds on Sequence Complexity Via Generalised Vandermonde Determinants.	SETA	2006	DBLP DOI BibTeX RDF	filter functions, linear feedbak shift registers, Vandermonde determinants, linear complexity, Binary sequences, symmetric functions
21	Dimitri Kagaris	Phase Shifter Merging.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	Built-in Self-Test (BIST), cellular automata, linear feedback shift registers, Test Pattern Generation (TPG), phase shifters
21	Maneli Noorkami, Faramarz Fekri	A Fast Correlation Attack via Unequal Error Correcting LDPC Codes.	CT-RSA	2004	DBLP DOI BibTeX RDF	cryptanalysis, Stream ciphers, linear feedback shift registers, fast correlation attacks, LDPC codes
21	Håvard Molland, Tor Helleseth	An Improved Correlation Attack Against Irregular Clocked and Filtered Keystream Generators.	CRYPTO	2004	DBLP DOI BibTeX RDF	Irregular clocked shift registers, Boolean functions, Stream cipher, Correlation attack
21	Dimitri Kagaris	Multiple-Seed TPG Structures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Built-In Self-Test (BIST), Linear Feedback Shift Registers (LFSRs), Test Pattern Generation (TPG)
21	Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	test-per-clock schemes, accumulator-based test pattern generators, built-in self-test, linear feedback shift registers, reseeding
21	Paul Camion, Miodrag J. Mihaljevic, Hideki Imai	Two Alerts for Design of Certain Stream Ciphers: Trapped LFSR and Weak Resilient Function over GF(q).	Selected Areas in Cryptography	2002	DBLP DOI BibTeX RDF	linear feedback shift registers over GF(), nonlinear combination generator, cryptanalysis, resilient functions, keystream generators
21	Philippe Chose, Antoine Joux, Michel Mitton	Fast Correlation Attacks: An Algorithmic Point of View.	EUROCRYPT	2002	DBLP DOI BibTeX RDF	match-and-sort, algorithmics, cryptanalysis, Stream ciphers, linear feedback shift registers, fast correlation attacks, parity-checks
21	Palash Sarkar 0001	The Filter-Combiner Model for Memoryless Synchronous Stream Ciphers.	CRYPTO	2002	DBLP DOI BibTeX RDF	synchronous stream ciphers, nonlinear filter model, nonlinear combiner model, filter-combiner model, cellular automata, linear feedback shift registers
21	Miodrag J. Mihaljevic, Marc P. C. Fossorier, Hideki Imai	Fast Correlation Attack Algorithm with List Decoding and an Application.	FSE	2001	DBLP DOI BibTeX RDF	nonlinear combiner, cryptanalysis, Stream ciphers, linear feedback shift registers, nonlinear filter, keystream generators
21	Palash Sarkar 0001, Subhamoy Maitra	Efficient Implementation of "Large" Stream Cipher Systems.	CHES	2001	DBLP DOI BibTeX RDF	Boolean functions, Stream Ciphers, Cellular Automata, Linear Feedback Shift Registers, Reconfigurable Hardware, Pipelined Architecture
21	Gianni Conte, Stefano Tommesani, Francesco Zanichelli	The Long And Winding Road to High-Performance Image Processing with MMX/SSE.	CAMP	2000	DBLP DOI BibTeX RDF	SIMD on registers, high-performance image processing, image processing, image processing, instruction sets, real-time image processing, multimedia processing
21	Miodrag J. Mihaljevic, Marc P. C. Fossorier, Hideki Imai	A Low-Complexity and High-Performance Algorithm for the Fast Correlation Attack.	FSE	2000	DBLP DOI BibTeX RDF	stream ciphers, decoding, linear feedback shift registers, fast correlation attack, keystream generators
21	Ondrej Novák	Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata.	EDCC	1999	DBLP DOI BibTeX RDF	linear cyclic codes, hardware test pattern generators, weighted random testing, Cellular automata, BIST, linear feedback shift registers, pseudoexhaustive testing
21	Alessandro Panconesi, Marina Papatriantafilou, Philippas Tsigas, Paul M. B. Vitányi	Randomized Naming Using Wait-Free Shared Variables.	Distributed Comput.	1998	DBLP DOI BibTeX RDF	Naming problem, Unique process ID, Asynchronous distributed protocols, Wait-free read/write registers, Test-and-set objects, Fault-tolerance, Randomized algorithms, Shared memory, Atomicity, Symmetry breaking, Adaptive adversary
21	Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu	A comprehensive estimation technique for high-level synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
21	Eun-Hee Hyun, Sung-Hee Kim	Real-time mobile data management using a minimal MMDB.	RTCSA	1995	DBLP DOI BibTeX RDF	real-time mobile data management, minimal MMDB, main memory database system, mobile computational viewpoint, location registers, fast access methods, digital cellular system, real-time systems, middleware, database management systems, relational data model, client/server architecture, design considerations
21	Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa	A superscalar RISC processor with pseudo vector processing feature.	ICCD	1995	DBLP DOI BibTeX RDF	superscalar RISC processor, pseudo vector processing, architectural extension, floating-point registers, scoreboard-based dependency check, pipeline stage optimization, 267 MFLOPS, 1.2 Gbyte/s, performance evaluation, performance, computer architecture, memory access, reduced instruction set computing, vector processor systems
21	Marc Tremblay, Bill Joy 0001, Ken Shin	A three dimensional register file for superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows
21	Siamak Arya, Howard Sachs, Sreeram Duvvuru	An architecture for high instruction level parallelism.	HICSS (1)	1995	DBLP DOI BibTeX RDF	high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution
21	Nadime Zacharia, Janusz Rajski, Jerzy Tyszer	Decompression of test data using variable-length seed LFSRs.	VTS	1995	DBLP DOI BibTeX RDF	test data decompression, variable-length seed LFSRs, deterministic test vectors, scan circuits, multiple polynomial LFSR, encoding efficiency, logic testing, built-in self test, integrated circuit testing, encoding, automatic testing, polynomials, linear feedback shift register, shift registers, modular design, digital integrated circuits
21	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
21	Andrew Klapper, Mark Goresky	Cryptanalysis Based on 2-Adic Rational Approximation.	CRYPTO	1995	DBLP DOI BibTeX RDF	cryptanalysis, Binary sequences, rational approximation, feedback with carry shift registers, 2-adic numbers
21	Chunming Qiao, Rami G. Melhem	Reconfiguration with Time Division Multiplexed MIN's for Multiprocessor.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	MIN's, multiprocessor communications, TDM-MIN's, N time slots, n-dimensional hypercubes, Markov analysis, partition of connection requests, partitioning, mappings, reconfiguration, multiprocessor interconnection networks, embedding, meshes, NP-hard, multistage interconnection networks, optical interconnects, rings, binary trees, shift registers, time division multiplexing, time division multiplexed, round-robin, cube-connected-cycles
21	Miodrag J. Mihaljevic, Jovan Dj. Golic	Convergence of a Bayesian Iterative Error-Correction Procedure on a Noisy Shift register Sequence.	EUROCRYPT	1992	DBLP DOI BibTeX RDF	Algorithms, Cryptanalysis, Convergence, Decoding, Shift registers, Fast correlation attack
21	Hussein M. Alnuweiri, Viktor K. Prasanna	Fast Image Labeling Using Local Operators on Mesh-Connected Computers.	IEEE Trans. Pattern Anal. Mach. Intell.	1991	DBLP DOI BibTeX RDF	bit-serial processors, local operators, asymptotic time complexity, very fast shift registers, parallel algorithm, parallel algorithms, computational complexity, computational complexity, parallel architectures, parallel architectures, computerised picture processing, computerised picture processing, stacks, communication links, mesh-connected computers, image labeling
21	Vicki H. Allan, Robert A. Mueller	Compaction with General Timing.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	general synchronous timing, microcode generation systems, branch delays, volatile registers, microoperations, multiple microinstructions, clocked microarchitectures, compilers, synchronisation, program compilers, microprogramming, target architecture, data-dependency graphs
19	Weifeng Xu, Russell Tessier	Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
19	Minwook Ahn, Yunheung Paek	Register coalescing techniques for heterogeneous register architecture with copy sifting.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	heterogeneous register architecture, compiler, Register allocation, embedded processors, register coalescing
19	Guang Zeng, Yang Yang, Wenbao Han, Shuqin Fan	Word Oriented Cascade Jump sigma-LFSR.	AAECC	2009	DBLP DOI BibTeX RDF	Cascade Jump LFSR, ??LFSR, Fast Software Encryption, Stream Cipher, Linear Feedback Shift Register(LFSR)
19	Praveen Raghavan, Francky Catthoor	SARA: StreAm register allocation.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	stream register, low power, register allocation, spatial locality
19	Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu	Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor.	CSE (2)	2009	DBLP DOI BibTeX RDF
19	Smita Krishnaswamy, Igor L. Markov, John P. Hayes	Improving testability and soft-error resilience through retiming.	DAC	2009	DBLP DOI BibTeX RDF	testability, soft errors, retiming
19	Suhyun Kim, Soo-Mook Moon	Rotating register allocation with multiple rotating branches.	ICS	2008	DBLP DOI BibTeX RDF	rotating register, register allocation, software pipelining
19	Yehuda Afek, Iftah Gamzu, Irit Levy, Michael Merritt, Gadi Taubenfeld	Group Renaming.	OPODIS	2008	DBLP DOI BibTeX RDF
19	Xuan Guan, Yunsi Fei	Reducing power consumption of embedded processors through register file partitioning and compiler support.	ASAP	2008	DBLP DOI BibTeX RDF
19	Viswanathan Subramanian, Arun K. Somani	Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
19	Haluk Rahmi Topcuoglu, Betül Demiröz, Mahmut T. Kandemir	Solving the Register Allocation Problem for Embedded Systems Using a Hybrid Evolutionary Algorithm.	IEEE Trans. Evol. Comput.	2007	DBLP DOI BibTeX RDF
19	Minwook Ahn, Jooyeon Lee, Yunheung Paek	Optimistic coalescing for heterogeneous register architectures.	LCTES	2007	DBLP DOI BibTeX RDF	heterogeneous register architecture, register coalesing, compiler, register allocation, embedded processors
19	Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001	Early Register Release for Out-of-Order Processors with RegisterWindows.	PACT	2007	DBLP DOI BibTeX RDF
19	Dirk Stegemann	Extended BDD-Based Cryptanalysis of Keystream Generators.	Selected Areas in Cryptography	2007	DBLP DOI BibTeX RDF	F-FCSR, cryptanalysis, Stream cipher, BDD, Trivium, Grain
19	JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally	Register pointer architecture for efficient embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
19	Xingwu Liu, Zhiwei Xu 0002, Juhua Pu	Revisiting the Impossibility for Boosting Service Resilience.	TAMC	2007	DBLP DOI BibTeX RDF
19	Neng-Fa Zhou	A Register-Free Abstract Prolog Machine with Jumbo Instructions.	ICLP	2007	DBLP DOI BibTeX RDF
19	Faith Ellen, Panagiota Fatourou, Eric Ruppert	The Space Complexity of Unbounded Timestamps.	DISC	2007	DBLP DOI BibTeX RDF	lower bounds, anonymous, shared memory, timestamps
19	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
19	Philip Brisk, Ajay Kumar Verma, Paolo Ienne	Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design.	ICCAD	2007	DBLP DOI BibTeX RDF
19	Yong Ki Lee, Ingrid Verbauwhede	A Compact Architecture for Montgomery Elliptic Curve Scalar Multiplication Processor.	WISA	2007	DBLP DOI BibTeX RDF	Compact Elliptic Curve Processor, Montgomery Scalar Multiplication
19	Yukihide Kohira, Atsushi Takahashi 0001	A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Mallik Kandala, Wei Zhang 0002, Laurence Tianruo Yang	An Area-Efficient Approach to Improving Register File Reliability against Transient Errors.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
19	James Aspnes, Faith Ellen Fich, Eric Ruppert	Relationships between broadcast and shared memory in reliable anonymous distributed systems.	Distributed Comput.	2006	DBLP DOI BibTeX RDF	Simulations, Robustness, Broadcast, Anonymous, Shared memory
19	Cheng-Yi Xiong, Jin-Wen Tian, Jian Liu 0011	A note on "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet Transform".	IEEE Trans. Signal Process.	2006	DBLP DOI BibTeX RDF
19	Jiachun Wu, Hao Zhang, Jianxin Liao, Xiaomin Zhu 0002, Bo Yang	Modeling and Analysis for an Enhanced Three-Tier Dynamic Location Management in 3G.	WASA	2006	DBLP DOI BibTeX RDF
19	Bakhtiar Affendi Rosdi, Atsushi Takahashi 0001	Low area pipelined circuits by multi-clock cycle paths and clock scheduling.	ASP-DAC	2006	DBLP DOI BibTeX RDF
19	Philipp Rohde	On the µ-Calculus Augmented with Sabotage.	FoSSaCS	2006	DBLP DOI BibTeX RDF
19	Abhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu	Issues and Support for Dynamic Register Allocation.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
19	Shih-Hsu Huang, Chia-Ming Chang 0002, Yow-Tyng Nieh	State re-encoding for peak current minimization.	ICCAD	2006	DBLP DOI BibTeX RDF	peak current, sequential circuit synthesis, finite state machine
19	Sultan Al-Hinai, Lynn Margaret Batten, Bernard D. Colbert, Kenneth Koon-Ho Wong	Algebraic Attacks on Clock-Controlled Stream Ciphers.	ACISP	2006	DBLP DOI BibTeX RDF	irregular clocking, stream cipher, linear feedback shift register, algebraic attack, clock control
19	Panagiota Fatourou, Nikolaos D. Kallimanis	Single-scanner multi-writer snapshot implementations are fast!	PODC	2006	DBLP DOI BibTeX RDF	atomic objects, multi-writer, single-scanner, shared memory systems, asynchronous, wait-free, snapshot
19	Florent Bouchez, Alain Darte, Christophe Guillon, Fabrice Rastello	Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How.	LCPC	2006	DBLP DOI BibTeX RDF
19	Burkhard Englert	On the Cost of Uniform Protocols Whose Memory Consumption Is Adaptive to Interval Contention.	OPODIS	2006	DBLP DOI BibTeX RDF
19	Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter	Recovery Mechanisms for Dual Core Architectures.	DFT	2006	DBLP DOI BibTeX RDF
19	Panagiota Fatourou, Faith Ellen Fich, Eric Ruppert	Time-space tradeoffs for implementations of snapshots.	STOC	2006	DBLP DOI BibTeX RDF	anonymous processes, distributed computing, lower bound, shared memory, wait-free, snapshot, time-space tradeoff