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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
34 | Ronaldo Rodrigues Ferreira, Gabriel L. Nazar, Jean da Rolt, Álvaro F. Moreira, Luigi Carro |
Live-Out Register Fencing: Interrupt-Triggered Soft Error Correction Based on the Elimination of Register-to-Register Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 15(3), pp. 60:1-60:25, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
34 | Nam Duong, Rakesh Kumar |
Register Multimapping: A technique for reducing register bank conflicts in processors with large register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SASP ![In: Proceedings of the IEEE 7th Symposium on Application Specific Processors, SASP 2009, San Francisco, CA, USA , July 27-28, 2009, pp. 50-53, 2009, IEEE Computer Society, 978-1-4244-4939-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Hanspeter Mössenböck, Michael Pfeiffer 0004 |
Linear Scan Register Allocation in the Context of SSA Form and Register Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 11th International Conference, CC 2002, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2002, Grenoble, France, April 8-12, 2002, Proceedings, pp. 229-246, 2002, Springer, 3-540-43369-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González 0001 |
Modulo Scheduling with Reduced Register Pressure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(6), pp. 625-638, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
register allocation, software pipelining, Instruction scheduling, loop scheduling, register spilling |
32 | Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz |
A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998, pp. 216-225, 1998, ACM/IEEE Computer Society, 0-8186-8609-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
dependency redirection, physical register reuse, register and memory renaming, result reuse, value temporal locality |
32 | Meng-chou Chang, Feipei Lai |
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(3), pp. 278-293, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors |
32 | Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke |
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010, pp. 180-189, 2010, ACM, 978-1-60558-635-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
ARCompact, dual instruction set architecture, variable-length instructions, register allocation, code size, instruction selection |
32 | Xuejun Yang, Yu Deng 0001, Li Wang 0027, Xiaobo Yan, Jing Du 0002, Ying Zhang 0032, Guibin Wang, Tao Tang 0001 |
SRF Coloring: Stream Register File Allocation via Graph Coloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 24(1), pp. 152-164, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SRF coloring, stream register file, memory management, compiler optimization, graph coloring, stream processor |
32 | Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum |
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 68-71, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dynamic resizing, performance, embedded processor, register file |
32 | Kimish Patel, Wonbok Lee, Massoud Pedram |
Active bank switching for temperature control of the register file in a microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 231-234, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register file, thermal model, temperature-aware design |
32 | Joel David Hamkins, Russell G. Miller |
Post's Problem for Ordinal Register Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CiE ![In: Computation and Logic in the Real World, Third Conference on Computability in Europe, CiE 2007, Siena, Italy, June 18-23, 2007, Proceedings, pp. 358-367, 2007, Springer, 978-3-540-73000-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ordinal computability, ordinal register machine, Post’s Problem, computability |
32 | Michael Drmota, Helmut Prodinger |
The register function for t-ary trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Algorithms ![In: ACM Trans. Algorithms 2(3), pp. 318-334, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Horton-Strahler numbers, Register function, generating functions, asymptotics |
32 | Chantana Chantrapornchai, Wanlop Surakumpolthorn, Edwin Hsing-Mean Sha |
Design Exploration Framework Under Impreciseness Based on Register-Constrained Inclusion Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIAN ![In: Advances in Computer Science - ASIAN 2004, Higher-Level Decision Making, 9th Asian Computing Science Conference, Dedicated to Jean-Louis Lassez on the Occasion of His 5th Cycle Birthday, Chiang Mai, Thailand, December 8-10, 2004, Proceedings, pp. 78-92, 2004, Springer, 3-540-24087-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Imprecise Design Exploration, Scheduling/Allocation, Multiple design attributes, Register constraint, Inclusion Scheduling, Imprecise information |
32 | Kun Zhang 0006, Tao Zhang 0037, Santosh Pande |
Binary translation to improve energy efficiency through post-pass register re-allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2004, September 27-29, 2004, Pisa, Italy, Fourth ACM International Conference On Embedded Software, Proceedings, pp. 74-85, 2004, ACM, 1-58113-860-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cache power consumption, dead registers, register re-allocation, unused registers |
32 | Masaharu Goto, Toshinori Sato |
Leakage Energy Reduction in Register Renaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS Workshops ![In: 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 23-24 March 2004, Hachioji, Tokyo, Japan, pp. 890-895, 2004, IEEE Computer Society, 0-7695-2087-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
super-scalar processors, embedded processors, register renaming, deep submicron, Leakage energy |
32 | Nam Sung Kim, Trevor N. Mudge |
Reducing register ports using delayed write-back queues and operand pre-fetch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003, pp. 172-182, 2003, ACM, 1-58113-733-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
write queue, low power, instruction level parallelism, register file, out-of-order processor |
32 | Torben Amtoft, Robert Muller |
Inferring annotated types for inter-procedural register allocation with constructor flattening. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TLDI ![In: Proceedings of TLDI'03: 2003 ACM SIGPLAN International Workshop on Types in Languages Design and Implementation, New Orleans, Louisiana, USA, January 18, 2003, pp. 86-97, 2003, ACM, 1-58113-649-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
type systems, register allocation, effects, defunctionalization, certifying compilers |
32 | Josep M. Codina, F. Jesús Sánchez, Antonio González 0001 |
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 175-184, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
register allocation, Modulo scheduling, clustered architectures, spill code, cluster assignment |
32 | Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan 0002 |
CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 228-233, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Register and Module Assignment Design for low power, High level synthesis, Low power design, Floorplanning |
32 | Massimiliano Poletto, Vivek Sarkar |
Linear scan register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 21(5), pp. 895-913, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
compilers, register allocation, code optimization |
32 | Matthias Mutz |
Register Transfer Level VHDL Models without Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 153-158, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VHDL RT subset, register transfer level models |
32 | Ambuj K. Singh, James H. Anderson, Mohamed G. Gouda |
The Elusive Atomic Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 41(2), pp. 311-339, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
linearizability, atomic register, wait-free synchronization |
32 | Werner E. Kluge |
Data File Management in Shift Register Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Database Syst. ![In: ACM Trans. Database Syst. 3(2), pp. 159-177, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
LIFO/FIFO operation modes, management of sequentially organized files, record retrieval, updating, insertion, data transformations, deletion, relocation, shift-register memories |
32 | Joseph S. M. Ho, Ian F. Akyildiz |
Dynamic hierarchical database architecture for location management in PCS networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 5(5), pp. 646-660, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
call delivery, directory register, location registeration, visitor location register, home location register |
31 | Anjali Mahajan, M. Sadique Ali |
Hybrid Evolutionary Algorithm for the Graph Coloring Register Allocation Problem for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Comput. Sci. ![In: Transactions on Computational Science V, Special Issue on Cognitive Knowledge Representation, pp. 206-219, 2009, Springer, 978-3-642-02096-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose |
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(1), pp. 82-95, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
General, Microprocessors, Pipeline processors, Performance attributes |
31 | Mei Wen, Nan Wu 0003, Maolin Guan, Chunyuan Zhang |
Load scheduling: Reducing pressure on distributed register files for free. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 340-345, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley |
Register Bank Assignment for Spatially Partitioned Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 21th International Workshop, LCPC 2008, Edmonton, Canada, July 31 - August 2, 2008, Revised Selected Papers, pp. 64-79, 2008, Springer, 978-3-540-89739-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Haluk Rahmi Topcuoglu, Betül Demiröz, Mahmut T. Kandemir |
Solving the Register Allocation Problem for Embedded Systems Using a Hybrid Evolutionary Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 11(5), pp. 620-634, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Weihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu |
Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 434, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar 0001, Chris Reade |
Register Sharing Verification During Data-Path Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCTA ![In: 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 5-7 March 2007, Kolkata, India, pp. 135-140, 2007, IEEE Computer Society, 978-0-7695-2770-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Santosh G. Nagarakatte, R. Govindarajan |
Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 16th International Conference, CC 2007, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2007, Braga, Portugal, March 26-30, 2007, Proceedings, pp. 126-140, 2007, Springer, 978-3-540-71228-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Noureddine Chabini, Wayne H. Wolf |
Register binding guided by the size of variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 587-594, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Qingying Deng, Minxuan Zhang, Jiang Jiang |
Register File Management and Compiler Optimization on EDSMT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA Workshops ![In: Frontiers of High Performance Computing and Networking ISPA 2007 Workshops, ISPA 2007 International Workshops SSDSN, UPWN, WISH, SGC, ParDMCom, HiPCoMB, and IST-AWSN Niagara Falls, Canada, August 28 - September 1, 2007, Proceedings, pp. 394-403, 2007, Springer, 978-3-540-74766-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim |
Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 765-770, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Dae-Hwan Kim, Hyuk-Jae Lee |
Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 269-278, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | V. Krishna Nandivada, Jens Palsberg |
SARA: Combining Stack Allocation and Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 15th International Conference, CC 2006, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2006, Vienna, Austria, March 30-31, 2006, Proceedings, pp. 232-246, 2006, Springer, 3-540-33050-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Fernando Magno Quintão Pereira, Jens Palsberg |
Register Allocation After Classical SSA Elimination is NP-Complete. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FoSSaCS ![In: Foundations of Software Science and Computation Structures, 9th International Conference, FOSSACS 2006, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2006, Vienna, Austria, March 25-31, 2006, Proceedings, pp. 79-93, 2006, Springer, 3-540-33045-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Jongwoo Bae, Neungsoo Park, Seong-Won Lee |
Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 805-813, 2006, Springer, 3-540-36679-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya |
A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 545-553, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu |
Register binding for clock period minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 439-444, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high-level synthesis, clock skew, timing optimization |
31 | Khaing Khaing Kyi Win, Weng-Fai Wong |
Cooperative Instruction Scheduling with Linear Scan Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2005, 12th International Conference, Goa, India, December 18-21, 2005, Proceedings, pp. 528-537, 2005, Springer, 3-540-30936-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Rami Beidas, Jianwen Zhu |
Scalable interprocedural register allocation for high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 511-516, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Nagendran Rangan, Karam S. Chatha |
A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 564-569, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Kentaro Hamayasu, Vasily G. Moshnyaga |
Impact of Register-Cache Bandwidth Variation on Processor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 212-225, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Saisanthosh Balakrishnan, Gurindar S. Sohi |
Exploiting Value Locality in Physical Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 265-276, 2003, IEEE Computer Society, 0-7695-2043-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Atsushi Ohori |
Register Allocation by Proof Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESOP ![In: Programming Languages and Systems, 12th European Symposium on Programming, ESOP 2003, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2003, Warsaw, Poland, April 7-11, 2003, Proceedings, pp. 399-413, 2003, Springer, 3-540-00886-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa |
On the Design of a Register Queue Based Processor Architecture (FaRM-rq). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, International Symposium, ISPA 2003, Aizu, Japan, July 2-4, 2003, Proceedings, pp. 248-262, 2003, Springer, 3-540-40523-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Ramesh Karri, Balakrishnan Iyer, Israel Koren |
Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8), pp. 877-888, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Xuemei Zhao, Yizheng Ye |
Design and Realization of a Low Power Register File Using Energy Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 268-277, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Changqing Fu, Kent D. Wilken |
A faster optimal register allocator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 245-256, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Lin Zhong 0001, Jiong Luo, Yunsi Fei, Niraj K. Jha |
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 391-394, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, S. Wolter, Steffen Buch, Marek Wróblewski, Josef A. Nossek |
Low power register file architecture for application specific DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 89-92, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan |
Analysis of the influence of register file size on energyconsumption, code size, and execution time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11), pp. 1329-1337, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Mike J. G. Lewis, L. E. M. Brackenbury |
Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 4-14, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Sid Ahmed Ali Touati |
Register Saturation in Superscalar and VLIW Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 213-228, 2001, Springer, 3-540-41861-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Soner Önder, Rajiv Gupta 0001 |
Load and store reuse using register file contents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 15th international conference on Supercomputing, ICS 2001, Sorrento, Napoli, Italy, June 16-21, 2001, pp. 289-302, 2001, ACM, 1-58113-410-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Nazanin Mansouri, Ranga Vemuri |
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 223-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
A design-for-testability technique for register-transfer level circuits using control/data flow extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8), pp. 706-723, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Sylvain Lelait, Guang R. Gao, Christine Eisenbeis |
A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 7th International Conference, CC'98, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings, pp. 204-218, 1998, Springer, 3-540-64304-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Fred C. Chow, Robert Kennedy, Shin-Ming Liu, Raymond Lo, Peng Tu |
Register Promotion by Partial Redundancy Elimination of Loads and Stores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), Montreal, Canada, June 17-19, 1998, pp. 26-37, 1998, ACM, 0-89791-987-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Johan Agat |
Types for Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Implementation of Functional Languages ![In: Implementation of Functional Languages, 9th International Workshop, IFL'97, St. Andrews, Scotland, UK, September 10-12, 1997, Selected Papers, pp. 92-111, 1997, Springer, 3-540-64849-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Silvia M. Müller, Uzi Vishkin |
Conflict-Free Access to Multiple Single-Ported Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 672-678, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Tsung-Yi Wu, Youn-Long Lin |
Register minimization beyond sharing among variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12), pp. 1583-1587, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Todd A. Proebsting, Charles N. Fischer |
Demand-Driven Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 18(6), pp. 683-710, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
optimizing compiler |
31 | David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker |
Global Predicate Analysis and Its Application to Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 114-125, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Rajiv Gupta 0001, Mary Lou Soffa, Denise Ombres |
Efficient Register Allocation via Coloring Using Clique Separators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 16(3), pp. 370-386, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
clique separators, node priorities, graph coloring, spans, spill code, interference graph |
31 | Qi Ning |
Register allocation for optimal loop scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASCON ![In: Proceedings of the 1993 Conference of the Centre for Advanced Studies on Collaborative Research, October 24-28, 1993, Toronto, Ontario, Canada, 2 Volumes, pp. 942-955, 1993, IBM. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
31 | Todd A. Proebsting, Charles N. Fischer |
Probalistic Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (PLDI), San Francisco, California, USA, June 17-19, 1992, pp. 300-310, 1992, ACM, 0-89791-475-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
31 | Angelika Zobel |
Program structure as basis for parallelizing global register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCL ![In: ICCL'92, Proceedings of the 1992 International Conference on Computer Languages, Oakland, California, USA, 20-23 Apr 1992, pp. 262-271, 1992, IEEE Computer Society, 0-8186-2585-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
31 | Philip H. Sweany, Steven J. Beaty |
Post-compaction register assignment in a retargetable compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 107-116, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
31 | Vatsa Santhanam, Daryl Odnert |
Register Allocation Across Procedure and Module Boundaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'90 Conference on Programming Language Design and Implementation (PLDI), White Plains, New York, USA, June 20-22, 1990, pp. 28-39, 1990, ACM, 0-89791-364-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
RISC |
31 | Gregory J. Chaitin |
Register Allocation & Spilling via Graph Coloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGPLAN Symposium on Compiler Construction ![In: Proceedings of the SIGPLAN '82 Symposium on Compiler Construction, Boston, Massachusetts, USA, June 23-25, 1982, pp. 98-105, 1982, ACM, 0-89791-074-5. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
31 | Gregory J. Chaitin |
Register allocation and spilling via graph coloring (with retrospective) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Best of PLDI ![In: 20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation 1979-1999, A Selection, pp. 66-74, 1982, ACM, 1-58113-623-4. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
31 | David R. Ditzel, Hubert R. McLellan |
Register Allocation for Free: The C Machine Stack Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, Palo Alto, California, USA, March 1-3, 1982., pp. 48-56, 1982, ACM Press, 0-89791-066-4. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
31 | Philip Brisk, Majid Sarrafzadeh |
Interference graphs for procedures in static single information form are interval graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, Nice, France, April 20, 2007, pp. 101-110, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
k-colorable subgraph problem, linear scan register allocation, static single information (SSI) form, compilers, register allocation, interval graph |
31 | Xiaowei Li 0001, Toshimitsu Masuzawa, Hideo Fujiwara |
Strong self-testability for data paths high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 229-234, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment |
31 | Andrzej Hlawiczka, Michal Kopec |
Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 380-385, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
serial seeding, linear hybrid cellular automata, n-cell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, n-bit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flip-flops, flip-flops, shift registers, pattern generators, integrated circuit economics |
31 | Frank Mayer, Albrecht P. Stroele |
A Versatile BIST Technique Combining Test Registers and Accumulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 412-, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
test register, built-in self-test, register-transfer level, accumulator |
31 | Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu |
A MISR Computation Algorithm for Fast Signature Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 213-218, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
single-input signature register, memory-oriented policy, time-oriented policy, reverse zero-checking policy, Multiple-input signature register |
31 | Joan Carletta, Christos A. Papachristou |
Structural constraints for circular self-test paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 486-491, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits |
31 | David W. Wall |
Experience with a Software-Defined Machine Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 14(3), pp. 299-338, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
optimization, profiling, graph coloring, register allocation, RISC, pipeline scheduling, intermediate language, register windows, interprocedural |
30 | Weifeng Xu, Russell Tessier |
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(3), pp. 11:1-11:40, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure |
30 | Ioannis E. Venetis, Guang R. Gao |
Mapping the LU decomposition on a many-core architecture: challenges and solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 71-80, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
register tiling, load balancing, multi-core, local memory, LU decomposition |
30 | Peter Koepke |
Ordinal Computability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CiE ![In: Mathematical Theory and Computational Practice, 5th Conference on Computability in Europe, CiE 2009, Heidelberg, Germany, July 19-24, 2009. Proceedings, pp. 280-289, 2009, Springer, 978-3-642-03072-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Ordinal machines, Infinite Time Register Machines, Constructible sets |
30 | Virgil Palanciuc, Dragos Badea |
A Spill Code Minimization Technique-Application in the Metrowerks StarCore C Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 32(6), pp. 475-499, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
rematerialization, Optimization, register allocation, spill code |
30 | Lal George, Matthias Blume |
Taming the IXP network processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, San Diego, California, USA, June 9-11, 2003, pp. 26-37, 2003, ACM, 1-58113-662-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Intel IXA, bank assignment, programming languages, code generation, register allocation, integer linear programming, network processors |
30 | Christoph W. Keßler, Andrzej Bednarski |
A Dynamic Programming Approach to Optimal Integrated Code Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 165-174, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
integrated code generation, time profile, dynamic programming, register allocation, instruction scheduling, instruction selection |
29 | Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda |
Power Reduction in VLIW Processor with Compiler Driven Bypass Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 233-238, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin |
Speculative software management of datapath-width for energy optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 78-87, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
narrow-width regions, compiler, reconfigurable computing, speculative execution, energy management, clock-gating |
29 | Xiaotong Zhuang, Santosh Pande, John S. Greenland Jr. |
A Framework for Parallelizing Load/Stores on Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 68-79, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Chii-Hwa Lee, Min-Shiang Hwang, Wei-Pang Yang |
Enhanced privacy and authentication for the global system for mobile communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Networks ![In: Wirel. Networks 5(4), pp. 231-243, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Luis Villa, Roger Espasa, Mateo Valero |
Effective Usage of Vector Registers in Advanced Vector Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 250-260, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Alfred V. Aho, Stephen C. Johnson, Jeffrey D. Ullman |
Code Generation for Machines with Multiregister Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Conference Record of the Fourth ACM Symposium on Principles of Programming Languages, Los Angeles, California, USA, January 1977, pp. 21-28, 1977, ACM. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
|
28 | Brian R. Nickerson |
Graph Coloring Register Allocation for Processors with Multi-Register Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'90 Conference on Programming Language Design and Implementation (PLDI), White Plains, New York, USA, June 20-22, 1990, pp. 40-52, 1990, ACM, 0-89791-364-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Intel 80960 |
27 | Diego Figueira |
Forward-XPath and extended register automata on data-trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDT ![In: Database Theory - ICDT 2010, 13th International Conference, Lausanne, Switzerland, March 23-25, 2010, Proceedings, pp. 231-241, 2010, ACM, 978-1-60558-947-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
alternating tree register automata, data-tree, forward XPath, infinite alphabet, unranked ordered tree, XML |
27 | Jongeun Lee, Aviral Shrivastava |
A compiler optimization to reduce soft errors in register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 41-49, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
architectural vulnerability factor, link-time optimization, embedded system, compilation, static analysis, soft error, register file |
27 | Insup Shin, Seungwhun Paik, Youngsoo Shin |
Register allocation for high-level synthesis using dual supply voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 937-942, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power, high-level synthesis, register allocation, dual supply voltage |
27 | Maziar Goudarzi, Tohru Ishihara |
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 383-386, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
asymmetric sram, leakage, instruction cache, register renaming |
27 | Han Liang, Piyush Mishra, Kaijie Wu 0001 |
Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 243-252, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy |
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