Search results for "FSMs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Mariusz Rawski, Henry Selvaraj, Tadeusz Luba	An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices.	DSD	2003	DBLP DOI BibTeX RDF
11	James Moscola, John W. Lockwood, Ronald Prescott Loui, Michael Pachos	Implementation of a Content-Scanning Module for an Internet Firewall.	FCCM	2003	DBLP DOI BibTeX RDF
11	Amit K. Chopra, Munindar P. Singh	Nonmonotonic Commitment Machines.	Workshop on Agent Communication Languages	2003	DBLP DOI BibTeX RDF
11	Dario Bonino, Fulvio Corno, Giovanni Squillero	A Real-Time Evolutionary Algorithm for Web Prediction.	Web Intelligence	2003	DBLP DOI BibTeX RDF
11	Simon M. Lucas	Evolving Finite State Transducers: Some Initial Explorations.	EuroGP	2003	DBLP DOI BibTeX RDF
11	Carlos Molina-Jiménez, Santosh K. Shrivastava, Ellis Solaiman, John P. Warne	Contract Representation for Run-time Monitoring and Enforcement.	CEC	2003	DBLP DOI BibTeX RDF
11	José C. Monteiro 0001, Arlindo L. Oliveira	Implicit FSM decomposition applied to low-power design.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
11	Priyank Kalla, Maciej J. Ciesielski	A comprehensive approach to the partial scan problem using implicitstate enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
11	J. Jenny Li, W. Eric Wong	Automatic Test Generation from Communicating Extended Finite State Machine (CEFSM)-Based Models.	Symposium on Object-Oriented Real-Time Distributed Computing	2002	DBLP DOI BibTeX RDF	CEFSM, specification, test generation, SDL
11	Tim Menzies, David Owen 0002, Bojan Cukic	You Seem Friendly, But Can I Trust You?	FAABS	2002	DBLP DOI BibTeX RDF
11	Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka	A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
11	Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo	FSM Decomposition for Low Power in FPGA.	FPL	2002	DBLP DOI BibTeX RDF
11	Wolfgang Grieskamp, Yuri Gurevich, Wolfram Schulte, Margus Veanes	Generating finite state machines from abstract state machines.	ISSTA	2002	DBLP DOI BibTeX RDF	finite state machine, test case generation, FSM, abstract state machine, executable specification, ASM
11	John Whaley, Michael C. Martin, Monica S. Lam	Automatic extraction of object-oriented component interfaces.	ISSTA	2002	DBLP DOI BibTeX RDF
11	Henry Selvaraj, Mariusz Rawski, Tadeusz Luba	FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition.	ITCC	2002	DBLP DOI BibTeX RDF	programmable read only memory, Boolean functions, implementation, digital circuits, sequential machines, logic minimization
11	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	Bisimulation relation, complete-1-distinguishability, finite state machine equivalence, sequential logic synthesis, equivalence checking
11	Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli	Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems.	ACSD	2001	DBLP DOI BibTeX RDF
11	Michael Affenzeller, Franz Pichler, Rudolf Mittelmann	On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata.	EUROCAST	2001	DBLP DOI BibTeX RDF
11	Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou	Automatic Functional Vector Generation Using the Interacting FSM Model.	ISQED	2001	DBLP DOI BibTeX RDF
11	Diana Marculescu, Radu Marculescu, Massoud Pedram	Theoretical bounds for switching activity analysis in finite-state machines.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
11	Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara	A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	non-scan design for testability, complete fault efficiency, controllers, at-speed test
11	Alexandre Petrenko	Fault Model-Driven Test Derivation from Finite State Models: Annotated Bibliography.	MOVEP	2000	DBLP DOI BibTeX RDF
11	Franco Fummi, Donatella Sciuto, Micaela Serra	Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	sequential circuits, functional testing, Synthesis for testability, logic minimization, redundant faults, redundancies removal
11	Valeri Solovjev	Refined CPLD Macrocell Architecture for the Effective FSM Implementation.	EUROMICRO	1999	DBLP DOI BibTeX RDF
11	Chien-Nan Jimmy Liu, Jing-Yang Jou	An Efficient Functional Coverage Test for HDL Descriptions at RTL.	ICCD	1999	DBLP DOI BibTeX RDF	verification, coverage, FSM, HDL
11	Imtiaz Ahmad, Raza Ul-Mustafa	On State Assignment of Finite State Machines Using Hypercube Embedding Approach.	ICCD	1999	DBLP DOI BibTeX RDF	hypercube embedding, gradient projection method, Kernighan Lin algorithm, finite state machine, state assignment
11	Oskar Mencer, Marco Platzner	Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.	HICSS	1999	DBLP DOI BibTeX RDF
11	Peter Bodorik, Dawn N. Jutla, A. Agarwal	Recoverable Virtual Memory through the Multi-View Memory Computer System.	HICSS	1999	DBLP DOI BibTeX RDF	Recoverable Virtual Memory, Multi-view Virtual Memory, Protection Architecture, Architectural Support for Operating Systems, Access Control
11	Michael Nicolaidis, Yervant Zorian	On-Line Testing for VLSI - A Compendium of Approaches.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	fail-safe circuits, SEU hardened circuits, monitoring of reliability indicators, thermal monitors, radiation monitors, on-line testing, self-checking circuits, current monitors
11	Gianpiero Cabodi, Paolo Camurati, Stefano Quer	Auxiliary variables for BDD-based representation and manipulation of Boolean functions.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	finite state machines, binary decision diagrams, reachability analysis, functional decompositions
11	Udo Brockmeyer, Gunnar Wittich	Real-Time Verification of Statemate Designs.	CAV	1998	DBLP DOI BibTeX RDF
11	Olivier Coudert	A New Paradigm for Dichotomy-based Constrained Encoding.	DATE	1998	DBLP DOI BibTeX RDF	constrained state encoding, twin graph coloring, dichotomy
11	Samary Baranov	CAD System for ASM and FSM Synthesis.	FPL	1998	DBLP DOI BibTeX RDF
11	Bilung Lee, Edward A. Lee	Hierarchical Concurrent Finite State Machines in Ptolemy.	ACSD	1998	DBLP DOI BibTeX RDF	concurrency, finite state machine, heterogeneity, hierarchy
11	Diana Marculescu, Radu Marculescu, Massoud Pedram	Theoretical bounds for switching activity analysis in finite-state machines.	ISLPED	1998	DBLP DOI BibTeX RDF
11	Igor Lemberski	Modified Approach to Automata State Encoding for LUT FPGA Implementation.	EUROMICRO	1998	DBLP DOI BibTeX RDF
11	Denis Hommais, Frédéric Pétrot	Efficient Combinational Loops Handling for Cycle Precise Simulation of System on a Chip.	EUROMICRO	1998	DBLP DOI BibTeX RDF
11	José C. Monteiro 0001, Arlindo L. Oliveira	Finite State Machine Decomposition For Low Power.	DAC	1998	DBLP DOI BibTeX RDF	system-on-chip test, testing embedded core, intellectual property test
11	Ajay J. Daga, William P. Birmingham	Interface finite-state machines: definition, minimization, and decomposition.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
11	Wayne H. Wolf	Redundancy Removal during High-Level Synthesis Using Scheduling Don't-Cares.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	scheduling dont-care, high-level synthesis, redundancy
11	Thorsten Grötker, Rainer Schoenen, Heinrich Meyr	PCC: a modeling technique for mixed control/data flow systems.	ED&TC	1997	DBLP DOI BibTeX RDF
11	Prasoon Surti, Liang-Fang Chao, Akhilesh Tyagi	Low power FSM design using Huffman-style encoding.	ED&TC	1997	DBLP DOI BibTeX RDF
11	J. W. J. M. Rutten, Michel R. C. M. Berkelaar	Improved State Assignment for Burst Mode Finite State Machines.	ASYNC	1997	DBLP DOI BibTeX RDF	finite state machines, state assignment, asynchronous logic
11	René Klösch, Johannes Weidl, Georg Trausmuth, Harald C. Gall	Facilitating Program Comprehension via Generic Components for State Machines.	WPC	1997	DBLP DOI BibTeX RDF
11	Reinhard Gerndt, Rolf Ernst	An Event-Driven Multi-Threading Architecture for Embedded Systems.	CODES	1997	DBLP DOI BibTeX RDF	multi-threading architecture, embedded system, hardware/software-codesign, event-flow
11	Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli	Trace driven logic synthesis - application to power minimization.	ICCAD	1997	DBLP DOI BibTeX RDF	Low Power, Logic Synthesis
11	Frédéric Pétrot, Denis Hommais, Alain Greiner	Cycle precise core based hardware/software system simulation with predictable event propagation.	EUROMICRO	1997	DBLP DOI BibTeX RDF	hardware software system simulation, predictable event propagation, cycle precise core based system simulator, digital embedded systems, Mealy signals, combinational signals, MIPS R3000, microprocessor core, PI-Bus, Pentium 120, communication, graph, C, high level synthesis, memories, directed graph, FSM, topological sort, compile-time, communicating finite state machines
11	Franco Fummi, Mariagiovanna Sami, F. Tartarini	Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
11	Raj S. Mitra, Bishnupriya Bhattacharya, Luciano Lavagno	Asynchronous Implementation of Synchronous Esterel Specifications.	VLSI Design	1997	DBLP DOI BibTeX RDF
11	Diana Marculescu, Radu Marculescu, Massoud Pedram	Sequence Compaction for Probabilistic Analysis of Finite-State Machines.	DAC	1997	DBLP DOI BibTeX RDF
11	Raj S. Mitra, Partha S. Roop, Anupam Basu	A new algorithm for implementation of design functions by available devices.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
11	Rubin A. Parekhji, G. Venkatesh 0001, Sunil D. Sherlekar	Monitoring machine based synthesis technique for concurrent error detection in finite state machines.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	monitoring machines, finite state machine synthesis, concurrent error detection
11	Enrique Alba 0001, José M. Troya	Genetic Algorithms for Protocol Validation.	PPSN	1996	DBLP DOI BibTeX RDF
11	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential logic synthesis and verification, finite state machine equivalence, bisimulation relation, 1-distinguishability, 1-equivalence, formal verification
11	Olivier Coudert, C.-J. Richard Shi	Exact Dichotomy-based Constrained Encodi.	ICCD	1996	DBLP DOI BibTeX RDF	Sequential logic synthesis, constrained state encoding, clique partition, set covering, dichotomy, ZBDD
11	Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton	Early Quantification and Partitioned Transition Relations.	ICCD	1996	DBLP DOI BibTeX RDF
11	Franco Fummi, Donatella Sciuto, M. Serro	Synthesis for testability of large complexity controllers.	ICCD	1995	DBLP DOI BibTeX RDF	large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates
11	Bhed Bahadur Bista, Atsushi Togashi, Norio Shiratori	Extension of protocol synthesis to structured entities.	ICNP	1995	DBLP DOI BibTeX RDF
11	Chunduri Rama Mohan, Partha Pratim Chakrabarti	Combined optimization of area and testability during state assignment of PLA-based FSM's.	VLSI Design	1995	DBLP DOI BibTeX RDF	combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization
11	Chuan-Jin Shi, Janusz A. Brzozswski	An efficient algorithm for constrained encoding and its applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi	Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Ruchir Puri, Jun Gu	An efficient algorithm to search for minimal closed covers in sequential machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Asawaree Kalavade, Edward A. Lee	A Hardware-Software Codesign Methodology for DSP Applications.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
11	Pranav Ashar, Srinivas Devadas, A. Richard Newton	Optimum and heuristic algorithms for an approach to finite state machine decomposition.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Test generation and verification for highly sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Doron Drusinsky-Yoresh	A state assignment procedure for single-block implementation of state charts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Xuejun Du, Gary D. Hachtel, Bill Lin 0001, A. Richard Newton	MUSE: a multilevel symbolic encoding algorithm for state assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Srinivas Devadas, Kurt Keutzer	A unified approach to the synthesis of fully testable sequential machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Seiyang Yang, Maciej J. Ciesielski	Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Pranav Ashar, Srinivas Devadas, A. Richard Newton	Irredundant interacting sequential machines via optimal logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Thomas Müller-Wipperfürth	Linking CAST.FSM to Practical Applications.	EUROCAST	1991	DBLP DOI BibTeX RDF
11	Martin Geiger	CAST.FSM Applied to VLSI Synthesis: Experimental Results and Requirements for Industrial Use.	EUROCAST	1991	DBLP DOI BibTeX RDF
11	David Binger, David Knapp	Automatic synthesis of a dual-PLA controller with a counter.	MICRO	1990	DBLP BibTeX RDF
11	Wayne H. Wolf	The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines.	DAC	1990	DBLP DOI BibTeX RDF
11	W. Y. L. Chan, C. T. Vuong, M. R. Otp	An Improved Protocol Test Generation Procedure Based on UIOS.	SIGCOMM	1989	DBLP DOI BibTeX RDF
11	Maria C. Yuang, Aaron Kershenbaum	Parallel Protocol Verification: The Two-Phase Algorithm and Complexity Analysis.	Automatic Verification Methods for Finite State Systems	1989	DBLP DOI BibTeX RDF
11	Pierre G. Paulin	Horizontal Partitioning of PLA-based Finite State Machines.	DAC	1989	DBLP DOI BibTeX RDF
11	Sanjiv Ahuja	On communication software testing (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
11	Rainer Brück 0001, Bernd Kleinjohann, Thomas Kathöfer, Franz J. Rammig	Synthesis of concurrent modular controllers from algorithmic descriptions.	DAC	1986	DBLP DOI BibTeX RDF