Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Francesca Palumbo, Nicola Carta, Luigi Raffo |
The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: 2011 Conference on Design and Architectures for Signal and Image Processing, DASIP 2011, Tampere, Finland, November 2-4, 2011, pp. 178-185, 2011, IEEE, 978-1-4577-0620-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | José Augusto Miranda Nacif, Thiago S. F. Silva, Luiz Filipe M. Vieira, Alex Borges Vieira, Antônio Otávio Fernandes, Claudionor Nunes Coelho |
A cache based algorithm to predict HDL modules faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 12th Latin American Test Workshop, LATW 2011, Beach of Porto de Galinhas, Brazil, March 27-30, 2011, pp. 1-3, 2011, IEEE, 978-1-4577-1488-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Craig L. Glennie, Derek D. Lichti |
Static Calibration and Analysis of the Velodyne HDL-64E S2 for High Accuracy Mobile Scanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Remote. Sens. ![In: Remote. Sens. 2(6), pp. 1610-1624, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Danilo Pani, Francesca Palumbo, Luigi Raffo |
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 2(3/4), pp. 187-202, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Nicola Bombieri, Giuseppe Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli |
HIFSuite: Tools for HDL Code Conversion and Manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2010, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Mehran Massoumi, Assim Sagahyroon |
ASIC verification: Integrating formal verification with HDL-based courses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Appl. Eng. Educ. ![In: Comput. Appl. Eng. Educ. 18(2), pp. 269-276, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes |
Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UKSim ![In: Proceedings of the 12th UKSim, International Conference on Computer Modelling and Simulation, Cambridge, UK, 24-26 March 2010, pp. 153-158, 2010, IEEE Computer Society, 978-0-7695-4016-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi |
A mixed HDL/PLI test package. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, pp. 518-523, 2010, IEEE Computer Society, 978-1-4244-9555-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Vladimir Hahanov, Irina V. Hahanova, Ngene Christopher Umerah, Tiecoura Yves |
Testing and verification of HDL-models for SoC components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, pp. 77-82, 2010, IEEE Computer Society, 978-1-4244-9555-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi |
Virtual tester development using HDL/PLI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, pp. 412-415, 2010, IEEE Computer Society, 978-1-4244-9555-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Nicola Bombieri, Giuseppe Di Guglielmo, Luigi Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli |
HIFSuite: Tools for HDL code conversion and manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: IEEE International High Level Design Validation and Test Workshop, HLDVT 2010, Anaheim, CA, USA, 10-12 June 2010, pp. 40-41, 2010, IEEE Computer Society, 978-1-4244-7805-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | M. H. Haghbayan, Sara Karamati, Fatemeh Javaheri, Zainalabedin Navabi |
Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, pp. 53-56, 2010, IEEE Computer Society, 978-0-7695-4248-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Vladimir Zdraveski, Milos Jovanovik, Riste Stojanov, Dimitar Trajanov |
HDL IP Cores Search Engine Based on Semantic Web Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICT Innovations ![In: ICT Innovations 2010 - Second International Conference, ICT Innovations 2010, Ohrid, Macedonia, September 12-15, 2010. Revised Selected Papers, pp. 306-315, 2010, 978-3-642-19324-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Alessandro Cilardo, Paolo Durante, Carmelo Lofiego, Antonino Mazzeo |
Early Prediction of Hardware Complexity in HLL-to-HDL Translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy, pp. 483-488, 2010, IEEE Computer Society, 978-0-7695-4179-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon |
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, Charlotte, North Carolina, USA, 2-4 May 2010, pp. 149-156, 2010, IEEE Computer Society, 978-0-7695-4056-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Thomas Marconi, Dimitris Theodoropoulos, Koen Bertels, Georgi Gaydadjiev |
A novel HDL coding style to reduce power consumption for reconfigurable devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China, pp. 295-299, 2010, IEEE, 978-1-4244-8981-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | K. Dhanumjaya, G. Kiran Kumar, M. N. Giriprasad, M. Raja Reddy |
Design and Modeling of Power Efficient, High Performance 32-bit ALU through Advanced HDL Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICT ![In: Information and Communication Technologies - International Conference, ICT 2010, Kochi, Kerala, India, September 7-9, 2010. Proceedings, pp. 13-21, 2010, Springer, 978-3-642-15765-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | J. Dhore, A. P. Thakare |
Implementation of AES encoder using active-HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWET ![In: Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26 - 27, 2010, pp. 954-957, 2010, ACM, 978-1-60558-812-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Adam Duley, Chris Spandikow, Miryung Kim |
A program differencing algorithm for verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASE ![In: ASE 2010, 25th IEEE/ACM International Conference on Automated Software Engineering, Antwerp, Belgium, September 20-24, 2010, pp. 477-486, 2010, ACM, 978-1-4503-0116-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Terence Chan |
Race logic synthesis for a multithreaded HDL/ESL simulator for SoC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 1179-1182, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Frank Winkler 0001, Gerald Kell, Oliver Schrape, Hans Gustat, Ulrich Jagdhold |
HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Berlin, Germany, March 2-4, 2009, pp. 137-145, 2009, Universitätsbibliothek Berlin, Germany. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
19 | Yaseen Zaidi, Christoph Grimm 0001, Jan Haase 0001 |
Fast and unified SystemC AMS - HDL simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2009, September 22-24, 2009, Sophia Antipolis, France, Proceedings, pp. 1-6, 2009, IEEE, 978-2-9530504-1-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
19 | Grzegorz Janczyk, Tomasz Bieniek |
The HDL and FE Thermal Modeling of Heterogeneous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 128-131, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Wesley Holland, Yoginder S. Dandass |
Optimizing Pipelining in HDL Generated Automatically from C Source Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ERSA ![In: Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2008, Las Vegas, Nevada, USA, July 14-17, 2008, pp. 184-190, 2008, CSREA Press, 1-60132-064-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
19 | Ahmed El Oualkadi, Denis Flandre |
Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, pp. 173-178, 2008, IEEE Computer Society, 978-0-7695-3170-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi |
Utilizing HDL simulation engines for accelerating design and test processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2008 East-West Design & Test Symposium, EWDTS 2008, Lviv, Ukraine, October 9-12, 2008, pp. 371-375, 2008, IEEE Computer Society, 978-1-4244-3402-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Mohammad Shokrollah-Shirazi, Seyed Ghassem Miremadi |
FPGA-Based Fault Injection into Synthesizable Verilog HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSIRI ![In: Second International Conference on Secure System Integration and Reliability Improvement, SSIRI 2008, July 14-17, 2008, Yokohama, Japan, pp. 143-149, 2008, IEEE Computer Society, 978-0-7695-3266-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Jeongwoo Park, Bongchun Lee, Kyu-sam Lim, Jeong Hun Kim, Suki Kim, Kwang-Hyun Baek |
Co-simulation of SystemC TLM with RTL HDL for surveillance camera system verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 474-477, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Azam Beg |
An Efficient Realization of an OCR System Using HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC-AI ![In: Proceedings of the 2008 International Conference on Artificial Intelligence, ICAI 2008, July 14-17, 2008, Las Vegas, Nevada, USA, 2 Volumes (includes the 2008 International Conference on Machine Learning; Models, Technologies and Applications), pp. 74-78, 2008, CSREA Press, 1-60132-072-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
19 | Khalil Arshak, Essa Jafer, Declan McDonagh, Christian Ibala |
Modelling and simulation of wireless sensor system for health monitoring using HDL and Simulinkw mixed environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 1(5), pp. 508-518, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
Observability Analysis on HDL Descriptions for Effective Functional Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8), pp. 1509-1521, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Joseph Buck, Dong Wang, Yunshan Zhu |
Formal model construction using HDL simulation semantics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: IEEE International High Level Design Validation and Test Workshop, HLDVT 2007, Irvine, CA, USA, November 7-9, 2007, pp. 115-122, 2007, IEEE Computer Society, 978-1-4244-1480-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Mahshid Sedghi, Armin Alaghi, Elnaz Koopahi, Zainalabedin Navabi |
An HDL-Based Platform for High Level NoC Switch Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 16th Asian Test Symposium, ATS 2007, Beijing, China, October 8-11, 2007, pp. 453-458, 2007, IEEE, 0-7695-2890-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Uljana Reinsalu, Anton Arhipov, Teet Evartson, Peeter Ellervee |
HDL-s for Students with Different Background. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE '07, San Diego, CA, USA, June 3-4, 2007, pp. 69-70, 2007, IEEE Computer Society, 0-7695-2849-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Adam Milik, Andrzej Pulka |
Common HDL-Matlab Simulation Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2007, September 18-20, 2007, Barcelona, Spain, Proceedings, pp. 68-73, 2007, ECSI. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
19 | Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 50, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Yana Yankova, Koen Bertels, Stamatis Vassiliadis, Roel Meeuws, Arcilio Virginia |
Automated HDL Generation: Comparative Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2750-2753, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Min-Chuan Lin, Guo-Ruey Tsai, Chun-Rong Wu, Ching-Hui Lin |
Watermarking Technique for HDL-based IP Module Protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IIH-MSP ![In: 3rd International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007), Kaohsiung, Taiwan, 26-28 November 2007, Proceedings, pp. 393-396, 2007, IEEE Computer Society, 978-0-7695-2994-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Robert B. Reese, Mitchell A. Thornton |
Introduction to Logic Synthesis using Verilog HDL ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
DOI RDF |
|
19 | Marco Alexandre Cravo Gomes, Gabriel Falcão Paiva Fernandes, João Gonçalves, Vítor Manuel Mendes da Silva, Miguel Falcão, Pedro Faia |
HDL Library of Processing Units for Generic and DVB-S2 LDPC Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMAP ![In: SIGMAP 2006 - Proceedings of the International Conference on Signal Processing and Multimedia Applications, Setúbal, Portugal, August 7-10, 2006, SIGMAP is part of ICETE - The International Joint Conference on e-Business and Telecommunications, pp. 17-24, 2006, INSTICC Press, 972-8865-64-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
19 | Manfred Mücke, Guido Hafeli |
A Bitwidth-aware HDL Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2006, September 19-22, 2006, Darmstadt, Germany, Proceedings, pp. 151-153, 2006, ECSI, 978-3-00-019710-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
19 | D. Guihal, L. Andrieux |
VHDL-AMS Model Generation from Other HDL Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2006, September 19-22, 2006, Darmstadt, Germany, Proceedings, pp. 77-83, 2006, ECSI, 978-3-00-019710-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
19 | Jen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham |
HDL Program Slicing to Reduce Bounded Model Checking Search Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-7, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Mile K. Stojcev |
Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 45(7-8), pp. 1272, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton |
Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 290-291, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Tun Li, Yang Guo 0003, Sikun Li |
Automatic Circuit Extractor for HDL Description Using Program Slicing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 19(5), pp. 718-728, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Jean-Pierre David, Etienne Bergeron |
An Intermediate Level HDL for System Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2004, September 14-17, 2004, Lille, France, Proceedings, pp. 526-536, 2004, ECSI. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
19 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali |
A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA/VLSI ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA, pp. 582-588, 2004, CSREA Press, 1-932415-41-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
19 | R. Pelliconi, Fabio Campi, L. Salsa, Claudio Mucci, S. Macchiavelli |
An in-circuit debug environment for multiprocessor SOCs based on a HDL RISC soft-core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2004 International Symposium on System-on-Chip, Tampere, Finland, November 16-18, 2004, pp. 193-196, 2004, IEEE, 0-7803-8558-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Che-Hua Shih, Jing-Yang Jou |
An efficient approach for error diagnosis in HDL design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 732-735, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali |
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 485-492, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Klaus-Jürgen Englert, Bernd Becker 0001, Rolf Drechsler |
Symbolic Simulation of Algorithms Specified in HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Tübingen, Germany, February 25-27, 2002, pp. 113-122, 2002, Shaker. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
19 | Jordan Dimitriov |
Developing semantics of Verilog HDL in formal compositional design of mixed hardware/software systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2002 |
RDF |
|
19 | Veselko Gustin |
Designing the microprocessor with Abel-HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Appl. Eng. Educ. ![In: Comput. Appl. Eng. Educ. 9(2), pp. 87-92, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Vanco B. Litovski, Dejan M. Maksimovic, Zeljko Mrcarica |
Mixed-signal modeling with AleC++: Specific features of the HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Simul. Pract. Theory ![In: Simul. Pract. Theory 8(6-7), pp. 433-449, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Anna Labbé, Philippe Poure, Fabrice Aubépart, Francis Braun |
HDL software development and hardware prototyping of a system-on-chip for an active filter controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 895-898, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Satnam Singh, Philip James-Roxby |
Lava and JBits: From HDL to Bitstream in Seconds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001, Rohnert Park, California, USA, April 29 - May 2, 2001, pp. 91-100, 2001, IEEE Computer Society, 0-7695-2667-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Tsutomu Maruyama |
An Approach for Automatic Data Allocation in C to HDL Compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001, Rohnert Park, California, USA, April 29 - May 2, 2001, pp. 255-256, 2001, IEEE Computer Society, 0-7695-2667-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Rajesh K. Gupta 0001, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont |
Panel: The Next HDL: If C++ is the Answer, What was the Question? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 71-72, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Michiel M. Ligthart, Karl Fant, Ross Smith, Alexander Taubin, Alex Kondratyev |
Asynchronous Design Using Commercial HDL Synthesis Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 114-, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Tsutomu Maruyama, Tsutomu Hoshino |
A C to HDL Compiler for Pipeline Processing on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 101-112, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Qiushuang Zhang, Ian G. Harris |
A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000, pp. 369-372, 2000, IEEE Computer Society, 0-7803-6448-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai, Hsing-Ming Juan |
A novel approach for functional coverage measurement in HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 217-220, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | I. Martínez, Pierre Delatte, Denis Flandre |
Characterization, Simulation and Modeling of PLL under Irradiation Using HDL-A. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMAS ![In: 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, BMAS 2000, Orlando, Florida, USA, 18-20 October 2000, pp. 57-61, 2000, IEEE Computer Society, 0-7695-0893-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | David Cabanis |
Application of object-orientation to HDL-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2000 |
RDF |
|
19 | R. Bruce Maunder, Zoran A. Salcic, George G. Coghill |
High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 9th International Workshop, FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings, pp. 377-384, 1999, Springer, 3-540-66457-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Gaetano Palumbo, Davide Torrisi, Riccardo Ursino |
A general HDL-A model of a DC-DC switching regulator core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, pp. 1663-1666, 1999, IEEE, 0-7803-5682-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Gregor Polansek, Andrej Zemva, Andrej Trost |
HW/SW Co-Simulation of Target C++ Applications and Synthesizable HDL with Performance Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1468-1471, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Farzan Fallah, Pranav Ashar, Srinivas Devadas |
Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 666-671, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Wei-Hsing Huang, Chin-Long Wey |
ATPRG: an automatic test program generator using HDL-A for fault diagnosis of analog/mixed-signal integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 47(2), pp. 426-431, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Jian Li 0061, Rajesh K. Gupta 0001 |
HDL code restructuring using timed decision tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Sixth International Workshop on Hardware/Software Codesign, CODES 1998, Seattle, Washington, USA, March 15-18, 1998, pp. 131-135, 1998, IEEE Computer Society, 0-8186-8442-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Peter Bellows, Brad L. Hutchings |
JHDL - An HDL for Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 175-184, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Rainer Leupers |
HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 11th International Symposium on System Synthesis, ISSS '98, Hsinchu, Taiwan, December 2-4, 1998., pp. 51-, 1998, ACM / IEEE Computer Society, 0-8186-8623-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Y. Yamaguchi, Kanemitsu Ootsu, Takanobu Baba |
A Cost and Performance Comparison for Wormhole Routers based on HDL Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: International Conference on Parallel and Distributed Systems, ICPADS '98, Tainan, Taiwan, December 14-16, 1998, pp. 375-382, 1998, IEEE Computer Society, 0-8186-8603-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Daniel C. Hyde |
Using verilog HDL to teach computer architecture concepts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@ISCA ![In: Proceedings of the 1998 workshop on Computer architecture education, WCAE@ISCA 1998, Barcelona, Spain, June 1998, pp. 10, 1998, ACM, 978-1-4503-4736-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Yutaka Maeda, Toshiki Tada, Yakichi Tanaka |
HDL Design of Pulse Density Neural Network Using Simultaneous Perturbation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP ![In: The Fifth International Conference on Neural Information Processing, ICONIP'R98, Kitakyushu, Japan, October 21-23, 1998, Proceedings, pp. 81-84, 1998, IOA Press. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP BibTeX RDF |
|
19 | Gordon G. Pace |
Hardware design based on Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1998 |
RDF |
|
19 | Yoshiyuki Ito, Yuichi Nakamura 0002 |
A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997, pp. 377-382, 1997, IEEE, 0-7803-3663-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | R. Bruce Maunder, Zoran A. Salcic, George G. Coghill |
FPLD HDL synthesis employing high-level evolutionary algorithm optimisation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings, pp. 265-273, 1997, Springer, 3-540-63465-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin |
Preserving HDL synthesis hierarchy for cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997, pp. 169-174, 1997, ACM, 0-89791-927-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | K. C. Chang 0001 |
Including HDL and synthesis in the EE and CSE digital design curriculum. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 1997 IEEE International Conference on Microelectronic Systems Education, MSE '97, Arlington, VA, USA, July 21-23, 1997, pp. 125-126, 1997, IEEE Computer Society, 0-8186-7996-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Masaharu Imai, Eugenio Villar |
ASPDAC 1995: HDL synthesizability and interoperability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 13(1), pp. 3-4, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP BibTeX RDF |
|
19 | Mona M. Ahmed, Hani F. Ragaie, Hisham Haddara |
A hierarchical approach to analog behavioral modeling of neural networks using HDL-A. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 2-9, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | T. Murayama, Yuji Gendai |
A top down mixed-signal design methodology using a mixed-signal simulator and analog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 59-64, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Claus Mayer, Jörg Pleickhardt, Hans Sahm |
A graphical data management system for HDL-based ASIC design projects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 92-97, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman M. Wahba |
HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, First International Conference, FMCAD '96, Palo Alto, California, USA, November 6-8, 1996, Proceedings, pp. 450-467, 1996, Springer, 3-540-61937-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Sudhir Aggarwal |
An Enhanced Macromodel for a CMOS Operational Amplifier for HDL Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 331-332, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VHDL-Analog, Non-linear model, Analog IC's, Operational Amplifier, Macromodel |
19 | Jian Li 0061, Rajesh K. Gupta 0001 |
HDL Optimization Using Timed Decision Tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 51-54, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Ulrich Golze |
VLSI-Entwurf eines RISC-Prozessors - eine Einführung in das Design großer Chips und die Hardware-Beschreibungssprache VERILOG HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1995 |
RDF |
|
19 | Michael J. C. Gordon |
The Semantic Challenge of Verilog HDL ![Search on Bibsonomy](Pics/bibsonomy.png) |
LICS ![In: Proceedings, 10th Annual IEEE Symposium on Logic in Computer Science, San Diego, California, USA, June 26-29, 1995, pp. 136-145, 1995, IEEE Computer Society, 0-8186-7050-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Masaharu Imai, Eugenio Villar |
Future direction of synthesizability and interoperability of HDL's: part 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995, 1995, ACM, 0-89791-766-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Eugenio Villar, Masaharu Imai |
Future direction of synthesizabilty and interoperability of HDL's: part 2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995, 1995, ACM, 0-89791-766-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Carol A. Fields |
The Proper Use of Hierarchy in HDL-Based High Density FPGA Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 5th International Workshop, FPL '95, Oxford, UK, August 29 - September 1, 1995, Proceedings, pp. 168-177, 1995, Springer, 3-540-60294-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Carol A. Fields |
Creating hierarchy in HDL-based high density FGPA design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995, pp. 594-599, 1995, IEEE Computer Society, 0-8186-7156-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Richard J. Boulton |
A Restricted Form on Higher-Order Rewriting Applied to an HDL Semantics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTA ![In: Rewriting Techniques and Applications, 6th International Conference, RTA-95, Kaiserslautern, Germany, April 5-7, 1995, Proceedings, pp. 309-323, 1995, Springer, 3-540-59200-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | David Knapp, Tai Ly, Don MacMillen, Ron Miller |
Behavioral Synthesis Methodology for HDL-Based Specification and Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995., pp. 286-291, 1995, ACM Press, 0-89791-725-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | I. Hoting, M. Blettner, D. Brunner, J. Wahrendorf, G. Schettler |
Prospektive Kohortenstudie in Israel zur Krebsmortalität in Abhängigkeit vom HDL-Status. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GMDS ![In: Medizin und Information, 39. Jahrestagung der GMDS, Dresden, September 1994, pp. 572-575, 1994, MMV Medizin Verlag. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
19 | Hans Eveking |
(V)HDL-based verification of heterogeneous synchronous/asynchronous systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble, France, September 19-22, 1994, pp. 566-571, 1994, IEEE Computer Society, 0-89791-685-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
VHDL |
19 | Dundar Dumlugol, Don Webber, Rajeev Madhavan |
Analog Modeling Using Event-Driven HDL's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 53-56, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Roger P. Ang, Nikil D. Dutt |
A Representation for the Binding of RT-Component Functionality to HDL Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHDL ![In: Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993, pp. 263-280, 1993, North-Holland, 0-444-81641-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|