Search results for "HDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Francesca Palumbo, Nicola Carta, Luigi Raffo	The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer.	DASIP	2011	DBLP DOI BibTeX RDF
19	José Augusto Miranda Nacif, Thiago S. F. Silva, Luiz Filipe M. Vieira, Alex Borges Vieira, Antônio Otávio Fernandes, Claudionor Nunes Coelho	A cache based algorithm to predict HDL modules faults.	LATW	2011	DBLP DOI BibTeX RDF
19	Craig L. Glennie, Derek D. Lichti	Static Calibration and Analysis of the Velodyne HDL-64E S2 for High Accuracy Mobile Scanning.	Remote. Sens.	2010	DBLP DOI BibTeX RDF
19	Danilo Pani, Francesca Palumbo, Luigi Raffo	A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations.	Int. J. High Perform. Syst. Archit.	2010	DBLP DOI BibTeX RDF
19	Nicola Bombieri, Giuseppe Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli	HIFSuite: Tools for HDL Code Conversion and Manipulation.	EURASIP J. Embed. Syst.	2010	DBLP DOI BibTeX RDF
19	Mehran Massoumi, Assim Sagahyroon	ASIC verification: Integrating formal verification with HDL-based courses.	Comput. Appl. Eng. Educ.	2010	DBLP DOI BibTeX RDF
19	Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes	Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL.	UKSim	2010	DBLP DOI BibTeX RDF
19	Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi	A mixed HDL/PLI test package.	EWDTS	2010	DBLP DOI BibTeX RDF
19	Vladimir Hahanov, Irina V. Hahanova, Ngene Christopher Umerah, Tiecoura Yves	Testing and verification of HDL-models for SoC components.	EWDTS	2010	DBLP DOI BibTeX RDF
19	Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi	Virtual tester development using HDL/PLI.	EWDTS	2010	DBLP DOI BibTeX RDF
19	Nicola Bombieri, Giuseppe Di Guglielmo, Luigi Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli	HIFSuite: Tools for HDL code conversion and manipulation.	HLDVT	2010	DBLP DOI BibTeX RDF
19	M. H. Haghbayan, Sara Karamati, Fatemeh Javaheri, Zainalabedin Navabi	Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
19	Vladimir Zdraveski, Milos Jovanovik, Riste Stojanov, Dimitar Trajanov	HDL IP Cores Search Engine Based on Semantic Web Technologies.	ICT Innovations	2010	DBLP DOI BibTeX RDF
19	Alessandro Cilardo, Paolo Durante, Carmelo Lofiego, Antonino Mazzeo	Early Prediction of Hardware Complexity in HLL-to-HDL Translation.	FPL	2010	DBLP DOI BibTeX RDF
19	Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon	Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research.	FCCM	2010	DBLP DOI BibTeX RDF
19	Thomas Marconi, Dimitris Theodoropoulos, Koen Bertels, Georgi Gaydadjiev	A novel HDL coding style to reduce power consumption for reconfigurable devices.	FPT	2010	DBLP DOI BibTeX RDF
19	K. Dhanumjaya, G. Kiran Kumar, M. N. Giriprasad, M. Raja Reddy	Design and Modeling of Power Efficient, High Performance 32-bit ALU through Advanced HDL Synthesis.	ICT	2010	DBLP DOI BibTeX RDF
19	J. Dhore, A. P. Thakare	Implementation of AES encoder using active-HDL.	ICWET	2010	DBLP DOI BibTeX RDF
19	Adam Duley, Chris Spandikow, Miryung Kim	A program differencing algorithm for verilog HDL.	ASE	2010	DBLP DOI BibTeX RDF
19	Terence Chan	Race logic synthesis for a multithreaded HDL/ESL simulator for SoC designs.	APCCAS	2010	DBLP DOI BibTeX RDF
19	Frank Winkler 0001, Gerald Kell, Oliver Schrape, Hans Gustat, Ulrich Jagdhold	HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken.	MBMV	2009	DBLP BibTeX RDF
19	Yaseen Zaidi, Christoph Grimm 0001, Jan Haase 0001	Fast and unified SystemC AMS - HDL simulation.	FDL	2009	DBLP BibTeX RDF
19	Grzegorz Janczyk, Tomasz Bieniek	The HDL and FE Thermal Modeling of Heterogeneous Systems.	DDECS	2008	DBLP DOI BibTeX RDF
19	Wesley Holland, Yoginder S. Dandass	Optimizing Pipelining in HDL Generated Automatically from C Source Codes.	ERSA	2008	DBLP BibTeX RDF
19	Ahmed El Oualkadi, Denis Flandre	Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications.	ISVLSI	2008	DBLP DOI BibTeX RDF
19	Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi	Utilizing HDL simulation engines for accelerating design and test processes.	EWDTS	2008	DBLP DOI BibTeX RDF
19	Mohammad Shokrollah-Shirazi, Seyed Ghassem Miremadi	FPGA-Based Fault Injection into Synthesizable Verilog HDL Models.	SSIRI	2008	DBLP DOI BibTeX RDF
19	Jeongwoo Park, Bongchun Lee, Kyu-sam Lim, Jeong Hun Kim, Suki Kim, Kwang-Hyun Baek	Co-simulation of SystemC TLM with RTL HDL for surveillance camera system verification.	ICECS	2008	DBLP DOI BibTeX RDF
19	Azam Beg	An Efficient Realization of an OCR System Using HDL.	IC-AI	2008	DBLP BibTeX RDF
19	Khalil Arshak, Essa Jafer, Declan McDonagh, Christian Ibala	Modelling and simulation of wireless sensor system for health monitoring using HDL and Simulinkw mixed environment.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
19	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	Observability Analysis on HDL Descriptions for Effective Functional Validation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
19	Joseph Buck, Dong Wang, Yunshan Zhu	Formal model construction using HDL simulation semantics.	HLDVT	2007	DBLP DOI BibTeX RDF
19	Mahshid Sedghi, Armin Alaghi, Elnaz Koopahi, Zainalabedin Navabi	An HDL-Based Platform for High Level NoC Switch Testing.	ATS	2007	DBLP DOI BibTeX RDF
19	Uljana Reinsalu, Anton Arhipov, Teet Evartson, Peeter Ellervee	HDL-s for Students with Different Background.	MSE	2007	DBLP DOI BibTeX RDF
19	Adam Milik, Andrzej Pulka	Common HDL-Matlab Simulation Environment.	FDL	2007	DBLP BibTeX RDF
19	Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler	Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL.	ISMVL	2007	DBLP DOI BibTeX RDF
19	Yana Yankova, Koen Bertels, Stamatis Vassiliadis, Roel Meeuws, Arcilio Virginia	Automated HDL Generation: Comparative Evaluation.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Min-Chuan Lin, Guo-Ruey Tsai, Chun-Rong Wu, Ching-Hui Lin	Watermarking Technique for HDL-based IP Module Protection.	IIH-MSP	2007	DBLP DOI BibTeX RDF
19	Robert B. Reese, Mitchell A. Thornton	Introduction to Logic Synthesis using Verilog HDL		2006	DOI RDF
19	Marco Alexandre Cravo Gomes, Gabriel Falcão Paiva Fernandes, João Gonçalves, Vítor Manuel Mendes da Silva, Miguel Falcão, Pedro Faia	HDL Library of Processing Units for Generic and DVB-S2 LDPC Decoding.	SIGMAP	2006	DBLP BibTeX RDF
19	Manfred Mücke, Guido Hafeli	A Bitwidth-aware HDL Extension.	FDL	2006	DBLP BibTeX RDF
19	D. Guihal, L. Andrieux	VHDL-AMS Model Generation from Other HDL Language.	FDL	2006	DBLP BibTeX RDF
19	Jen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham	HDL Program Slicing to Reduce Bounded Model Checking Search Overhead.	ITC	2006	DBLP DOI BibTeX RDF
19	Mile K. Stojcev	Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
19	Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton	Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator.	ISVLSI	2005	DBLP DOI BibTeX RDF
19	Tun Li, Yang Guo 0003, Sikun Li	Automatic Circuit Extractor for HDL Description Using Program Slicing.	J. Comput. Sci. Technol.	2004	DBLP DOI BibTeX RDF
19	Jean-Pierre David, Etienne Bergeron	An Intermediate Level HDL for System Level Design.	FDL	2004	DBLP BibTeX RDF
19	Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali	A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models.	ESA/VLSI	2004	DBLP BibTeX RDF
19	R. Pelliconi, Fabio Campi, L. Salsa, Claudio Mucci, S. Macchiavelli	An in-circuit debug environment for multiprocessor SOCs based on a HDL RISC soft-core.	SoC	2004	DBLP DOI BibTeX RDF
19	Che-Hua Shih, Jing-Yang Jou	An efficient approach for error diagnosis in HDL design.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
19	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models.	DFT	2003	DBLP DOI BibTeX RDF
19	Klaus-Jürgen Englert, Bernd Becker 0001, Rolf Drechsler	Symbolic Simulation of Algorithms Specified in HDL.	MBMV	2002	DBLP BibTeX RDF
19	Jordan Dimitriov	Developing semantics of Verilog HDL in formal compositional design of mixed hardware/software systems.		2002	RDF
19	Veselko Gustin	Designing the microprocessor with Abel-HDL.	Comput. Appl. Eng. Educ.	2001	DBLP DOI BibTeX RDF
19	Vanco B. Litovski, Dejan M. Maksimovic, Zeljko Mrcarica	Mixed-signal modeling with AleC++: Specific features of the HDL.	Simul. Pract. Theory	2001	DBLP DOI BibTeX RDF
19	Anna Labbé, Philippe Poure, Fabrice Aubépart, Francis Braun	HDL software development and hardware prototyping of a system-on-chip for an active filter controller.	ICECS	2001	DBLP DOI BibTeX RDF
19	Satnam Singh, Philip James-Roxby	Lava and JBits: From HDL to Bitstream in Seconds.	FCCM	2001	DBLP DOI BibTeX RDF
19	Tsutomu Maruyama	An Approach for Automatic Data Allocation in C to HDL Compilers.	FCCM	2001	DBLP DOI BibTeX RDF
19	Rajesh K. Gupta 0001, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont	Panel: The Next HDL: If C++ is the Answer, What was the Question?	DAC	2001	DBLP DOI BibTeX RDF
19	Michiel M. Ligthart, Karl Fant, Ross Smith, Alexander Taubin, Alex Kondratyev	Asynchronous Design Using Commercial HDL Synthesis Tools.	ASYNC	2000	DBLP DOI BibTeX RDF
19	Tsutomu Maruyama, Tsutomu Hoshino	A C to HDL Compiler for Pipeline Processing on FPGAs.	FCCM	2000	DBLP DOI BibTeX RDF
19	Qiushuang Zhang, Ian G. Harris	A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions.	ICCAD	2000	DBLP DOI BibTeX RDF
19	Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai, Hsing-Ming Juan	A novel approach for functional coverage measurement in HDL.	ISCAS	2000	DBLP DOI BibTeX RDF
19	I. Martínez, Pierre Delatte, Denis Flandre	Characterization, Simulation and Modeling of PLL under Irradiation Using HDL-A.	BMAS	2000	DBLP DOI BibTeX RDF
19	David Cabanis	Application of object-orientation to HDL-based designs.		2000	RDF
19	R. Bruce Maunder, Zoran A. Salcic, George G. Coghill	High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules.	FPL	1999	DBLP DOI BibTeX RDF
19	Gaetano Palumbo, Davide Torrisi, Riccardo Ursino	A general HDL-A model of a DC-DC switching regulator core.	ICECS	1999	DBLP DOI BibTeX RDF
19	Gregor Polansek, Andrej Zemva, Andrej Trost	HW/SW Co-Simulation of Target C++ Applications and Synthesizable HDL with Performance Estimation.	EUROMICRO	1999	DBLP DOI BibTeX RDF
19	Farzan Fallah, Pranav Ashar, Srinivas Devadas	Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage.	DAC	1999	DBLP DOI BibTeX RDF
19	Wei-Hsing Huang, Chin-Long Wey	ATPRG: an automatic test program generator using HDL-A for fault diagnosis of analog/mixed-signal integrated circuits.	IEEE Trans. Instrum. Meas.	1998	DBLP DOI BibTeX RDF
19	Jian Li 0061, Rajesh K. Gupta 0001	HDL code restructuring using timed decision tables.	CODES	1998	DBLP DOI BibTeX RDF
19	Peter Bellows, Brad L. Hutchings	JHDL - An HDL for Reconfigurable Systems.	FCCM	1998	DBLP DOI BibTeX RDF
19	Rainer Leupers	HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation.	ISSS	1998	DBLP DOI BibTeX RDF
19	Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Y. Yamaguchi, Kanemitsu Ootsu, Takanobu Baba	A Cost and Performance Comparison for Wormhole Routers based on HDL Designs.	ICPADS	1998	DBLP DOI BibTeX RDF
19	Daniel C. Hyde	Using verilog HDL to teach computer architecture concepts.	WCAE@ISCA	1998	DBLP DOI BibTeX RDF
19	Yutaka Maeda, Toshiki Tada, Yakichi Tanaka	HDL Design of Pulse Density Neural Network Using Simultaneous Perturbation.	ICONIP	1998	DBLP BibTeX RDF
19	Gordon G. Pace	Hardware design based on Verilog HDL.		1998	RDF
19	Yoshiyuki Ito, Yuichi Nakamura 0002	A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface.	ASP-DAC	1997	DBLP DOI BibTeX RDF
19	R. Bruce Maunder, Zoran A. Salcic, George G. Coghill	FPLD HDL synthesis employing high-level evolutionary algorithm optimisation.	FPL	1997	DBLP DOI BibTeX RDF
19	Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin	Preserving HDL synthesis hierarchy for cell placement.	ISPD	1997	DBLP DOI BibTeX RDF
19	K. C. Chang 0001	Including HDL and synthesis in the EE and CSE digital design curriculum.	MSE	1997	DBLP DOI BibTeX RDF
19	Masaharu Imai, Eugenio Villar	ASPDAC 1995: HDL synthesizability and interoperability.	IEEE Des. Test Comput.	1996	DBLP BibTeX RDF
19	Mona M. Ahmed, Hani F. Ragaie, Hisham Haddara	A hierarchical approach to analog behavioral modeling of neural networks using HDL-A.	EURO-DAC	1996	DBLP DOI BibTeX RDF
19	T. Murayama, Yuji Gendai	A top down mixed-signal design methodology using a mixed-signal simulator and analog HDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
19	Claus Mayer, Jörg Pleickhardt, Hans Sahm	A graphical data management system for HDL-based ASIC design projects.	EURO-DAC	1996	DBLP DOI BibTeX RDF
19	Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman M. Wahba	HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment.	FMCAD	1996	DBLP DOI BibTeX RDF
19	Sudhir Aggarwal	An Enhanced Macromodel for a CMOS Operational Amplifier for HDL Implementation.	VLSI Design	1996	DBLP DOI BibTeX RDF	VHDL-Analog, Non-linear model, Analog IC's, Operational Amplifier, Macromodel
19	Jian Li 0061, Rajesh K. Gupta 0001	HDL Optimization Using Timed Decision Tables.	DAC	1996	DBLP DOI BibTeX RDF
19	Ulrich Golze	VLSI-Entwurf eines RISC-Prozessors - eine Einführung in das Design großer Chips und die Hardware-Beschreibungssprache VERILOG HDL.		1995	RDF
19	Michael J. C. Gordon	The Semantic Challenge of Verilog HDL	LICS	1995	DBLP DOI BibTeX RDF
19	Masaharu Imai, Eugenio Villar	Future direction of synthesizability and interoperability of HDL's: part 1.	ASP-DAC	1995	DBLP DOI BibTeX RDF
19	Eugenio Villar, Masaharu Imai	Future direction of synthesizabilty and interoperability of HDL's: part 2.	ASP-DAC	1995	DBLP DOI BibTeX RDF
19	Carol A. Fields	The Proper Use of Hierarchy in HDL-Based High Density FPGA Design.	FPL	1995	DBLP DOI BibTeX RDF
19	Carol A. Fields	Creating hierarchy in HDL-based high density FGPA design.	EURO-DAC	1995	DBLP DOI BibTeX RDF
19	Richard J. Boulton	A Restricted Form on Higher-Order Rewriting Applied to an HDL Semantics.	RTA	1995	DBLP DOI BibTeX RDF
19	David Knapp, Tai Ly, Don MacMillen, Ron Miller	Behavioral Synthesis Methodology for HDL-Based Specification and Validation.	DAC	1995	DBLP DOI BibTeX RDF
19	I. Hoting, M. Blettner, D. Brunner, J. Wahrendorf, G. Schettler	Prospektive Kohortenstudie in Israel zur Krebsmortalität in Abhängigkeit vom HDL-Status.	GMDS	1994	DBLP BibTeX RDF
19	Hans Eveking	(V)HDL-based verification of heterogeneous synchronous/asynchronous systems.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
19	Dundar Dumlugol, Don Webber, Rajeev Madhavan	Analog Modeling Using Event-Driven HDL's.	VLSI Design	1994	DBLP DOI BibTeX RDF
19	Roger P. Ang, Nikil D. Dutt	A Representation for the Binding of RT-Component Functionality to HDL Behavior.	CHDL	1993	DBLP BibTeX RDF