Search results for "LUT"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Bjoern Driemeyer, Julian Spiess, John G. Kauffman, Maurits Ortmanns	Complexity Reduced LUT-Based DAC Correction in Continuous-Time Delta-Sigma Modulators.	ISCAS	2022	DBLP DOI BibTeX RDF
17	Xiaole Cui, Fan Liu, Sunrui Zhang, Xiaoxin Cui	An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells.	ISCAS	2022	DBLP DOI BibTeX RDF
17	Zeeshan Ali, Pallavi Paliwal, Rupesh Lad, Dhanraj Bhukya, Shalabh Gupta	A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM.	ISCAS	2022	DBLP DOI BibTeX RDF
17	Jakub Slowik, Gregory Williams, Rummah Albashir, Anthony Samagio, Geraldine Shirley Nicholas, Fareena Saqib	Dynamic Key Updates for LUT Locked Design.	HOST	2022	DBLP DOI BibTeX RDF
17	Lingjuan Wu, Xuelin Zhang, Siyi Wang, Wei Hu 0008	Hardware Trojan Detection at LUT: Where Structural Features Meet Behavioral Characteristics.	HOST	2022	DBLP DOI BibTeX RDF
17	Revathi Pogiri, Samit Ari, K. K. Mahapatra	Design and FPGA Implementation of the LUT based Sigmoid Function for DNN Applications.	iSES	2022	DBLP DOI BibTeX RDF
17	Da Won Kim, Dalta Imam Maulana, Wanyeong Jung	Kyber Accelerator on FPGA Using Energy-Efficient LUT-Based Barrett Reduction.	ISOCC	2022	DBLP DOI BibTeX RDF
17	Xiang Zhang, Chengzhe Lu, Dawei Yan, Wei Dong, Qingsen Yan	DualBLN: Dual Branch LUT-Aware Network for Real-Time Image Retouching.	ACCV (3)	2022	DBLP DOI BibTeX RDF
17	Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh	Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees.	VDAT	2022	DBLP DOI BibTeX RDF
17	Anishetti Venkatesh, Chandan Kumar Jha 0001, G. U. Vinod, Masahiro Fujita, Virendra Singh	Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound.	VDAT	2022	DBLP DOI BibTeX RDF
17	Hongyang Hu, Zi Wang, Xiaoxin Xu, Kai Xi, Kun Zhang, Junyu Zhang, Chunmeng Dou	A 55nm 32Mb Digital Flash CIM Using Compressed LUT Multiplier and Low Power WL Voltage Trimming Scheme for AI Edge Inference.	APCCAS	2022	DBLP DOI BibTeX RDF
17	Ming Liu 0022, Yifan He, Hailong Jiao	An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator.	APCCAS	2022	DBLP DOI BibTeX RDF
17	Gaurav Kolhe, Tyler Sheaves, Kevin Immanuel Gubbi, Tejas Kadale, Setareh Rafatirad, Sai Manoj P. D., Avesta Sasan, Hamid Mahmoodi, Houman Homayoun	Silicon validation of LUT-based logic-locked IP cores.	DAC	2022	DBLP DOI BibTeX RDF
17	Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon	Improving LUT-based optimization for ASICs.	DAC	2022	DBLP DOI BibTeX RDF
17	Joonsang Yu, Junki Park, Seongmin Park, Minsoo Kim, Sihwa Lee, Dong Hyun Lee, Jungwook Choi	NN-LUT: neural approximation of non-linear operations for efficient transformer inference.	DAC	2022	DBLP DOI BibTeX RDF
17	Bo-Yu Tseng, Brian M. Kurkoski, Philipp Mohr, Gerhard Bauch 0001	An FPGA Implementation of Two-Input LUT Based Information Bottleneck LDPC Decoders.	MOCAST	2022	DBLP DOI BibTeX RDF
17	Biting Yu, Luping Zhou, Lei Wang 0001, Wanqi Yang, Ming Yang 0014, Pierrick Bourgeat, Jurgen Fripp	SA-LuT-Nets: Learning Sample-Adaptive Intensity Lookup Tables for Brain Tumor Segmentation.	IEEE Trans. Medical Imaging	2021	DBLP DOI BibTeX RDF
17	Jinfeng Yan, Ruiming Xiao, Fenzhen Su, Jinbiao Bai, Feixue Jia	Impact of Port Construction on the Spatial Pattern of Land Use in Coastal Zones Based on CLDI and LUT Models: A Case Study of Qingdao and Yantai.	Remote. Sens.	2021	DBLP DOI BibTeX RDF
17	Mountassar Maamoun, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, Rachid Beguenane	Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization.	IET Circuits Devices Syst.	2021	DBLP DOI BibTeX RDF
17	Pablo Pascual Campo, Alberto Brihuega, Lauri Anttila, Matias Turunen, Dani Korpi, Markus Allén, Mikko Valkama	Gradient-Adaptive Spline-Interpolated LUT Methods for Low-Complexity Digital Predistortion.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
17	Hui Chen 0015, Heping Yang, Wenqing Song, Zhonghai Lu, Yuxiang Fu, Li Li 0003, Zongguang Yu	Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
17	Antonio J. Ginés, Gildas Léger, Eduardo J. Peralías	Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
17	Mohd. Tasleem Khan, Jitendra Kumar 0006, Shaik Rafi Ahamed, Juhi Faridi	Partial-LUT Designs for Low-Complexity Realization of DA-Based BLMS Adaptive Filter.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
17	Peng Gu, Xinfeng Xie, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Krishna T. Malladi, Yuan Xie 0001	DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
17	Carlo Condo	A fixed latency ORBGRAND decoder architecture with LUT-aided error-pattern scheduling.	CoRR	2021	DBLP BibTeX RDF
17	Joonsang Yu, Junki Park, Seongmin Park, Minsoo Kim, Sihwa Lee, Dong Hyun Lee, Jungwook Choi	NN-LUT: Neural Approximation of Non-Linear Operations for Efficient Transformer Inference.	CoRR	2021	DBLP BibTeX RDF
17	Jia Sun, Shuo Shi, Lunche Wang, Haiyan Li, Shaoqiang Wang, Wei Gong 0004, Torbern Tagesson	Optimizing LUT-based inversion of leaf chlorophyll from hyperspectral lidar data: Role of cost functions and regulation strategies.	Int. J. Appl. Earth Obs. Geoinformation	2021	DBLP DOI BibTeX RDF
17	Mingi Cho, Jaedong Jang, Yezee Seo, Seyeon Jeong, Soochang Chung, Taekyoung Kwon 0002	Towards bidirectional LUT-level detection of hardware Trojans.	Comput. Secur.	2021	DBLP DOI BibTeX RDF
17	Marcin Kubica, Adam Opara, Dariusz Kania	Technology Mapping for LUT-Based FPGA		2021	DOI RDF
17	Ariel Castillo, Francisco Martínez, Pedro Donoso, Leonel Gutierrez, Ricardo de la Paz Guala	VLT-LUT: Modeling the Very Long-Term Evolution of the City in 300 Years.	COMPLEX NETWORKS	2021	DBLP DOI BibTeX RDF
17	Zdenek Vasícek	Synthesis of approximate circuits for LUT-based FPGAs.	DDECS	2021	DBLP DOI BibTeX RDF
17	Sarah Azimi, Corrado De Sio, Luca Sterpone	A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor.	DATE	2021	DBLP DOI BibTeX RDF
17	Yanpeng Cao, Changjun Song, Yongming Tang	Efficient LUT-based FPGA Accelerator Design for Universal Quantized CNN Inference.	ASSE	2021	DBLP DOI BibTeX RDF
17	Jin Hee Kim, Jason Helge Anderson	Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation.	FPL	2021	DBLP DOI BibTeX RDF
17	Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon	A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs.	ISPD	2021	DBLP DOI BibTeX RDF
17	Stefano Andriani, A. Zabot, Giancarlo Calvagno, JD Vandenberg	3D-LUT Optimization for High Dynamic Range andWide Color Gamut Color Processing.	Color Imaging: Displaying, Processing, Hardcopy, and Applications	2021	DBLP DOI BibTeX RDF
17	Heping Yang, Hui Chen 0015, Yuxiang Fu, Li Li 0003	Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT.	ISOCC	2021	DBLP DOI BibTeX RDF
17	Dongsu Kim, Jongsun Park 0001	Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell.	ISOCC	2021	DBLP DOI BibTeX RDF
17	Amean Al Safi, Ali S. Al-Khayyat, Zeyad Aklah	FPGA-Based Implementation of MSPWM Utilizing 6-Input LUT for Reference Signal Generation.	CCWC	2021	DBLP DOI BibTeX RDF
17	Ruixiao Li, Hayato Yamana	Fast and Accurate Function Evaluation with LUT over Integer-Based Fully Homomorphic Encryption.	AINA (2)	2021	DBLP DOI BibTeX RDF
17	Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli	LUT-Based Optimization For ASIC Design Flow.	DAC	2021	DBLP DOI BibTeX RDF
17	Alexander Barkalov 0001, Larysa Titarenko, Kamil Mielcarek	Improving characteristics of LUT-based Mealy FSMs.	Int. J. Appl. Math. Comput. Sci.	2020	DBLP DOI BibTeX RDF
17	Thomas Miraglio, Karine Adeline, Margarita Huesca, Susan L. Ustin, Xavier Briottet	Joint Use of PROSAIL and DART for Fast LUT Building: Application to Gap Fraction and Leaf Biochemistry Estimations over Sparse Oak Stands.	Remote. Sens.	2020	DBLP DOI BibTeX RDF
17	Tuaha Nomani, Mujahid Mohsin, Zahid Pervaiz, Muhammad Shafique 0001	xUAVs: Towards Efficient Approximate Computing for UAVs - Low Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization.	IEEE Access	2020	DBLP DOI BibTeX RDF
17	Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski	Improving Characteristics of LUT-Based Moore FSMs.	IEEE Access	2020	DBLP DOI BibTeX RDF
17	Jongseok Bae, Sang-Hwa Yi, Hyungmo Koo, Sungjae Oh, Hansik Oh, Woojin Choi, Jaekyung Shin, Chan Mi Song, Keum-Cheol Hwang, Kang-Yoon Lee, Youngoo Yang	LUT-Based Focal Beamforming System Using 2-D Adaptive Sequential Searching Algorithm for Microwave Power Transfer.	IEEE Access	2020	DBLP DOI BibTeX RDF
17	Emmanuel Luján, Juan A. Zuloaga Mellino, Alejandro D. Otero, Leonardo Rey Vega, Cecilia G. Galarza, Esteban E. Mocskos	Extreme Coverage in 5G Narrowband IoT: A LUT-Based Strategy to Optimize Shared Channels.	IEEE Internet Things J.	2020	DBLP DOI BibTeX RDF
17	Ranendra Kumar Sarma, Mohd. Tasleem Khan, Rafi Ahamed Shaik, Jinti Hazarika	A Novel Time-Shared and LUT-Less Pipelined Architecture for LMS Adaptive Filter.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
17	Yasir Ali Shah, Khalid Javeed, Muhammad Imran Shehzad 0001, Shoaib Azmat	LUT-based high-speed point multiplier for Goldilocks-Curve448.	IET Comput. Digit. Tech.	2020	DBLP DOI BibTeX RDF
17	Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi	LUT Input Reordering to Reduce Aging Impact on FPGA LUTs.	IEEE Trans. Computers	2020	DBLP DOI BibTeX RDF
17	Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subramanian S. Iyer, Maryam Shojaei Baghini	A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
17	S. M. Swamynathan, V. Bhanumathi 0001	Stability Enhancing SRAM cell for low power LUT Design.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
17	A. Balamanikandan, K. Krishnamoorthi	Low area ASIC implementation of LUT-CLA-QTL architecture for cryptography applications.	Wirel. Networks	2020	DBLP DOI BibTeX RDF
17	Sanjiv K. Sinha, Hitendra Padalia, Anindita Dasgupta, Jochem Verrelst, Juan Pablo Rivera	Estimation of leaf area index using PROSAIL based LUT inversion, MLRA-GPR and empirical models: Case study of tropical deciduous forest plantation, North India.	Int. J. Appl. Earth Obs. Geoinformation	2020	DBLP DOI BibTeX RDF
17	Jun Yang, Si Yuan Yang, Zi Hao Chen, Xiu Yin Zhang	An Agile LUT-Based All-Digital Transmitter.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
17	Pouya Haghi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram	O⁴-DNN: A Hybrid DSP-LUT-Based Processing Unit With Operation Packing and Out-of-Order Execution for Efficient Realization of Convolutional Neural Networks on FPGA Devices.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
17	Stefan Nikolic 0001, Grace Zgheib, Paolo Ienne	Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing.	FPGA	2020	DBLP DOI BibTeX RDF
17	Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh	LUT-based Circuit Approximation with Targeted Error Guarantees.	ATS	2020	DBLP DOI BibTeX RDF
17	Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada	A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS.	FPL	2020	DBLP DOI BibTeX RDF
17	Yanpeng Cao, Chengcheng Wang, Yongming Tang	Explore Efficient LUT-based Architecture for Quantized Convolutional Neural Networks on FPGA.	FCCM	2020	DBLP DOI BibTeX RDF
17	Feng Wang 0046, Liren Zhu, Jiaxi Zhang 0001, Lei Li, Yang Zhang, Guojie Luo	Dual-Output LUT Merging during FPGA Technology Mapping.	ICCAD	2020	DBLP DOI BibTeX RDF
17	Aarthy Mani, Fei Li 0015, Ming Ming Wong, Luo Tao, Liwei Yang, Vishnu Paramasivam, Anh Tuan Do	Ultra-Low Leakage, High Fan-Out Neuro Connection Map with TCAM-Based LUT, Localized Priority Encoder and Decoder-Less SRAM.	ISCAS	2020	DBLP DOI BibTeX RDF
17	Joo-Sung Choi, Suk-Ju Kang, Min-Ji Lee, Jun-Young Park, Ji-Won Lee	Sequential Compression Using Efficient LUT Correlation for Display Defect Compensation.	ISOCC	2020	DBLP DOI BibTeX RDF
17	Naoto Soga, Hiroki Nakahara	Design Method for an LUT Network-Based CNN with a Sparse Local Convolution.	FPT	2020	DBLP DOI BibTeX RDF
17	Hiroshi Tajima, Teppei Tsubokawa, Yoshihiro Maeda, Norishige Fukushima	Fast Local LUT Upsampling.	VISIGRAPP (4: VISAPP)	2020	DBLP DOI BibTeX RDF
17	Nobuhiko Kikuchi, Riu Hirai	Proposal of LUT-based transmitter nonlinearity compensator with precursor compensation for Short-Reach IM/DD PAM Signalling with Tomlinson-Harashima Precoding (THP).	ECOC	2020	DBLP DOI BibTeX RDF
17	Vahid Jamshidi	NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-basedlook-up table for ultralow power and highly reliable FPGA designs.	Turkish J. Electr. Eng. Comput. Sci.	2019	DBLP DOI BibTeX RDF
17	Gai Liu, Zhiru Zhang	PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization.	ACM Trans. Reconfigurable Technol. Syst.	2019	DBLP DOI BibTeX RDF
17	Md. Mahbub Alam, Mark M. Tehranipoor, Domenic Forte	Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
17	Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski	Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
17	Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli	LUT-Based Hierarchical Reversible Logic Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
17	Emmanuel Luján, Juan A. Zuloaga Mellino, Alejandro D. Otero, Leonardo Rey Vega, Cecilia G. Galarza, Esteban E. Mocskos	Extreme coverage in 5G Narrowband IoT: a LUT-based strategy to optimize shared channels.	CoRR	2019	DBLP BibTeX RDF
17		A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping.	CoRR	2019	DBLP BibTeX RDF
17	Jun Li 0065, Xiumin Wang, Jinlong He, Chen Su, Liang Shan 0002	Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm.	Entropy	2019	DBLP DOI BibTeX RDF
17	Yixiong Yang, Xin Shi, Fang Su, Zhibo Wang 0004, Pei Yang, Huazhong Yang, Yongpan Liu	A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
17	Ilker Kalyoncu, Emre Ozeren, Abdurrahman Burak, Omer Ceylan, Yasar Gurbuz	A Phase-Calibration Method for Vector-Sum Phase Shifters Using a Self-Generated LUT.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
17	Ryuji Fuchikami, Fumio Issiki	Fast and Light-weight Binarized Neural Network Implemented in an FPGA using LUT-based Signal Processing and its Time-domain Extension for Multi-bit Processing.	ICCE-Berlin	2019	DBLP DOI BibTeX RDF
17	Liwen Wang, Takumi Takahashi, Shinsuke Ibi, Seiichi Sampei	A Study on Replica Generation Using LUT Based on Information Bottleneck for MF-GaBP in Massive MIMO Detection.	VTC Fall	2019	DBLP DOI BibTeX RDF
17	Qazi Arbab Ahmed, Tobias Wiersema, Marco Platzner	Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.	ARC	2019	DBLP DOI BibTeX RDF
17	Gaurav Kolhe, Hadi Mardani Kamali, Miklesh Naicker, Tyler David Sheaves, Hamid Mahmoodi, Sai Manoj P. D., Houman Homayoun, Setareh Rafatirad, Avesta Sasan	Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality.	ICCAD	2019	DBLP DOI BibTeX RDF
17	Sasan Zhalehpour, Jiachuan Lin, Hassan Sepehrian, Wei Shi 0007, Leslie A. Rusch	Experimental Demonstration of Reduced-Size LUT Predistortion for 256QAM SiP Transmitter.	OFC	2019	DBLP BibTeX RDF
17	Gaurav Kolhe, Sai Manoj P. D., Setareh Rafatirad, Hamid Mahmoodi, Avesta Sasan, Houman Homayoun	On Custom LUT-based Obfuscation.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
17	Tuaha Nomani, Mujahid Mohsin	A Novel Approximate Adder Design Methodology with Single LUT Delay for Fault-tolerant FPGA-based Systems.	INTELLECT	2019	DBLP DOI BibTeX RDF
17	Yuechi Yu, Tianxing Wang, Jiancheng Shi 0001, Wang Zhou 0002	A Lut-Based Method to Estimate Clear-Sky Instantaneous Land Surface Shortwave Downward Radiation and its Direct Component from Modis Data.	IGARSS	2019	DBLP DOI BibTeX RDF
17	Hiroshi Tajima, Teppei Tsubokawa, Yoshihiro Maeda, Norishige Fukushima	Local LUT Upsampling for Acceleration of Edge-preserving Filtering.	VISIGRAPP (4: VISAPP)	2019	DBLP DOI BibTeX RDF
17	Igor Lemberski, Artjoms Suponenkovs, Marina Uhanova	LUT-Oriented Asynchronous Logic Design Based on Resubstitution.	DTIS	2019	DBLP DOI BibTeX RDF
17	Hong Liu, Leibo Liu, Wenping Zhu, Qiang Li, Huiyu Mo, Shaojun Wei	L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network.	DAC	2019	DBLP DOI BibTeX RDF
17	Simone G. O. Fiori, Nicola Fioranelli	Smooth statistical modeling of bivariate non-monotonic data by a three-stage LUT neural system.	Neural Comput. Appl.	2018	DBLP DOI BibTeX RDF
17	Alexander Barkalov 0001, Larysa Titarenko, Kamil Mielcarek	Hardware Reduction for Lut-Based Mealy FSMs.	Int. J. Appl. Math. Comput. Sci.	2018	DBLP DOI BibTeX RDF
17	Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma	Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design.	Integr.	2018	DBLP DOI BibTeX RDF
17	Yuan-Gen Wang, Dongqing Xie, Brij B. Gupta	A Study on the Collusion Security of LUT-Based Client-Side Watermark Embedding.	IEEE Access	2018	DBLP DOI BibTeX RDF
17	Mariusz Wisniewski, Stanislaw Deniziak	BMB synthesis of binary functions using symbolic functional decomposition for LUT-based FPGAs.	J. Parallel Distributed Comput.	2018	DBLP DOI BibTeX RDF
17	Kejie Huang, Rong Zhao, Yong Lian 0001	Racetrack Memory based hybrid Look-Up Table (LUT) for low power reconfigurable computing.	J. Parallel Distributed Comput.	2018	DBLP DOI BibTeX RDF
17	Igor Lemberski, Artjoms Suponenkovs	Asynchronous logiс one-level LUT design based on partial acknowledgement.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
17	Sunwoong Kim, Hyuk-Jae Lee	Optimized Interpolation and Cached Data Access in LUT-Based RGB-to-RGBW Conversion.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
17	Anzhela Yu. Matrosova, Sergey Ostanin	Trojan circuits masking and debugging of combinational circuits with LUT insertion.	AQTR	2018	DBLP DOI BibTeX RDF
17	Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada	A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture.	MWSCAS	2018	DBLP DOI BibTeX RDF
17	Wenyi Feng, Jonathan W. Greene, Alan Mishchenko	Improving FPGA Performance with a S44 LUT Structure.	FPGA	2018	DBLP DOI BibTeX RDF
17	Daisuke Suzuki, Takahiro Hanyu	Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
17	Zhiming Yang 0001, Peng Sun, Yang Yu 0015, Hui Zhang, Guoyu Gao, Xiyuan Peng	Workload-aware failure prediction method for VLSI devices using an LUT based approach.	I2MTC	2018	DBLP DOI BibTeX RDF