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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 465 occurrences of 241 keywords
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Results
Found 842 publication records. Showing 835 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Bjoern Driemeyer, Julian Spiess, John G. Kauffman, Maurits Ortmanns |
Complexity Reduced LUT-Based DAC Correction in Continuous-Time Delta-Sigma Modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 16-20, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Xiaole Cui, Fan Liu, Sunrui Zhang, Xiaoxin Cui |
An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 2571-2575, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Zeeshan Ali, Pallavi Paliwal, Rupesh Lad, Dhanraj Bhukya, Shalabh Gupta |
A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 2745-2749, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Jakub Slowik, Gregory Williams, Rummah Albashir, Anthony Samagio, Geraldine Shirley Nicholas, Fareena Saqib |
Dynamic Key Updates for LUT Locked Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2022, McLean, VA, USA, June 27-30, 2022, pp. 105-108, 2022, IEEE, 978-1-6654-8532-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Lingjuan Wu, Xuelin Zhang, Siyi Wang, Wei Hu 0008 |
Hardware Trojan Detection at LUT: Where Structural Features Meet Behavioral Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2022, McLean, VA, USA, June 27-30, 2022, pp. 121-124, 2022, IEEE, 978-1-6654-8532-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Revathi Pogiri, Samit Ari, K. K. Mahapatra |
Design and FPGA Implementation of the LUT based Sigmoid Function for DNN Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2022, Warangal, India, December 18-22, 2022, pp. 410-413, 2022, IEEE, 979-8-3503-9922-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Da Won Kim, Dalta Imam Maulana, Wanyeong Jung |
Kyber Accelerator on FPGA Using Energy-Efficient LUT-Based Barrett Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022, pp. 83-84, 2022, IEEE, 978-1-6654-5971-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Xiang Zhang, Chengzhe Lu, Dawei Yan, Wei Dong, Qingsen Yan |
DualBLN: Dual Branch LUT-Aware Network for Real-Time Image Retouching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACCV (3) ![In: Computer Vision - ACCV 2022 - 16th Asian Conference on Computer Vision, Macao, China, December 4-8, 2022, Proceedings, Part III, pp. 173-189, 2022, Springer, 978-3-031-26312-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh |
Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 435-449, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Anishetti Venkatesh, Chandan Kumar Jha 0001, G. U. Vinod, Masahiro Fujita, Virendra Singh |
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 397-407, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Hongyang Hu, Zi Wang, Xiaoxin Xu, Kai Xi, Kun Zhang, Junyu Zhang, Chunmeng Dou |
A 55nm 32Mb Digital Flash CIM Using Compressed LUT Multiplier and Low Power WL Voltage Trimming Scheme for AI Edge Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022, pp. 1-5, 2022, IEEE, 978-1-6654-5073-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Ming Liu 0022, Yifan He, Hailong Jiao |
An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022, pp. 55-59, 2022, IEEE, 978-1-6654-5073-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Gaurav Kolhe, Tyler Sheaves, Kevin Immanuel Gubbi, Tejas Kadale, Setareh Rafatirad, Sai Manoj P. D., Avesta Sasan, Hamid Mahmoodi, Houman Homayoun |
Silicon validation of LUT-based logic-locked IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 1189-1194, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon |
Improving LUT-based optimization for ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 421-426, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Joonsang Yu, Junki Park, Seongmin Park, Minsoo Kim, Sihwa Lee, Dong Hyun Lee, Jungwook Choi |
NN-LUT: neural approximation of non-linear operations for efficient transformer inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 577-582, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Bo-Yu Tseng, Brian M. Kurkoski, Philipp Mohr, Gerhard Bauch 0001 |
An FPGA Implementation of Two-Input LUT Based Information Bottleneck LDPC Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 11th International Conference on Modern Circuits and Systems Technologies, MOCAST 2022, Bremen, Germany, June 8-10, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-6717-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Biting Yu, Luping Zhou, Lei Wang 0001, Wanqi Yang, Ming Yang 0014, Pierrick Bourgeat, Jurgen Fripp |
SA-LuT-Nets: Learning Sample-Adaptive Intensity Lookup Tables for Brain Tumor Segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Medical Imaging ![In: IEEE Trans. Medical Imaging 40(5), pp. 1417-1427, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Jinfeng Yan, Ruiming Xiao, Fenzhen Su, Jinbiao Bai, Feixue Jia |
Impact of Port Construction on the Spatial Pattern of Land Use in Coastal Zones Based on CLDI and LUT Models: A Case Study of Qingdao and Yantai. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Remote. Sens. ![In: Remote. Sens. 13(16), pp. 3110, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Mountassar Maamoun, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, Rachid Beguenane |
Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 15(5), pp. 475-484, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Pablo Pascual Campo, Alberto Brihuega, Lauri Anttila, Matias Turunen, Dani Korpi, Markus Allén, Mikko Valkama |
Gradient-Adaptive Spline-Interpolated LUT Methods for Low-Complexity Digital Predistortion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(1), pp. 336-349, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Hui Chen 0015, Heping Yang, Wenqing Song, Zhonghai Lu, Yuxiang Fu, Li Li 0003, Zongguang Yu |
Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(3), pp. 1231-1244, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Antonio J. Ginés, Gildas Léger, Eduardo J. Peralías |
Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(8), pp. 3197-3210, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Mohd. Tasleem Khan, Jitendra Kumar 0006, Shaik Rafi Ahamed, Juhi Faridi |
Partial-LUT Designs for Low-Complexity Realization of DA-Based BLMS Adaptive Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 68(4), pp. 1188-1192, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Peng Gu, Xinfeng Xie, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Krishna T. Malladi, Yuan Xie 0001 |
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8), pp. 1586-1599, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Carlo Condo |
A fixed latency ORBGRAND decoder architecture with LUT-aided error-pattern scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2111.08134, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
17 | Joonsang Yu, Junki Park, Seongmin Park, Minsoo Kim, Sihwa Lee, Dong Hyun Lee, Jungwook Choi |
NN-LUT: Neural Approximation of Non-Linear Operations for Efficient Transformer Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2112.02191, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
17 | Jia Sun, Shuo Shi, Lunche Wang, Haiyan Li, Shaoqiang Wang, Wei Gong 0004, Torbern Tagesson |
Optimizing LUT-based inversion of leaf chlorophyll from hyperspectral lidar data: Role of cost functions and regulation strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Appl. Earth Obs. Geoinformation ![In: Int. J. Appl. Earth Obs. Geoinformation 105, pp. 102602, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Mingi Cho, Jaedong Jang, Yezee Seo, Seyeon Jeong, Soochang Chung, Taekyoung Kwon 0002 |
Towards bidirectional LUT-level detection of hardware Trojans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Secur. ![In: Comput. Secur. 104, pp. 102223, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Marcin Kubica, Adam Opara, Dariusz Kania |
Technology Mapping for LUT-Based FPGA ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2021 |
DOI RDF |
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17 | Ariel Castillo, Francisco Martínez, Pedro Donoso, Leonel Gutierrez, Ricardo de la Paz Guala |
VLT-LUT: Modeling the Very Long-Term Evolution of the City in 300 Years. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPLEX NETWORKS ![In: Complex Networks & Their Applications X - Volume 2, Proceedings of the Tenth International Conference on Complex Networks and Their Applications COMPLEX NETWORKS 2021, Madrid, Spain, November 30 - December 2, 2021, pp. 792-803, 2021, Springer, 978-3-030-93413-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Zdenek Vasícek |
Synthesis of approximate circuits for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 17-22, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Sarah Azimi, Corrado De Sio, Luca Sterpone |
A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 252-257, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Yanpeng Cao, Changjun Song, Yongming Tang |
Efficient LUT-based FPGA Accelerator Design for Universal Quantized CNN Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASSE ![In: ASSE 2021: 2nd Asia Service Sciences and Software Engineering Conference, Macau, 24-26 February, 2021., pp. 108-115, 2021, ACM, 978-1-4503-8908-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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17 | Jin Hee Kim, Jason Helge Anderson |
Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021, pp. 334-340, 2021, IEEE, 978-1-6654-3759-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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17 | Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon |
A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: ISPD '21: International Symposium on Physical Design, Virtual Event, USA, March 22-24, 2021, pp. 135-142, 2021, ACM, 978-1-4503-8300-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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17 | Stefano Andriani, A. Zabot, Giancarlo Calvagno, JD Vandenberg |
3D-LUT Optimization for High Dynamic Range andWide Color Gamut Color Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Color Imaging: Displaying, Processing, Hardcopy, and Applications ![In: Color Imaging XXVI: Displaying, Processing, Hardcopy, and Applications, Virtual Event, January 11-28, 2021., pp. 1-7, 2021, Society for Imaging Science and Technology. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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17 | Heping Yang, Hui Chen 0015, Yuxiang Fu, Li Li 0003 |
Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 13-14, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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17 | Dongsu Kim, Jongsun Park 0001 |
Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 77-78, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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17 | Amean Al Safi, Ali S. Al-Khayyat, Zeyad Aklah |
FPGA-Based Implementation of MSPWM Utilizing 6-Input LUT for Reference Signal Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCWC ![In: 11th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2021, Las Vegas, NV, USA, January 27-30, 2021, pp. 597-602, 2021, IEEE, 978-1-6654-1490-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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17 | Ruixiao Li, Hayato Yamana |
Fast and Accurate Function Evaluation with LUT over Integer-Based Fully Homomorphic Encryption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA (2) ![In: Advanced Information Networking and Applications - Proceedings of the 35th International Conference on Advanced Information Networking and Applications (AINA-2021), Toronto, ON, Canada, 12-14 May, 2021, Volume 2, pp. 620-633, 2021, Springer, 978-3-030-75074-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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17 | Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli |
LUT-Based Optimization For ASIC Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, pp. 871-876, 2021, IEEE, 978-1-6654-3274-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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17 | Alexander Barkalov 0001, Larysa Titarenko, Kamil Mielcarek |
Improving characteristics of LUT-based Mealy FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Appl. Math. Comput. Sci. ![In: Int. J. Appl. Math. Comput. Sci. 30(4), pp. 745-759, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Thomas Miraglio, Karine Adeline, Margarita Huesca, Susan L. Ustin, Xavier Briottet |
Joint Use of PROSAIL and DART for Fast LUT Building: Application to Gap Fraction and Leaf Biochemistry Estimations over Sparse Oak Stands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Remote. Sens. ![In: Remote. Sens. 12(18), pp. 2925, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Tuaha Nomani, Mujahid Mohsin, Zahid Pervaiz, Muhammad Shafique 0001 |
xUAVs: Towards Efficient Approximate Computing for UAVs - Low Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 102982-102996, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski |
Improving Characteristics of LUT-Based Moore FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 155306-155318, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Jongseok Bae, Sang-Hwa Yi, Hyungmo Koo, Sungjae Oh, Hansik Oh, Woojin Choi, Jaekyung Shin, Chan Mi Song, Keum-Cheol Hwang, Kang-Yoon Lee, Youngoo Yang |
LUT-Based Focal Beamforming System Using 2-D Adaptive Sequential Searching Algorithm for Microwave Power Transfer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 196024-196033, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Emmanuel Luján, Juan A. Zuloaga Mellino, Alejandro D. Otero, Leonardo Rey Vega, Cecilia G. Galarza, Esteban E. Mocskos |
Extreme Coverage in 5G Narrowband IoT: A LUT-Based Strategy to Optimize Shared Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 7(3), pp. 2129-2136, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Ranendra Kumar Sarma, Mohd. Tasleem Khan, Rafi Ahamed Shaik, Jinti Hazarika |
A Novel Time-Shared and LUT-Less Pipelined Architecture for LMS Adaptive Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(1), pp. 188-197, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Yasir Ali Shah, Khalid Javeed, Muhammad Imran Shehzad 0001, Shoaib Azmat |
LUT-based high-speed point multiplier for Goldilocks-Curve448. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 14(4), pp. 149-157, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi |
LUT Input Reordering to Reduce Aging Impact on FPGA LUTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 69(10), pp. 1500-1506, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subramanian S. Iyer, Maryam Shojaei Baghini |
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(5), pp. 1073-1083, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | S. M. Swamynathan, V. Bhanumathi 0001 |
Stability Enhancing SRAM cell for low power LUT Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 96, pp. 104704, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
17 | A. Balamanikandan, K. Krishnamoorthi |
Low area ASIC implementation of LUT-CLA-QTL architecture for cryptography applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Networks ![In: Wirel. Networks 26(4), pp. 2681-2693, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Sanjiv K. Sinha, Hitendra Padalia, Anindita Dasgupta, Jochem Verrelst, Juan Pablo Rivera |
Estimation of leaf area index using PROSAIL based LUT inversion, MLRA-GPR and empirical models: Case study of tropical deciduous forest plantation, North India. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Appl. Earth Obs. Geoinformation ![In: Int. J. Appl. Earth Obs. Geoinformation 86, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Jun Yang, Si Yuan Yang, Zi Hao Chen, Xiu Yin Zhang |
An Agile LUT-Based All-Digital Transmitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. ![In: IEEE Trans. Circuits Syst. 67-I(12), pp. 5550-5560, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Pouya Haghi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram |
O⁴-DNN: A Hybrid DSP-LUT-Based Processing Unit With Operation Packing and Out-of-Order Execution for Efficient Realization of Convolutional Neural Networks on FPGA Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9), pp. 3056-3069, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Stefan Nikolic 0001, Grace Zgheib, Paolo Ienne |
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, February 23-25, 2020, pp. 150-160, 2020, ACM, 978-1-4503-7099-8. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh |
LUT-based Circuit Approximation with Targeted Error Guarantees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 29th IEEE Asian Test Symposium, ATS 2020, Penang, Malaysia, November 23-26, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-7467-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada |
A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020, pp. 323-327, 2020, IEEE, 978-1-7281-9902-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Yanpeng Cao, Chengcheng Wang, Yongming Tang |
Explore Efficient LUT-based Architecture for Quantized Convolutional Neural Networks on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020, Fayetteville, AR, USA, May 3-6, 2020, pp. 232, 2020, IEEE, 978-1-7281-5803-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Feng Wang 0046, Liren Zhu, Jiaxi Zhang 0001, Lei Li, Yang Zhang, Guojie Luo |
Dual-Output LUT Merging during FPGA Technology Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, pp. 132:1-132:9, 2020, IEEE. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Aarthy Mani, Fei Li 0015, Ming Ming Wong, Luo Tao, Liwei Yang, Vishnu Paramasivam, Anh Tuan Do |
Ultra-Low Leakage, High Fan-Out Neuro Connection Map with TCAM-Based LUT, Localized Priority Encoder and Decoder-Less SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Joo-Sung Choi, Suk-Ju Kang, Min-Ji Lee, Jun-Young Park, Ji-Won Lee |
Sequential Compression Using Efficient LUT Correlation for Display Defect Compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2020, Yeosu, South Korea, October 21-24, 2020, pp. 115-116, 2020, IEEE, 978-1-7281-8331-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
17 | Naoto Soga, Hiroki Nakahara |
Design Method for an LUT Network-Based CNN with a Sparse Local Convolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: International Conference on Field-Programmable Technology, (IC)FPT 2020, Maui, HI, USA, December 9-11, 2020, pp. 294-295, 2020, IEEE, 978-1-6654-2302-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Hiroshi Tajima, Teppei Tsubokawa, Yoshihiro Maeda, Norishige Fukushima |
Fast Local LUT Upsampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VISIGRAPP (4: VISAPP) ![In: Proceedings of the 15th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications, VISIGRAPP 2020, Volume 4: VISAPP, Valletta, Malta, February 27-29, 2020., pp. 67-75, 2020, SCITEPRESS, 978-989-758-402-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Nobuhiko Kikuchi, Riu Hirai |
Proposal of LUT-based transmitter nonlinearity compensator with precursor compensation for Short-Reach IM/DD PAM Signalling with Tomlinson-Harashima Precoding (THP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECOC ![In: European Conference on Optical Communications, ECOC 2020, Virtual Event, Belgium, December 6-10, 2020, pp. 1-3, 2020, IEEE, 978-1-7281-7361-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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17 | Vahid Jamshidi |
NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-basedlook-up table for ultralow power and highly reliable FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 27(6), pp. 4486-4501, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Gai Liu, Zhiru Zhang |
PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 11(4), pp. 23:1-23:23, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Md. Mahbub Alam, Mark M. Tehranipoor, Domenic Forte |
Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(12), pp. 2897-2910, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski |
Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(8), pp. 1950131:1-1950131:21, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli |
LUT-Based Hierarchical Reversible Logic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9), pp. 1675-1688, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Emmanuel Luján, Juan A. Zuloaga Mellino, Alejandro D. Otero, Leonardo Rey Vega, Cecilia G. Galarza, Esteban E. Mocskos |
Extreme coverage in 5G Narrowband IoT: a LUT-based strategy to optimize shared channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1908.02798, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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17 | |
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1903.11264, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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17 | Jun Li 0065, Xiumin Wang, Jinlong He, Chen Su, Liang Shan 0002 |
Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Entropy ![In: Entropy 21(8), pp. 814, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Yixiong Yang, Xin Shi, Fang Su, Zhibo Wang 0004, Pei Yang, Huazhong Yang, Yongpan Liu |
A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5), pp. 1970-1980, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Ilker Kalyoncu, Emre Ozeren, Abdurrahman Burak, Omer Ceylan, Yasar Gurbuz |
A Phase-Calibration Method for Vector-Sum Phase Shifters Using a Self-Generated LUT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4), pp. 1632-1642, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Ryuji Fuchikami, Fumio Issiki |
Fast and Light-weight Binarized Neural Network Implemented in an FPGA using LUT-based Signal Processing and its Time-domain Extension for Multi-bit Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-Berlin ![In: 9th IEEE International Conference on Consumer Electronics, ICCE-Berlin 2019, Berlin, Germany, September 8-11, 2019, pp. 120-121, 2019, IEEE, 978-1-7281-2745-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Liwen Wang, Takumi Takahashi, Shinsuke Ibi, Seiichi Sampei |
A Study on Replica Generation Using LUT Based on Information Bottleneck for MF-GaBP in Massive MIMO Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Fall ![In: 90th IEEE Vehicular Technology Conference, VTC Fall 2019, Honolulu, HI, USA, September 22-25, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1220-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Qazi Arbab Ahmed, Tobias Wiersema, Marco Platzner |
Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings, pp. 127-136, 2019, Springer, 978-3-030-17226-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Gaurav Kolhe, Hadi Mardani Kamali, Miklesh Naicker, Tyler David Sheaves, Hamid Mahmoodi, Sai Manoj P. D., Houman Homayoun, Setareh Rafatirad, Avesta Sasan |
Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019, pp. 1-8, 2019, ACM, 9781728123509. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Sasan Zhalehpour, Jiachuan Lin, Hassan Sepehrian, Wei Shi 0007, Leslie A. Rusch |
Experimental Demonstration of Reduced-Size LUT Predistortion for 256QAM SiP Transmitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2019, San Diego, CA, USA, March 3-7, 2019, pp. 1-3, 2019, IEEE, 978-1-943580-53-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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17 | Gaurav Kolhe, Sai Manoj P. D., Setareh Rafatirad, Hamid Mahmoodi, Avesta Sasan, Houman Homayoun |
On Custom LUT-based Obfuscation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019, pp. 477-482, 2019, ACM, 978-1-4503-6252-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Tuaha Nomani, Mujahid Mohsin |
A Novel Approximate Adder Design Methodology with Single LUT Delay for Fault-tolerant FPGA-based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INTELLECT ![In: Second International Conference on Latest trends in Electrical Engineering and Computing Technologies, INTELLECT 2019, Karachi, Pakistan, November 13-14, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-2435-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Yuechi Yu, Tianxing Wang, Jiancheng Shi 0001, Wang Zhou 0002 |
A Lut-Based Method to Estimate Clear-Sky Instantaneous Land Surface Shortwave Downward Radiation and its Direct Component from Modis Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IGARSS ![In: 2019 IEEE International Geoscience and Remote Sensing Symposium, IGARSS 2019, Yokohama, Japan, July 28 - August 2, 2019, pp. 1861-1864, 2019, IEEE, 978-1-5386-9154-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Hiroshi Tajima, Teppei Tsubokawa, Yoshihiro Maeda, Norishige Fukushima |
Local LUT Upsampling for Acceleration of Edge-preserving Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VISIGRAPP (4: VISAPP) ![In: Proceedings of the 14th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications, VISIGRAPP 2019, Volume 4: VISAPP, Prague, Czech Republic, February 25-27, 2019., pp. 131-138, 2019, SciTePress, 978-989-758-354-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Igor Lemberski, Artjoms Suponenkovs, Marina Uhanova |
LUT-Oriented Asynchronous Logic Design Based on Resubstitution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DTIS 2019, Mykonos, Greece, April 16-18, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-3424-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Hong Liu, Leibo Liu, Wenping Zhu, Qiang Li, Huiyu Mo, Shaojun Wei |
L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, pp. 192, 2019, ACM, 978-1-4503-6725-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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17 | Simone G. O. Fiori, Nicola Fioranelli |
Smooth statistical modeling of bivariate non-monotonic data by a three-stage LUT neural system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 30(4), pp. 1353-1368, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Alexander Barkalov 0001, Larysa Titarenko, Kamil Mielcarek |
Hardware Reduction for Lut-Based Mealy FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Appl. Math. Comput. Sci. ![In: Int. J. Appl. Math. Comput. Sci. 28(3), pp. 595-607, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma |
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 62, pp. 1-13, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Yuan-Gen Wang, Dongqing Xie, Brij B. Gupta |
A Study on the Collusion Security of LUT-Based Client-Side Watermark Embedding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 6, pp. 15816-15822, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Mariusz Wisniewski, Stanislaw Deniziak |
BMB synthesis of binary functions using symbolic functional decomposition for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 120, pp. 16-22, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Kejie Huang, Rong Zhao, Yong Lian 0001 |
Racetrack Memory based hybrid Look-Up Table (LUT) for low power reconfigurable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 117, pp. 127-137, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Igor Lemberski, Artjoms Suponenkovs |
Asynchronous logiс one-level LUT design based on partial acknowledgement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 80, pp. 53-61, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Sunwoong Kim, Hyuk-Jae Lee |
Optimized Interpolation and Cached Data Access in LUT-Based RGB-to-RGBW Conversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(7), pp. 943-947, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Anzhela Yu. Matrosova, Sergey Ostanin |
Trojan circuits masking and debugging of combinational circuits with LUT insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AQTR ![In: IEEE International Conference on Automation, Quality and Testing, Robotics, AQTR 2018, Cluj-Napoca, Romania, May 24-26, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-2205-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada |
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 408-411, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Wenyi Feng, Jonathan W. Greene, Alan Mishchenko |
Improving FPGA Performance with a S44 LUT Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018, pp. 61-66, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Daisuke Suzuki, Takahiro Hanyu |
Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018, pp. 291, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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17 | Zhiming Yang 0001, Peng Sun, Yang Yu 0015, Hui Zhang, Guoyu Gao, Xiyuan Peng |
Workload-aware failure prediction method for VLSI devices using an LUT based approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
I2MTC ![In: IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2018, Houston, TX, USA, May 14-17, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-2222-3. The full citation details ...](Pics/full.jpeg) |
2018 |
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