Search results for "PowerPC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Wei Qin, Sharad Malik	Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation.	DATE	2003	DBLP DOI BibTeX RDF
11	Pramote Kuacharoen, Vincent John Mooney, Vijay K. Madisetti	Software Streaming via Block Streaming.	DATE	2003	DBLP DOI BibTeX RDF
11	Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu	Automated Test Model Generation from Switch Level Custom Circuits.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
11	Georgi Kuzmanov, Stamatis Vassiliadis	Arbitrating Instructions in an pmu-Coded CCM.	FPL	2003	DBLP DOI BibTeX RDF
11	Antoine Colin, Stefan M. Petters	Experimental Evaluation of Code Properties for WCET Analysis.	RTSS	2003	DBLP DOI BibTeX RDF
11	Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French	A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels.	ISCA	2003	DBLP DOI BibTeX RDF
11	Henrique Madeira, Raphael R. Some, Francisco Moreira 0001, Diamantino Costa, David A. Rennels	Experimental Evaluation of a COTS System for Space Application.	DSN	2002	DBLP DOI BibTeX RDF
11	Brendon Cahoon, Kathryn S. McKinley	Simple and effective array prefetching in Java.	Java Grande	2002	DBLP DOI BibTeX RDF	array prefetching, Java, static analysis, memory optimization
11	Mark Probst, Andreas Krall, Bernhard Scholz	Register Liveness Analysis for Optimizing Dynamic Binary Translation.	WCRE	2002	DBLP DOI BibTeX RDF
11	Avishay Orpaz, Shlomo Weiss	A study of CodePack: optimizing embedded code space.	CODES	2002	DBLP DOI BibTeX RDF	codepack, optimization, embedded systems, embedded software, code compression
11	Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long	Static timing analysis based circuit-limited-yield estimation.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
11	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?	VTS	2002	DBLP DOI BibTeX RDF
11	Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina	A Wavelet-Based Timing Parameter Extraction Method.	ITC	2002	DBLP DOI BibTeX RDF
11	Ivan Dimov 0001, Aneta Karaivanova, Rayna Georgieva, Sofiya Ivanovska	Parallel Importance Separation and Adaptive Monte Carlo Algorithms for Multiple Integrals.	Numerical Methods and Application	2002	DBLP DOI BibTeX RDF
11	Simon Jolly, Atanas N. Parashkevov, Tim McDougall	Automated equivalence checking of switch level circuits .	DAC	2002	DBLP DOI BibTeX RDF	MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking
11	Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham	Design and Development Paradigm for Industrial Formal Verification CAD Tools.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
11	Pradip Bose	Ensuring Dependable Processor Performance: An Experience Report on Pre-Silicon Performance Validation.	DSN	2001	DBLP DOI BibTeX RDF
11	Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir	Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation.	CHARME	2001	DBLP DOI BibTeX RDF
11	Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir	Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.	IOLTW	2001	DBLP DOI BibTeX RDF
11	Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long	Timing Yield Estimation from Static Timing Analysis.	ISQED	2001	DBLP DOI BibTeX RDF
11	Magdy S. Abadir, Juhong Zhu, Li-C. Wang	Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor.	VTS	2001	DBLP DOI BibTeX RDF
11	Weiwu Hu, Gang Shi, Fuxin Zhang	Communication with Threads in Software DSM.	CLUSTER	2001	DBLP DOI BibTeX RDF
11	Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain	Expression-tree-based algorithms for code compression on embedded RISC architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
11	Pradip Bose	Testing for Function and Performance: Towards an Integrated Processor Validation Methodology.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	performance test cases, bounds modeling, performance validation, integrated methodology, test generation, microprocessor testing
11	Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen	A Buffer-Oriented Methodology for Microarchitecture Validation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	processor validation, superscalar microarchitecture, design validation
11	Matteo Corti 0002, Roberto Brega, Thomas R. Gross	Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems.	LCTES	2000	DBLP DOI BibTeX RDF
11	Fred G. Gustavson, Alexander Karaivanov, Minka Marinova, Jerzy Wasniewski, Plamen Y. Yalamov	A Fast Minimal Storage Symmetric Indefinite Solver.	PARA	2000	DBLP DOI BibTeX RDF
11	André Hergenhan, Wolfgang Rosenstiel	Static Timing Analysis of Embedded Software on Advanced Processor Architectures.	DATE	2000	DBLP DOI BibTeX RDF
11	David M. Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose	Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.	PACS	2000	DBLP DOI BibTeX RDF
11	Vivek Sarkar	Optimized unrolling of nested loops.	ICS	2000	DBLP DOI BibTeX RDF
11	Shervin Hojat, Paul Kartschoke	Techniques for Improving Timing Convergence of Advanced Microprocessors.	EUROMICRO	2000	DBLP DOI BibTeX RDF
11	Gary W. Maier, Shawn Smith	Electronic Process Limited Yield.	ISQED	2000	DBLP DOI BibTeX RDF
11	Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia	"Timing closure by design, " a high frequency microprocessor design methodology.	DAC	2000	DBLP DOI BibTeX RDF	chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure
11	Dawson R. Engler, Wilson C. Hsieh	Derive: a tool that automatically reverse-engineers instruction encodings.	Dynamo	2000	DBLP DOI BibTeX RDF
11	Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly	Power reduction and power-delay trade-offs using logic transformations.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	CMOS logic, low power, logic synthesis, power estimation, logic optimization
11	Jong-Deok Choi, Manish Gupta 0002, Mauricio J. Serrano, Vugranam C. Sreedhar, Samuel P. Midkiff	Escape Analysis for Java.	OOPSLA	1999	DBLP DOI BibTeX RDF	Java
11	Charles Lefurgy, Eva Piccininni, Trevor N. Mudge	Evaluation of a High Performance Code Compression Method.	MICRO	1999	DBLP DOI BibTeX RDF
11	Jon Tyler, Jeff Lent, Anh Mather, Huy Nguyen	AltiVecTM: bringing vector technology to the PowerPCTM processor family.	IPCCC	1999	DBLP DOI BibTeX RDF
11	Martin S. Schmookler, Ramesh C. Agarwal, Fred G. Gustavson	Series Approximation Methods for Divide and Square Root in the Power3(TM) Processor.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
11	Paulo Centoducatte, Ricardo Pannain, Guido Araujo	Compressed Code Execution on DSP Architectures.	ISSS	1999	DBLP DOI BibTeX RDF
11	Xin Hong, Kenneth Adamson, Weiru Liu	Using Parallel Techniques to Improve the Computational Efficiency of Evidential Combination.	ICTAI	1999	DBLP DOI BibTeX RDF	belief function combination, the local computation technique, parallelism, clustering algorithm, Reasoning under uncertainty
11	Tom Thomas, Brian W. Anthony	Area, Performance, and Yield Implications of Redundancy in On-Chip Caches.	ICCD	1999	DBLP DOI BibTeX RDF	cache, redundancy, microprocessor, yield, SRAM, yield enhancement, microprocessor design, embedded SRAM
11	Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen	Superscalar Processor Validation at the Microarchitecture Level.	VLSI Design	1999	DBLP DOI BibTeX RDF
11	Richard B. Brown, Bruce Bernhardt, M. LaMacchia, J. Abrokwah, Phiroze N. Parakh, Todd D. Basso, Spencer M. Gold, S. Stetson, Claude R. Gauthier, D. Foster, B. Crawforth, T. McQuire, Karem A. Sakallah, Ronald J. Lomax, Trevor N. Mudge	Overview of complementary GaAs technology for high-speed VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
11	Li-C. Wang, Magdy S. Abadir	Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	high-level test generation, assertion test generation, design validation, logic verification, symbolic trajectory evaluation
11	Matthias Menge	Superskalare Prozessoren.	Inform. Spektrum	1998	DBLP DOI BibTeX RDF	Scoreboarding, Reservierungseinheit, Competion-Unit, Retirement-Unit, History-Buffer, Reorder-Buffer
11	Leland L. Day, Paul A. Ganfield, Dennis M. Rickert, Fred J. Ziegler	Test methodology for a microprocessor with partial scan.	ITC	1998	DBLP DOI BibTeX RDF
11	Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela	Clock Distribution Methodology for PowerPCTM Microprocessors.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
11	Ann Marie Rincon, Cory Cherichetti, James A. Monzel, David R. Stauffer, Michael T. Trick	Core Design and System-on-a-Chip Integration.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
11	Charles Lefurgy, Peter L. Bird, I-Cheng K. Chen, Trevor N. Mudge	Improving Code Density Using Compression Techniques.	MICRO	1997	DBLP DOI BibTeX RDF	Code Space Optimization, Embedded Systems, Compression, Code Density
11	Geoff Wyvill	The Virtual Display Case.	Computer Graphics International	1997	DBLP DOI BibTeX RDF
11	Yuan C. Chou, Daniel P. Siewiorek, John Paul Shen	A Realistic Study on Multithreaded Superscalar Processor Design.	Euro-Par	1997	DBLP DOI BibTeX RDF
11	Shai Halevi, Hugo Krawczyk	MMH: Software Message Authentication in the Gbit/Second Rates.	FSE	1997	DBLP DOI BibTeX RDF
11	Kevin J. Nowka, H. Peter Hofstee	Circuits and Microarchitecture for Gigahertz VLSI Designs.	ARVLSI	1997	DBLP DOI BibTeX RDF
11	Neelakantan Sundaresan	Exploiting Delayed Synchronization Arrivals in Light-Weight Data Parallelism.	HICSS (1)	1997	DBLP DOI BibTeX RDF
11	Kemal Ebcioglu, Erik R. Altman	DAISY: Dynamic Compilation for 100% Architectural Compatibility.	ISCA	1997	DBLP DOI BibTeX RDF	object code compatible VLIW, instruction-level parallelism, superscalar, binary translation, dynamic compilation
11	Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir	Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation.	DAC	1997	DBLP DOI BibTeX RDF
11	Kyle L. Nelson, Alok Jain, Randal E. Bryant	Formal Verification of a Superscalar Execution Unit.	DAC	1997	DBLP DOI BibTeX RDF
11	Mikko H. Lipasti, John Paul Shen	Exceeding the Dataflow Limit via Value Prediction.	MICRO	1996	DBLP DOI BibTeX RDF
11	Peter Fritzson, Roland Wismüller, Olav Hansen, Jonas Sala, Peter Skov	A Parallel Debugger with Support for Distributed Arrays, Multiple Executables and Dynamic Processes.	CC	1996	DBLP DOI BibTeX RDF
11	Norman Ramsey	Relocating Machine Instructions by Currying.	PLDI	1996	DBLP DOI BibTeX RDF
11	Ali-Reza Adl-Tabatabai, Geoff Langdale, Steven Lucco, Robert Wahbe	Efficient and Language-Independent Mobile Programs.	PLDI	1996	DBLP DOI BibTeX RDF
11	Mikko H. Lipasti, Christopher B. Wilkerson, John Paul Shen	Value Locality and Load Value Prediction.	ASPLOS	1996	DBLP DOI BibTeX RDF
11	Farooq Butt	Implementing FORTRAN77 Support in the GNU gdb Debugger.	ACM SIGPLAN Notices	1995	DBLP DOI BibTeX RDF	FORTRAN, UNIX
11	Derek Chiou, Boon Seong Ang, Robert Greiner, Arvind, James C. Hoe, Michael J. Beckerle, James E. Hicks, G. Andrew Boughton	START-NG: Delivering Seamless Parallel Computing.	Euro-Par	1995	DBLP DOI BibTeX RDF
11	Mariam Kamkar, Patrik Krajina	Dynamic slicing of distributed programs.	ICSM	1995	DBLP DOI BibTeX RDF	program maintenance activities, computer supported methods, distributed dynamic dependence graph, communication dependences, distributed dynamic slicer, ANSI-C programming language, parallel MIMD computer, Parsytec GC/Powerplus, parallel programming, graph theory, software maintenance, message passing, program slicing, distributed programs, dependence analysis, program diagnostics, dynamic slicing, dynamic slice, static slice
11	Rainer Gerlich, Mladen Kerep	Distributed and Parallel Systems and HOOD 4.	Ada-Europe	1995	DBLP DOI BibTeX RDF	Distributed Systems, Software Design, Parallel Systems, HOOD, Software Partitioning