Search results for "Reconfiguration"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Fotis Foukalas, Yiorgos Ntarladimas, Aristotelis Glentis, Zachos Boufidis	Protocol Reconfiguration Using Component-Based Design.	DAIS	2005	DBLP DOI BibTeX RDF
26	Sachin Kogekar, Sandeep Neema, Xenofon D. Koutsoukos	Dynamic Software Reconfiguration in Sensor Networks.	Systems Communications	2005	DBLP DOI BibTeX RDF
26	Jing Liu, Houshang Darabi	Control reconfiguration of discrete event systems controllers with partial observation.	IEEE Trans. Syst. Man Cybern. Part B	2004	DBLP DOI BibTeX RDF
26	Elisabeth A. Strunk, John C. Knight	Assured Reconfiguration of Embedded Real-Time Software.	DSN	2004	DBLP DOI BibTeX RDF
26	Hassan Gomaa, Mohamed Hussein 0002	Software Reconfiguration Patterns for Dynamic Evolution of Software Architectures.	WICSA	2004	DBLP DOI BibTeX RDF
26	Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterjee	Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
26	Usama Malik	Minimising Reconfiguration Overheads in Embedded Applications (Abstract).	FPL	2004	DBLP DOI BibTeX RDF
26	Michael Ullmann, Michael Hübner 0001, Björn Grimm, Jürgen Becker 0001	On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.	FPL	2004	DBLP DOI BibTeX RDF
26	Erik Vonnahme, Björn Griese, Mario Porrmann, Ulrich Rückert 0001	Dynamic Reconfiguration of Real-Time Network Interfaces.	PARELEC	2004	DBLP DOI BibTeX RDF
26	Gunnar Tufte, Pauline C. Haddow	Biologically-Inspired: A Rule-Based Self-Reconfiguration of a Virtex Chip.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
26	Masaru Fukushi, Susumu Horiguchi	Reconfiguration Algorithm for Degradable Processor Arrays Based on Row and Column Rerouting.	DFT	2004	DBLP DOI BibTeX RDF
26	Asma Ben Letaifa, Zièd Choukair, Sami Tabbane	Dynamic Reconfiguration of Telecom Services Architectures According to Mobility and Traffic Models.	AINA (2)	2004	DBLP DOI BibTeX RDF
26	Nico Janssens, Sam Michiels, Tom Holvoet, Pierre Verbaeten	A Modular Approach Enforcing Safe Reconfiguration of Producer-Consumer Applications.	ICSM	2004	DBLP DOI BibTeX RDF
26	Juan Francisco Díaz, Gustavo Gutierrez, Carlos Alberto Olarte, Camilo Rueda	Using Constraint Programming for Reconfiguration of Electrical Power Distribution Networks.	MOZ	2004	DBLP DOI BibTeX RDF
26	Hassan Gomaa, Mohamed Hussein 0002	Dynamic Software Reconfiguration in Software Product Families.	PFE	2003	DBLP DOI BibTeX RDF
26	Brandon Blodget, Scott McMillan, Patrick Lysaght	A Lightweight Approach for Embedded Reconfiguration of FPGAs.	DATE	2003	DBLP DOI BibTeX RDF
26	Richard H. Turner, Roger F. Woods	Design Flow for Efficient FPGA Reconfiguration.	FPL	2003	DBLP DOI BibTeX RDF
26	Iván González, Sergio López-Buedo, Francisco J. Gómez, Javier Martínez	Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm.	FPL	2003	DBLP DOI BibTeX RDF
26	Minoru Watanabe, Fuminori Kobayashi	An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit.	IPDPS	2003	DBLP DOI BibTeX RDF
26	Daniel Mesquita, Fernando Gehm Moraes, José Palma 0002, Leandro Möller, Ney Laert Vilar Calazans	Remote and Partial Reconfiguration of FPGAs: Tools and Trends.	IPDPS	2003	DBLP DOI BibTeX RDF
26	Naveed Arshad, Dennis Heimbigner, Alexander L. Wolf	Deployment and Dynamic Reconfiguration Planning for Distributed Software Systems.	ICTAI	2003	DBLP DOI BibTeX RDF
26	Lorenzo Fernández Maimó, José M. García 0001, Rafael Casado	On Deadlock Frequency during Dynamic Reconfiguration in NOWs.	Euro-Par	2001	DBLP DOI BibTeX RDF
26	Chor Ping Low	An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Degradable VLSI/WSI arrays, efficient heuristic, NP-completeness, greedy algorithm
26	Tim Courtney, Richard H. Turner, Roger F. Woods	Multiplexer Based Reconfiguration for Virtex Multipliers.	FPL	2000	DBLP DOI BibTeX RDF
26	Scott McMillan, Steve Guccione	Partial Run-Time Reconfiguration Using JRTR.	FPL	2000	DBLP DOI BibTeX RDF
26	Kiran Bondalapati, Viktor K. Prasanna	Loop Pipelining and Optimization for Run Time Reconfiguration.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
26	Camel Tanougast, Yves Berviller, Serge Weber	Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
26	John Marty Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici	Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration.	FCCM	2000	DBLP DOI BibTeX RDF
26	Ruoming Pang, Timothy Mark Pinkston, José Duato	The Double Scheme: Deadlock-Free Dynamic Reconfiguration of Cut-Through Networks.	ICPP	2000	DBLP DOI BibTeX RDF
26	Jonathan K. Millen	Local Reconfiguration Policies.	S&P	1999	DBLP DOI BibTeX RDF
26	Noemi de La Rocque Rodriguez, Roberto Ierusalimschy	Dynamic Reconfiguration of CORBA-Based Applications.	SOFSEM	1999	DBLP DOI BibTeX RDF
26	Eshwar Belani, Ravi Mittal	A General Reconfiguration Technique for Fault Tolerant Processor Architectures.	VLSI Design	1997	DBLP DOI BibTeX RDF
26	Jagannathan Narasimham, Kazuo Nakajima, Chong S. Rim, Anton T. Dahbura	Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
26	Dimiter R. Avresky, Khalid M. Al-Tawil	Reconfiguration of Faulty Hypercubes.	EDCC	1994	DBLP DOI BibTeX RDF
26	H. Lin, Fabrizio Lombardi, Mi Lu	On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
26	Sy-Yen Kuo, Ing-Yi Chen	Efficient reconfiguration algorithms for degradable VLSI/WSI arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
26	Jung Hwan Kim, Phill-Kyu Rhee	A resource-efficient reconfiguration algorithm of VLSI 2-D processor arrays.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
26	Thomas L. Rodeheffer, Michael D. Schroeder	Automatic Reconfiguration in Autonet.	SOSP	1991	DBLP DOI BibTeX RDF	ARPANET
26	Brent Hailpern, Gail E. Kaiser	Dynamic reconfiguration in an object-based programming language with distributed shared data.	ICDCS	1991	DBLP DOI BibTeX RDF
26	Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli	An algorithm for functional reconfiguration of fixed-size arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
26	Sy-Yen Kuo, W. Kent Fuchs	Spare Allocation and Reconfiguration in Large Area VLSI.	DAC	1988	DBLP BibTeX RDF
26	Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat	TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Look-Up Table (LUT), MTJ, TAS, multi-context configuration, nonvolatile, Simulation, FPGA, architecture, low power, dynamical reconfiguration, flip-flop, MRAM
26	Åke Arvidsson, Johannes Göbel, Anthony E. Krzesinski, Peter G. Taylor	A Distributed Scheme for Value-Based Bandwidth Reconfiguration.	FITraMEn	2008	DBLP DOI BibTeX RDF	bandwidth prices, bandwidth reconfiguration, network planning and optimisation, scalability, distributed control
26	Abdel Aziz Farrag, Shituo Lou, Qi Yao	Fault-tolerance and reconfiguration of circulant graphs and hypercubes.	SpringSim	2008	DBLP DOI BibTeX RDF	fault-tolerance, networks, reconfiguration, hypercubes, circulant graphs
26	Conrado Pilotto, José Rodrigo Azambuja, Fernanda Lima Kastensmidt	Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications.	SBCCI	2008	DBLP DOI BibTeX RDF	fault tolerance, FPGA, TMR, dynamic partial reconfiguration
26	Ann Gordon-Ross, Jeremy Lau, Brad Calder	Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	cache tuning, phase prediction, phase-based reconfiguration, phase-based tuning, caches, configurable caches, configurable architecture
26	Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio	SEU mitigation for sram-based fpgas through dynamic partial reconfiguration.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault detection, SEU, partial dynamic reconfiguration
26	Michael Hübner 0001, Jürgen Becker 0001	Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration.	SBCCI	2006	DBLP DOI BibTeX RDF	designflow, dynamic and partial reconfiguration, reconfigurable hardware
26	Reza M. Rad, Mohammad Tehranipoor	A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices.	DFT	2006	DBLP DOI BibTeX RDF	Nanoscale Devices, Fault Tolerance, Test, Reconfiguration, Redundancy, Crossbar
26	Olav Lysne, Timothy Mark Pinkston, José Duato	Part II: A Methodology for Developing Deadlock-Free Dynamic Network Reconfiguration Processes.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	deadlock-freedom methodology, system reliability and availability, Interconnection network, dynamic reconfiguration
26	N. Sreenath, Prakash Ramaswamy	Virtual Topology Reconfiguration for Node Failures in Wavelength Routed Optical Networks.	ICAS/ICNS	2005	DBLP DOI BibTeX RDF	Reconfiguration, Network connectivity, Node failures, WDM optical networks, Virtual topology
26	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt	Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration.	DAC	2005	DBLP DOI BibTeX RDF	HW-SW partitioning, linear placement, partial dynamic reconfiguration
26	Matthias Pfeffer, Theo Ungerer	Dynamic Real-Time Reconfiguration on a Multithreaded Java-Microcontroller.	ISORC	2004	DBLP DOI BibTeX RDF	real-time kernels and operating systems, embedded systems, multithreading, dynamic reconfiguration, real-time Java
26	Michael Hübner 0001, Tobias Becker, Jürgen Becker 0001	Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration.	SBCCI	2004	DBLP DOI BibTeX RDF	virtex, dynamic partial reconfiguration
26	Dirk Koch, Jürgen Teich	Platform-independent methodology for partial reconfiguration.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	bitstream extraction, configuration compression, partial reconfiguration
26	Etienne Schneider, Florentin Picioroaga, Uwe Brinkschulte	Dynamic reconfiguration through OSA+, a real-time middleware.	Doctoral Symposium on Middleware	2004	DBLP DOI BibTeX RDF	real-time, middleware, dynamic reconfiguration
26	Régis Leveugle, Lörinc Antoni, Béla Fehér	Dependability Analysis: A New Application for Run-Time Reconfiguration.	IPDPS	2003	DBLP DOI BibTeX RDF	hardware emulation, fault injection, dependability analysis, Digital circuits, run-time reconfiguration
26	Haralambos Laskaridis, Georgios I. Papadimitriou, Andreas S. Pomportsis	Applying Optical Reconfiguration on ATM Switch Fabrics.	IPDPS	2003	DBLP DOI BibTeX RDF	ATM, reconfiguration, correlation, switch fabric
26	Nitin Srivastava, Jerry L. Trahan, Ramachandran Vaidyanathan, Suresh Rai	Adaptive Image Filtering Using Run-Time Reconfiguration.	IPDPS	2003	DBLP DOI BibTeX RDF	adaptive image filtering, image processing, run-time reconfiguration
26	Wu Jigang, Thambipillai Srikanthan	On the Reconfiguration Algorithm for Fault-Tolerant VLSI Arrays.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF	degradable VLSI array, fault-tolerance, reconfiguration, NP-completeness, greedy algorithm
26	Olav Lysne, Timothy Mark Pinkston, José Duato	A Methodology for Developing Dynamic Network Reconfiguration Processes.	ICPP	2003	DBLP DOI BibTeX RDF	dynamic network reconfiguration, interconnection network architecture, highly-available and highly-dependable network-based systems, Deadlock-free routing
26	Bogdan M. Maziarz, Vijay K. Jain	Automatic Reconfiguration and Yield of the TESH Multicomputer Network.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	TESH, fault-tolerance, routing, VLSI, Interconnection networks, reconfiguration, redundancy, yield, hierarchical networks, manufacturing defects, parallel computing systems, ULSI
26	Hwajung Lee, Hongsik Choi, Suresh Subramaniam 0001, Hyeong-Ah Choi	Preserving Survivability During Logical Topology Reconfiguration in WDM Ring Networks.	ICPP Workshops	2002	DBLP DOI BibTeX RDF	Wavelength Constraint, Reconfiguration Cost, Network Survivability
26	Hector A. Duran-Limon, Gordon S. Blair	Reconfiguration of Resources in Middleware.	WORDS	2002	DBLP DOI BibTeX RDF	resource reconfiguration, reflection, adaptive middleware, distributed multimedia
26	Edson L. Horta, John W. Lockwood, David E. Taylor, David B. Parlour	Dynamic hardware plugins in an FPGA with partial run-time reconfiguration.	DAC	2002	DBLP DOI BibTeX RDF	FPG, partial RTR, platform computing, Internet, routing, network, modularity, reconfiguration, IP, hardware, packet
26	George A. Papadopoulos, Farhad Arbab	Dynamic Reconfiguration in Coordination Languages.	HPCN	2000	DBLP DOI BibTeX RDF	Coordination Languages and Models, Software Engineering for Distributed and Parallel Systems, Modelling Software Architectures, Dynamic Reconfiguration, Component-Based Systems
26	Lukás Sekanina, Vladimír Drábek	Relation between Fault Tolerance and Reconfiguration in Cellular Systems.	IOLTW	2000	DBLP DOI BibTeX RDF	fault tolerance, reconfiguration, evolution, cell, cellular automaton
26	Yuh-Rong Leu, Sy-Yen Kuo	Distributed Fault-Tolerant Ring Embedding and Reconfiguration in Hypercubes.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	faulty link, free-link dimension, reconfiguration, hypercube, Hamiltonian cycle
26	Sumito Nakano, Naotake Kamiura, Yutaka Hata, Nobuyuki Matsui	Reconfiguration of Two-Dimensional Meshes Embedded in Faulty Hypercubes.	DFT	1999	DBLP DOI BibTeX RDF	reconfiguration, hypercube, embedding, two-dimensional mesh
22	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj	3D configuration caching for 2D FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
22	Cees T. A. M. de Laat, Chris Develder, Admela Jukan, Joe Mambretti	Introduction.	Euro-Par	2009	DBLP DOI BibTeX RDF
22	Antonino Tumeo, Simone Borgio, Davide Bosisio, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	A multiprocessor self-reconfigurable JPEG2000 encoder.	IPDPS	2009	DBLP DOI BibTeX RDF
22	Shafqat Khan, Emmanuel Casseau, Daniel Ménard	Reconfigurable SWP Operator for Multimedia Processing.	ASAP	2009	DBLP DOI BibTeX RDF
22	Eryk Laskowski, Marek Tudruj	Optimized Communication Control in Programs for Dynamic Look-Ahead Reconfigurable SoC Systems.	ISPDC	2008	DBLP DOI BibTeX RDF
22	Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera	Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, routing, variation, yield enhancement
22	Sebastian Lange, Martin Middendorf	Hyperreconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
22	Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner 0001, Jürgen Becker 0001, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker	Fine grain reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
22	Kimon Karras, Elias S. Manolakos	An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture.	FPL	2008	DBLP DOI BibTeX RDF
22	Kouhi Shinohara, Minoru Watanabe	Defect tolerance of holographic configurations in ORGAs.	IPDPS	2008	DBLP DOI BibTeX RDF
22	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Chenglie Du, Gang Li	A Software Dual-Bus Architecture Suitable for Distributed Real-Time Embedded System.	CSSE (4)	2008	DBLP DOI BibTeX RDF
22	Eryk Laskowski, Marek Tudruj	Inter-processor Communication Optimization in Dynamically Reconfigurable Embedded Parallel Systems.	PPAM	2007	DBLP DOI BibTeX RDF
22	Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril	Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.	VLSI Design	2007	DBLP DOI BibTeX RDF
22	Klaus Danne, Marco Platzner	An EDF schedulability test for periodic tasks on reconfigurable hardware devices.	LCTES	2006	DBLP DOI BibTeX RDF	scheduling, FPGA, real-time, reconfigurable hardware, periodic tasks
22	Minghui Wang, Shugen Ma, Bin Li 0001, Yuechao Wang	Configuration Analysis for Reconfigurable Modular Planetary Robots Based on MSV and CSM.	IROS	2006	DBLP DOI BibTeX RDF
22	Mateusz Majer	An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization.	FPL	2006	DBLP DOI BibTeX RDF
22	Steffen Toscher, Roland Kasper, Thomas Reinemann	Implementation of a reconfigurable hard real-time control system for mechatronic and automotive applications.	IPDPS	2006	DBLP DOI BibTeX RDF
22	Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto	Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
22	Armin Lawi, Kentaro Oda, Takaichi Yoshida	A Quorum Based Group k-Mutual Exclusion Algorithm for Open Distributed Environments.	ISPA	2005	DBLP DOI BibTeX RDF
22	Steffen Göbel 0001	An MDA Approach for Adaptable Components.	ECMDA-FA	2005	DBLP DOI BibTeX RDF
22	Wensheng Zhang 0001, Guohong Cao	DCTC: dynamic convoy tree-based collaboration for target tracking in sensor networks.	IEEE Trans. Wirel. Commun.	2004	DBLP DOI BibTeX RDF
22	Marc Epalza, Paolo Ienne, Daniel Mlynek	Adding Limited Reconfigurability to Superscalar Processors.	IEEE PACT	2004	DBLP DOI BibTeX RDF
22	Vangelis Gazis, Nancy Alonistioti, Lazaros F. Merakos	Metadata Design for Introspection-Capable Reconfigurable Systems.	NETWORKING	2004	DBLP DOI BibTeX RDF
22	Lei He, Tulika Mitra, Weng-Fai Wong	Configuration bitstream compression for dynamically reconfigurable FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
22	Shyamnath Harinath, Ron Sass	Reconfigurable Mapping Functions for Online Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF
22	Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana	The MOLEN rho-mu-Coded Processor.	FPL	2001	DBLP DOI BibTeX RDF
22	John Marty Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici	On-Line Fault Tolerance for FPGA Interconnect with Roving STARs.	DFT	2001	DBLP DOI BibTeX RDF
22	John S. McCaskill, Patrick Wagler	From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains.	FPL	2000	DBLP DOI BibTeX RDF
22	Etienne Godard, Sanjeev Setia, Elizabeth L. White	DyRecT: Software Support for Adaptive Parallelism on NOWs.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
22	Andreas Savva, Takashi Nanya	A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	memory duplication, RSM, fault tolerance, PRAM, graceful degradation, MPP, BSP model