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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6857 occurrences of 2748 keywords
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Results
Found 7335 publication records. Showing 7335 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Seungryul Choi, Nicholas Kohout, Sumit Pamnani, Dongkeun Kim, Donald Yeung |
A general framework for prefetch scheduling in linked data structures and its application to multi-chain prefetching. |
ACM Trans. Comput. Syst. |
2004 |
DBLP DOI BibTeX RDF |
memory parallelism, pointer-chasing code, Data prefetching |
20 | David A. Papa, Saurabh N. Adya, Igor L. Markov |
Constructive benchmarking for placement. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
placer, performance, evaluation, benchmark, comparison |
20 | Keith D. Underwood, Ron Brightwell |
The Impact of MPI Queue Usage on Message Latency. |
ICPP |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Jason Cong, Michail Romesis, Min Xie 0004 |
Optimality, scalability and stability study of partitioning and placement algorithms. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
optimality, scalability, stability, partitioning, placement |
20 | Jim Gray 0001 |
A View of Database System Performance Measures. |
SIGMETRICS |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Cliff C. N. Sze |
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
VLSI, benchmarks, physical design, clock network synthesis |
19 | Prasun Dewan |
A demonstration of the flexibility of widget generation. |
EICS |
2010 |
DBLP DOI BibTeX RDF |
mvc, benchmarks, inheritance, layout |
19 | Meikel Poess, Raghunath Othayoth Nambiar |
A power consumption analysis of decision support systems. |
WOSP/SIPEW |
2010 |
DBLP DOI BibTeX RDF |
performance tuning and optimization, power and performance, use of benchmarks in industry and academia, energy efficiency, benchmarking, software performance testing |
19 | Håkon Ording Bugge |
An evaluation of Intel's core i7 architecture using a comparative approach. |
Comput. Sci. Res. Dev. |
2009 |
DBLP DOI BibTeX RDF |
SPEC MPI2007, Nehalem, iCore7, Harpertown, Quad-Core, QuickPath Interconnect, Moore’s Law, Benchmarking, Stream, Micro-benchmarks |
19 | Marcelo R. N. Mendes, Pedro Bizarro, Paulo Marques |
A Performance Study of Event Processing Systems. |
TPCTC |
2009 |
DBLP DOI BibTeX RDF |
Benchmarking, Complex Event Processing, Micro-benchmarks |
19 | Jing Chen 0017, Silvio Micali |
A new approach to auctions and resilient mechanism design. |
STOC |
2009 |
DBLP DOI BibTeX RDF |
collusion-resilient auctions, implementation in surviving strategies, player-knowledge benchmarks, resilient mechanism design, combinatorial auctions |
19 | Ziv Bar-Yossef, Maxim Gurevich |
Random sampling from a search engine's index. |
J. ACM |
2008 |
DBLP DOI BibTeX RDF |
Benchmarks, search engines, sampling, size estimation |
19 | Davood Shamsi, Farinaz Koushanfar, Miodrag Potkonjak |
Challenging benchmark for location discovery in ad hoc networks: foundations and applications. |
MobiHoc |
2008 |
DBLP DOI BibTeX RDF |
add hoc networks, hard instances, localization, benchmarks, NP-complete problem |
19 | Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov |
The coming of age of (academic) global routing. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
optimization, routing, VLSI, benchmarks, computer-aided design, congestion, global routing, wirelength |
19 | Pilar Caamaño, Francisco Bellas, José Antonio Becerra, Richard J. Duro |
Application domain study of evolutionary algorithms in optimization problems. |
GECCO |
2008 |
DBLP DOI BibTeX RDF |
algorithm characterization, comparison tests, optimization benchmarks, evolutionary algorithms, error measures |
19 | Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
RevLib: An Online Resource for Reversible Functions and Reversible Circuits. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Benchmarks, Synthesis, Reversible Logic |
19 | Pawel Gepner, David L. Fraser, Michal Filip Kowalik |
Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications. |
ICCS (1) |
2008 |
DBLP DOI BibTeX RDF |
quad-core processors, parallel processing, benchmarks, HPC, multi-core processors |
19 | Malay K. Ganai, Aarti Gupta |
Efficient BMC for Multi-Clock Systems with Clocked Specifications. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
OpenCores multiclock system benchmarks, clocked specifications, multiphased clocks, level-sensitive latches, SAT-based bounded model checking, synchronous multiclock systems, clocked LTL properties, clock modeling schemes, clock constraints, loop-checks, gated clocks |
19 | Andrew Over, Bill Clarke, Peter E. Strazdins |
A Comparison of Two Approaches to Parallel Simulation of Multiprocessors. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
speedup analysis, Sparc Sulima, UltraSPARC IIICu-based multiprocessor systems, careful locking, simulation time quantum, serial simulation, load-balancing, parallel simulation, parallel discrete event simulation, interconnect model, NAS parallel benchmarks |
19 | Brian P. Doherty |
A real-time benchmark for Java. |
JTRES |
2007 |
DBLP DOI BibTeX RDF |
SPECjbb2005, Java, real-time, benchmarks, RTSJ |
19 | Rachid Guerraoui, Michal Kapalka, Jan Vitek |
STMBench7: a benchmark for software transactional memory. |
EuroSys |
2007 |
DBLP DOI BibTeX RDF |
benchmarks, software transactional memory |
19 | Ziv Bar-Yossef, Maxim Gurevich |
Random sampling from a search engine's index. |
WWW |
2006 |
DBLP DOI BibTeX RDF |
benchmarks, search engines, sampling, size estimation |
19 | Ai-Hsin Liu, Robert P. Dick |
Automatic run-time extraction of communication graphs from multithreaded applications. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
communication, benchmarks, synthesis, multithread, task graph, run-time |
19 | Javier Fabra, Pedro Álvarez 0001, José A. Bañares, Joaquin Ezpeleta |
RLinda: A Petri Net Based Implementation of the Linda Coordination Paradigm for Web Services Interactions. |
EC-Web |
2006 |
DBLP DOI BibTeX RDF |
Tuple space benchmarks, Petri nets, Linda, Service coordination |
19 | Rahul Garg 0001, Yogish Sabharwal |
MPI and communication - Software routing and aggregation of messages to optimize the performance of HPCC randomaccess benchmark. |
SC |
2006 |
DBLP DOI BibTeX RDF |
HPC challenge, randomaccess, benchmarks, high performance computing, supercomputing, linpack, Blue Gene/L |
19 | Parkson Wong, Haoqiang Jin, Jeffrey C. Becker |
Load Balancing Multi-Zone Applications on a Heterogeneous Cluster with Multi-Level Parallelism. |
ISPDC/HeteroPar |
2004 |
DBLP DOI BibTeX RDF |
load balancing, heterogeneous cluster, NAS Parallel Benchmarks, hybrid parallel programming |
19 | Jürgen Dix, Ugur Kuter, Dana S. Nau |
Planning in Answer Set Programming Using Ordered Task Decomposition. |
KI |
2003 |
DBLP DOI BibTeX RDF |
HTN planning, ASP systems, benchmarks, nonmonotonic reasoning |
19 | Ludmila Cherkasova, Wenting Tang |
Capacity planning tool for streaming media services. |
ACM Multimedia |
2003 |
DBLP DOI BibTeX RDF |
media server benchmarks, media server capacity, workload profiling, measurements, SLAs, capacity planning |
19 | Lutz Prechelt, Stefan U. Hänßgen |
Efficient Parallel Execution of Irregular Recursive Programs. |
IEEE Trans. Parallel Distributed Syst. |
2002 |
DBLP DOI BibTeX RDF |
Granularity control, benchmarks, profiling, recursion, instrumentation, SMP, irregular problems |
19 | Hillery C. Hunter, Wen-mei W. Hwu |
Code coverage and input variability: effects on architecture and compiler research. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
architecture, compiler, benchmarks, DSP, telecommunications, code coverage |
19 | Ruofan Xu, Michael S. Hsiao |
Embedded core testing using genetic algorithms. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
gate level implementation, user defined logic, random inputs, high level benchmarks, wrapper size, genetic algorithms, genetic algorithms, fault diagnosis, logic testing, controllability, controllability, high level synthesis, automatic test pattern generation, observability, observability, application specific integrated circuits, fault coverage, SOC, test application time, test patterns, embedded core testing, internal state |
19 | Mauricio Marín |
Comparative Analysis of a Parallel Discrete-Event Simulator. |
SCCC |
2000 |
DBLP DOI BibTeX RDF |
simulation running times, optimistic synchronization protocol, bulk-synchronous parallel model, parallel processing, protocols, benchmarks, discrete event simulation, synchronisation, software performance evaluation, parallel discrete-event simulator, large scale systems, protocol performance |
19 | Jens Mache |
An Assessment of Gigabit Ethernet as Cluster Interconnect. |
IWCC |
1999 |
DBLP DOI BibTeX RDF |
cluster interconnect, performance evaluation, communication network, Gigabit Ethernet, NAS parallel benchmarks |
19 | Zhe Wu 0002, Benjamin W. Wah |
Solving Hard Satisfiability Problems: A Unified Algorithm Based on Discrete Lagrange Multipliers. |
ICTAI |
1999 |
DBLP DOI BibTeX RDF |
DIMACS benchmarks, discrete Lagrange-multiplier method, first-order search procedure, satisfiability, traps |
19 | Felip Manyà, Ramón Béjar, Gonzalo Escalada-Imaz |
The satisfiability problem in regular CNF-formulas. |
Soft Comput. |
1998 |
DBLP DOI BibTeX RDF |
Multiple-valued regular CNF-formulas, benchmarks, threshold, satisfiability problem |
19 | Heng Liao, Andrew Wolfe |
Available Parallelism in Video Applications. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
MPEG1, MPEG2, SPEC benchmarks, audio applications, general-purpose applications, linear complexity global scheduling algorithm, video coding, encoders, instruction-level parallelism, decoders, optimization techniques, MPEG4, H.263, media processors, video applications, graphics applications |
19 | Jian Li 0061, Rajesh K. Gupta 0001 |
Decomposition of timed decision tables and its use in presynthesis optimizations. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
TDT decomposition, behavioral HDL description, kernel extraction algorithm, optimized HDL description, presynthesis optimizations, system behavior model, timed decision table decomposition, benchmarks, decision tables, circuit synthesis |
19 | W. Lynn Gallagher, Chuan-lin Wu |
Evaluation of a memory hierarchy for the MTS multithreaded processor. |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache |
19 | Kuang-Chih Liu, Chung-Ta King |
On the effectiveness of sectored caches in reducing false sharing misses. |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
sectored caches, false sharing misses, bus-based multiprocessors, coherence unit, MESI protocol, LU, SORBYR, SORBYC, benchmarks, FFT, performance metric, cache storage, Radix |
19 | Thomas Ragg, Steffen Gutjahr |
Automatic determination of optimal network topologies based on information theory and evolution. |
EUROMICRO |
1997 |
DBLP DOI BibTeX RDF |
optimal network topology, automatic topology determination, learning task, input-output relation, neural unit sorting, intelligent mutation operator, input unit ranking, efficient optimization technique, network scalability, evolutionary algorithm, benchmarks, evolution, information theory, network topology, multilayer perceptrons, network performance, information content, list, network size |
19 | Silvia M. Figueira, Francine Berman |
Predicting Slowdown for Networked Workstations. |
HPDC |
1997 |
DBLP DOI BibTeX RDF |
performance-efficient allocations, competing load, high-performance clusters, scientific benchmarks, performance evaluation, networks of workstations, slowdown, networked workstations, allocation strategies |
19 | Henk L. Muller, Paul W. A. Stallard, David H. D. Warren |
The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison. |
PDP |
1996 |
DBLP DOI BibTeX RDF |
virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios |
19 | Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao |
Easily Testable Data Path Allocation Using Input/Output Registers. |
Asian Test Symposium |
1996 |
DBLP DOI BibTeX RDF |
testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design |
19 | Wanlin Cao, Dhiraj K. Pradhan |
Sequential redundancy identification using recursive learning. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
ISCAS benchmarks, c-cycle redundancies, c-cycle redundant faults, redundancy identification algorithm, sequential redundancy identification, state transition information, uncontrollability analysis, logic CAD, FIRES, untestable faults, recursive learning |
19 | Sameer A. Nene, Shree K. Nayar |
Closest Point Search in High Dimensions. |
CVPR |
1996 |
DBLP DOI BibTeX RDF |
projection search, searching by slicing, object recognition, benchmarks, Pattern classification, nearest neighbor, closest point |
19 | Pablo Ibáñez, Víctor Viñals |
Performance Assessment of Contents Management in Multilevel On-Chip Caches. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
multilevel on-chip caches, Inclusion contents management, Exclusion, second-level cache miss ratio, system CPI, floating point SPEC'92 benchmarks, performance metrics, contents management, cache storage, design space, performance assessment, Demand |
19 | Dimitrios Kagaris, Spyros Tragoudas |
A multiseed counter TPG with performance guarantee. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
built-in test pattern generators, multiseed counter test pattern generator, low hardware overhead, fast CAD tool, ISCAS'85 benchmarks, hardware/time overhead, built-in self test, performance guarantee, test set generation |
19 | Fidel Muradali, Janusz Rajski |
A self-driven test structure for pseudorandom testing of non-scan sequential circuits. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test |
19 | Dimitrios Kagaris, Spyros Tragoudas |
Generating deterministic unordered test patterns with counters. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
counting circuits, deterministic unordered test patterns, counter-based schemes, built-in mechanisms, test pattern generation session, ISCAS'85 benchmarks, logic testing, built-in self test, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, hardware overhead |
19 | Suresh Rajgopal |
Challenges in Low Power Microprocessor Design. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
power benchmarks, latch power, idle power, active power, clock enabling, max power, thermal power, transient power, low-power, clock gating, microprocessor design, di/dt |
19 | Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé |
Quantitative analysis of vector code. |
PDP |
1995 |
DBLP DOI BibTeX RDF |
Convex C3480, Perfect Club benchmarks, cost/performance tradeoffs, single bus memory architecture, slow-down, vector register, vector programs, performance evaluation, virtual machines, simulation study, vector processor systems, vector code |
19 | Chantal Ykman-Couvreur, Bill Lin 0001 |
Optimised state assignment for asynchronous circuit synthesis. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
optimised state assignment, asynchronous circuit synthesis, complete state coding, state graph level, asynchronous benchmarks, circuit area, logic design, encoding, asynchronous circuits, computation time, state assignment |
19 | S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault |
Test configurations to enhance the testability of sequential circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector |
19 | Soumitra Bose, Vishwani D. Agrawal |
Sequential logic path delay test generation by symbolic analysis. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions |
19 | Glenn Jennings |
Accurate ternary-valued compiled logic simulation of complex logic networks by OTDD composition. |
Annual Simulation Symposium |
1995 |
DBLP DOI BibTeX RDF |
circuit diagrams, ternary-valued compiled logic simulation, complex logic networks, OTDD composition, combinational U inaccuracies, reconvergent fanout, Kleenean strong ternary logic, Ordered Ternary Decision Diagram, standard ISCAS 85 benchmarks, performance evaluation, logic CAD, digital simulation, circuit analysis computing, ternary logic, incompletely-specified functions |
19 | Sekhar R. Sarukkai, Jerry C. Yan, Melisa Schmidt |
Automated instrumentation and monitoring of data movement in parallel programs. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
data-structure alignments, inter-processor data-structure interactions, compiler front end tools, tracking data-structure movements, NAS benchmarks, parallel programming, parallel programs, data structures, message passing, data flow analysis, software performance evaluation, program diagnostics, performance tools, message passing programs, inter-processor communications, data movement |
19 | Ching-Farn Eric Wu, Yew-Huey Liu, Yarsun Hsu |
Timestamp consistency and trace-driven analysis for distributed parallel systems. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
IBM computers, timestamp consistency, trace-driven analysis, distributed parallel systems, continuous event data stream, parallel program execution progress, separate streams, logical event order, local clock discrepancy, performance analysis techniques, IBM SPn systems, system events, minimal trace overhead, trace-driven analysis tools, NAS kernel benchmarks, performance evaluation, parallel processing, message passing, message passing, timing, parallel machines, clocks, system monitoring, integrated approach, multiple processors |
19 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu |
A comprehensive estimation technique for high-level synthesis. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area |
19 | Abdel-Fattah Yousif, Jun Gu |
Concurrent automatic test pattern generation algorithm for combinational circuits. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
concurrent automatic test pattern generation algorithm, global computations techniques, concurrent search, ISCAS'85, ISCAS'89 benchmarks, computational complexity, logic testing, NP-hard, combinational circuits, combinational circuits, automatic testing |
19 | Glenn Holt, Akhilesh Tyagi |
EPNR: an energy-efficient automated layout synthesis package. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
EPNR, energy-efficient automated layout synthesis package, MCNC Logic Synthesis '93 benchmarks, VPNR, VLSI energy minimization problems, VLSI, logic testing, placement, logic CAD, circuit layout CAD, global routing, logic arrays, standard cells, channel routing |
19 | Richard Games, Arkady Kanevsky, Peter C. Krupp, Leonard Monk |
Real-time communications scheduling for massively parallel processors. |
IEEE Real Time Technology and Applications Symposium |
1995 |
DBLP DOI BibTeX RDF |
real-time communications scheduling, computationally intensive, lifecycle costs, large-scale scientific computing, software challenges, processing nodes, real-time application benchmarks, scheduling, performance evaluation, fault tolerance, real-time systems, parallel processing, multiprocessor interconnection networks, multiprocessor interconnection networks, real-time scheduling, processor scheduling, real-time applications, massively parallel processors, multi-level security |
19 | Ragunathan Rajkumar, Michael Gagliardi, Lui Sha |
The real-time publisher/subscriber inter-process communication model for distributed real-time systems: design and implementation. |
IEEE Real Time Technology and Applications Symposium |
1995 |
DBLP DOI BibTeX RDF |
utility programs, real-time publisher/subscriber inter-process communication model, application-level toolkits, group-based programming, anonymous communication techniques, programming ease, upgradable real-time systems, performance benchmarks, design, real-time systems, scalability, software architecture, distributed processing, software tools, interfaces, implementation, application program interfaces, portability, programming models, distributed real-time systems, software portability, application generators, analyzability, programming interface |
19 | Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye |
A technique to determine power-efficient, high-performance superscalar processors. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation |
19 | Kleanthis Psarris, Santosh Pande |
Classical dependence analysis techniques: sufficiently accurate in practice. |
HICSS (2) |
1995 |
DBLP DOI BibTeX RDF |
GCD test, Banerjee-Wolfe test, statement data dependence, automatic loop parallelization, Perfect benchmarks, exact test, program testing, data analysis, accuracy, parallelizing compilers, program diagnostics, sufficient conditions, program control structures, parallelising compilers, data dependence analysis, greatest common divisor, automatic vectorization |
19 | Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri |
Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture |
19 | Jin-Tai Yan, Pei-Yung Hsiao |
A new fuzzy-clustering-based approach for two-way circuit partitioning. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
fuzzy-clustering-based approach, two-way circuit partitioning, circuit netlist, undirected edge-weighted graph, tree net model, clustering distance, area information, area-balanced constraints, circuit benchmarks, VLSI, simulated annealing, network topology, trees (mathematics), fuzzy set theory, logic partitioning, fuzzy c-means clustering, fuzzy memberships |
19 | Nayeem Islam, Roy H. Campbell |
Design Considerations for Shared Memory Multiprocessor Message Systems. |
IEEE Trans. Parallel Distributed Syst. |
1992 |
DBLP DOI BibTeX RDF |
comparative performance, message passing system designs, shared memory EncoreMultimax multiprocessor, example parallel applications, shared memorymachine results, Intel iPSC/2, NX/2 operating system, bufferorganization, value semantics, kernel space, memory caching, message sizes, synchronization, benchmarks, message passing, program testing, parallel machines, shared memory systems, design alternatives, parallelprogramming, copying, coordination strategy |
19 | Jiun-Ming Hsu, Prithviraj Banerjee |
Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer. |
IEEE Trans. Parallel Distributed Syst. |
1992 |
DBLP DOI BibTeX RDF |
parallel CAD, realistic workloads, time interval distributions, statistical functions, nonlinear regression technique, message destinations, trace-drive simulation environment, performance evaluation, performance evaluation, parallel programs, parallel programming, benchmarks, statistical analysis, hypercube networks, digital simulation, workload characterization, execution traces, temporal locality, spatial locality, hypercube multicomputer, software monitoring, DMA, message length, link utilizations |
19 | Richard S. Wallace, Michael D. Howard |
HBA Vision Architecture: Built and Benchmarked. |
IEEE Trans. Pattern Anal. Mach. Intell. |
1989 |
DBLP DOI BibTeX RDF |
vision architecture, hierarchical bus architecture, algorithmic benchmarks, local neighborhood operations, Apply, image-to-image transformations, floating-point coprocessors, computer vision, computer vision, parallel processing, parallel architectures, software tools, programming environment, programming environments, computerised picture processing, programming model, looping, boundary conditions |
17 | Sameh Sharkawi, Don DeSota, Raj Panda, Rajeev Indukuru, Stephen Stevens, Valerie E. Taylor, Xingfu Wu |
Performance projection of HPC applications using SPEC CFP2006 benchmarks. |
IPDPS |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Andreas Eisenblätter, Hans-Florian Geerdes |
Capacity optimization for UMTS: Bounds and benchmarks for interference reduction. |
PIMRC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Ariel Tchougang, Alexandre Blansché, Laurent A. Baumes, Nicolas Lachiche, Pierre Collet |
Testing the CAX on a Real-World Problem and Other Benchmarks. |
PPSN |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Marc Somers, JoAnn M. Paul |
Webpage-based benchmarks for mobile device design. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Seetharami R. Seelam, I-Hsin Chung, Guojing Cong, Hui-Fang Wen, David J. Klepacki |
Workload Performance Characterization of DARPA HPCS Benchmarks. |
HPCC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Frederic Maris, Pierre Régnier |
TLP-GP: New Results on Temporally-Expressive Planning Benchmarks. |
ICTAI (1) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Dibyendu Das 0001, Madhavi Valluri, Michael Wong, Chris Cambly |
Speeding up STL Set/Map Usage in C++ Applications. |
SIPEW |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Xiaoqing Cheng |
Performance, Benchmarking and Sizing in Developing Highly Scalable Enterprise Software. |
SIPEW |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Jaydeep Marathe, Frank Mueller 0001 |
Source-Code-Correlated Cache Coherence Characterization of OpenMP Benchmarks. |
IEEE Trans. Parallel Distributed Syst. |
2007 |
DBLP DOI BibTeX RDF |
simulation, Cache memories, SMPs, program instrumentation, coherence protocols, dynamic binary rewriting |
17 | Radek Pelánek |
BEEM: Benchmarks for Explicit Model Checkers. |
SPIN |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Karl Fürlinger, Michael Gerndt, Jack J. Dongarra |
Scalability Analysis of the SPEC OpenMP Benchmarks on Large-Scale Shared Memory Multiprocessors. |
International Conference on Computational Science (2) |
2007 |
DBLP DOI BibTeX RDF |
Shared Memory Multiprocessors, SPEC |
17 | Benjamin Z. Yao, Xiong Yang, Song Chun Zhu |
Introduction to a Large-Scale General Purpose Ground Truth Database: Methodology, Annotation Tool and Benchmarks. |
EMMCVPR |
2007 |
DBLP DOI BibTeX RDF |
Ground truth Annotation, Sketch representation, Top-down/Bottom-up Labeling, Benchmark, Image database |
17 | Farrukh Nadeem, Muhammad Murtaza Yousaf, Radu Prodan, Thomas Fahringer |
Soft Benchmarks-Based Application Performance Prediction Using a Minimum Training Set. |
e-Science |
2006 |
DBLP DOI BibTeX RDF |
|
17 | P. Bull, A. Knowles, Gianni Tedesco, Andrew Hone |
Diophantine Benchmarks for the B-Cell Algorithm. |
ICARIS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Rajaa S. Shindi, Shaun Cooper |
Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated. |
SIGAda |
2006 |
DBLP DOI BibTeX RDF |
sim-alpha, cache, cpu, context switches, processor simulators |
17 | Tushar S. Kulkarni, Bernd S. W. Schröder |
An Enumeration Problem in Ordered Sets Leads to Possible Benchmarks for Run-Time Prediction Algorithms. |
ICFCA |
2006 |
DBLP DOI BibTeX RDF |
search, constraint satisfaction, enumeration |
17 | M. Erkan Keremoglu, Serdar Tasiran, Tayfun Elmas |
A classification of concurrency bugs in java benchmarks by developer intent. |
PADTAD |
2006 |
DBLP DOI BibTeX RDF |
concurrency errors, verification, refinement, atomicity, race condition |
17 | Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John |
Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks. |
IISWC |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Eamonn Kenny, Brian A. Coghlan, George Tsouloupas, Marios D. Dikaiakos, John Walsh 0001, Stephen Childs, David O'Callaghan, Geoff Quigley |
Heterogeneous Grid Computing: Issues and Early Benchmarks. |
International Conference on Computational Science (3) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Philip J. Sokolowski, Daniel Grosu |
Performance of the NAS Parallel Benchmarks on Grid Enabled Clusters. |
NCA |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Rob F. Van der Wijngaart, Michael A. Frumkin |
Evaluating the Information Power Grid Using the NAS Grid Benchmarks. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Guansong Zhang, Priya Unnikrishnan, James Ren |
Experiments with Auto-Parallelizing SPEC2000FP Benchmarks. |
LCPC |
2004 |
DBLP DOI BibTeX RDF |
SMT machine, parallel do, OpenMP, parallelizing compiler, automatic parallelization |
17 | Eamonn J. Keogh, Shruti Kasetty |
On the Need for Time Series Data Mining Benchmarks: A Survey and Empirical Demonstration. |
Data Min. Knowl. Discov. |
2003 |
DBLP DOI BibTeX RDF |
data mining, time series, experimental evaluation |
17 | Vinod Tipparaju, Manojkumar Krishnan, Jarek Nieplocha, Gopalakrishnan Santhanaraman, Dhabaleswar K. Panda 0001 |
Exploiting Non-blocking Remote Memory Access Communication in Scientific Benchmarks. |
HiPC |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Loriano Storchi, Carlo Manuali, Osvaldo Gervasi, Giuseppe Vitillaro, Antonio Laganà, Francesco Tarantelli |
Linear Algebra Computation Benchmarks on a Model Grid Platform. |
International Conference on Computational Science |
2003 |
DBLP DOI BibTeX RDF |
|
17 | João Gabriel Silva |
Dependability Benchmarks: Can We Rely on Them? |
LADC |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Clint Kreitner |
The Development and Proliferation of Consensus Security Configuration Benchmarks for Systems Connected to the Interne. |
HICSS |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Daniel Etiemble |
Numerical Applications and Sub-Word Parallelism: The NAS Benchmarks on a Pentium 4. |
HPCS |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Eamonn J. Keogh, Shruti Kasetty |
On the need for time series data mining benchmarks: a survey and empirical demonstration. |
KDD |
2002 |
DBLP DOI BibTeX RDF |
data mining, time series, experimental evaluation |
17 | Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty |
A Set of Benchmarks fo Modular Testing of SOCs. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Michael A. Frumkin, Rob F. Van der Wijngaart |
NAS Grid Benchmarks: A Tool for Grid Space Exploration. |
HPDC |
2001 |
DBLP DOI BibTeX RDF |
|
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