Search results for "multiprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Benjamín Sahelices, Pablo Ibáñez, Víctor Viñals, José María Llabería	A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors.	Euro-Par	2009	DBLP DOI BibTeX RDF
18	Chenjie Yu, Xiangrong Zhou, Peter Petrov	Low-power inter-core communication through cache partitioning in embedded multiprocessors.	SBCCI	2009	DBLP DOI BibTeX RDF	low-power cache architectures, low-power cache coherence, MPSoC, on-chip communication
18	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
18	Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang 0058, Tianzhou Chen	L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	CMP, cache design, L1 cache
18	Ahmed Abousamra, Rami G. Melhem, Daniel Mossé	Minimizing expected energy consumption for streaming applications with linear dependencies on chip multiprocessors.	SIES	2009	DBLP DOI BibTeX RDF
18	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	Dynamic cache clustering for chip multiprocessors.	ICS	2009	DBLP DOI BibTeX RDF	non-uniform cache architecture (nuca), chip multiprocessor (cmp)
18	Kai Tian, Yunlian Jiang, Xipeng Shen	A study on optimally co-scheduling jobs of different lengths on chip multiprocessors.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	cache contention, cmp scheduling, perfect matching, a*-search, co-scheduling
18	Yamin Li, Shietung Peng, Wanming Chu	An Efficient Parallel Sorting Algorithm on Metacube Multiprocessors.	ICA3PP	2009	DBLP DOI BibTeX RDF	metacube, Parallel algorithm, hypercube, sort algorithm
18	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
18	Omer Khan, Sandip Kundu	Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.	HiPEAC	2009	DBLP DOI BibTeX RDF	Dynamic Thermal Management (DTM), Virtual Thermal Manager (VTM), Dynamic Voltage and Frequency Scaling (DVFS)
18	Scott Schneider 0001, Jae-Seung Yeom, Benjamin Rose, John C. Linford, Adrian Sandu, Dimitrios S. Nikolopoulos	A comparison of programming models for multiprocessors with explicitly managed memory hierarchies.	PPoPP	2009	DBLP DOI BibTeX RDF	explicitly managed memory hierarchies, programming models, cell be
18	Abhishek Bhattacharjee, Margaret Martonosi	Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors.	ISCA	2009	DBLP DOI BibTeX RDF	intel tbb, thread criticality prediction, parallel processing, caches, dvfs
18	Yefu Wang, Kai Ma, Xiaorui Wang	Temperature-constrained power control for chip multiprocessors with online model estimation.	ISCA	2009	DBLP DOI BibTeX RDF	power management, chip multiprocessor, feedback control
18	Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph	Process variation characterization of chip-level multiprocessors.	DAC	2009	DBLP DOI BibTeX RDF	software, process variation, characterization
18	Assaf Shacham, Keren Bergman, Luca P. Carloni	Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
18	Jieyi Long, Seda Ogrenci Memik, Gokhan Memik, Rajarshi Mukherjee	Thermal monitoring mechanisms for chip multiprocessors.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	Thermal sensor allocation, nonuniform and uniform sensor placement
18	Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger	Multitasking workload scheduling on flexible-core chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	flexible cores, multitask scheduling, multicore architectures
18	Yunlian Jiang, Xipeng Shen, Jie Chen 0010, Rahul Tripathi	Analysis and approximation of optimal co-scheduling on chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	CMP scheduling, cache contention, perfect matching, co-scheduling
18	Kenji Funaoka, Shinpei Kato, Nobuyuki Yamasaki	Energy-Efficient Optimal Real-Time Scheduling on Multiprocessors.	ISORC	2008	DBLP DOI BibTeX RDF	Energy-Aware Multiprocessor Systems, Voltage and Frequency Scaling, Real-Time Scheduling
18	Kenji Funaoka, Shinpei Kato, Nobuyuki Yamasaki	Work-Conserving Optimal Real-Time Scheduling on Multiprocessors.	ECRTS	2008	DBLP DOI BibTeX RDF
18	Stephen A. Edwards, Nalini Vasudevan, Olivier Tardieu	Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads.	DATE	2008	DBLP DOI BibTeX RDF
18	Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Functional Self-Testing for Bus-Based Symmetric Multiprocessors.	DATE	2008	DBLP DOI BibTeX RDF
18	Ramazan Bitirgen, Engin Ipek, José F. Martínez	Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach.	MICRO	2008	DBLP DOI BibTeX RDF
18	Brian Rogers, Chenyu Yan, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin	Single-level integrity and confidentiality protection for distributed shared memory multiprocessors.	HPCA	2008	DBLP DOI BibTeX RDF
18	Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin	Implementation and evaluation of a migration-based NUCA design for chip multiprocessors.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	NUCA, post office placement problem, CMP, data migration
18	Chenjie Yu, Peter Petrov	Distributed and low-power synchronization architecture for embedded multiprocessors.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	synchronization, multiprocessor
18	Kenji Funaoka, Shinpei Kato, Nobuyuki Yamasaki	New Abstraction for Optimal Real-Time Scheduling on Multiprocessors.	RTCSA	2008	DBLP DOI BibTeX RDF
18	Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin	Integrated code and data placement in two-dimensional mesh based chip multiprocessors.	ICCAD	2008	DBLP DOI BibTeX RDF
18	Vijay Nagarajan, Rajiv Gupta 0001	Support for symmetric shadow memory in multiprocessors.	PADTAD	2008	DBLP DOI BibTeX RDF	symmetric shadow memory, monitoring
18	Zhiyi Yu, Bevan M. Baas	A low-area interconnect architecture for chip multiprocessors.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Qifei Fan, Ge Zhang 0007, Weiwu Hu	A synchronized variable frequency clock scheme in chip multiprocessors.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Christian Bienia, Sanjeev Kumar, Kai Li 0001	PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors.	IISWC	2008	DBLP DOI BibTeX RDF
18	Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	Lightweight DMA management mechanisms for multiprocessors on FPGA.	ASAP	2008	DBLP DOI BibTeX RDF
18	Abu Saad Papa, Madhu Mutyam	Power management of variation aware chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	chipmulti-processor, process variation, power-aware, adaptive voltage scaling
18	Mahmut T. Kandemir, Feihui Li, Mary Jane Irwin, Seung Woo Son 0001	A novel migration-based NUCA design for chip multiprocessors.	SC	2008	DBLP DOI BibTeX RDF
18	Lars Arge, Michael T. Goodrich, Michael J. Nelson 0002, Nodari Sitchinava	Fundamental parallel algorithms for private-cache chip multiprocessors.	SPAA	2008	DBLP DOI BibTeX RDF	parallel external memory, pem, private-cache cmp
18	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
18	Chenjie Yu, Peter Petrov	Latency and bandwidth efficient communication through system customization for embedded multiprocessors.	DAC	2008	DBLP DOI BibTeX RDF	snoop protocol, embedded multiprocessor
18	Jan Christian Meyer, Anne C. Elster	Latency Impact on Spin-Lock Algorithms for Modern Shared Memory Multiprocessors.	CISIS	2008	DBLP DOI BibTeX RDF
18	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Nahalal: Cache Organization for Chip Multiprocessors.	IEEE Comput. Archit. Lett.	2007	DBLP DOI BibTeX RDF
18	Guilin Chen, Mahmut T. Kandemir	An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF
18	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
18	James Laudon, Lawrence Spracklen	The Coming Wave of Multithreaded Chip Multiprocessors.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	performance, parallel programming, multithreading, Chip multiprocessing
18	Alexandra Fedorova, Margo I. Seltzer, Michael D. Smith 0001	Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler.	PACT	2007	DBLP DOI BibTeX RDF
18	Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg	Strategies for Compiling µ TC to Novel Chip Multiprocessors.	SAMOS	2007	DBLP DOI BibTeX RDF
18	Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	An Interrupt Controller for FPGA-based Multiprocessors.	ICSAMOS	2007	DBLP DOI BibTeX RDF
18	Pepijn J. de Langen, Ben H. H. Juurlink	Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors.	SAMOS	2007	DBLP DOI BibTeX RDF
18	Filip Pizlo, Daniel Frampton, Erez Petrank, Bjarne Steensgaard	Stopless: a real-time garbage collector for multiprocessors.	ISMM	2007	DBLP DOI BibTeX RDF	real-time, concurrency, garbage collection, lock-free
18	Haakon Dybdahl, Per Stenström	An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors.	HPCA	2007	DBLP DOI BibTeX RDF
18	Alaa R. Alameldeen, David A. Wood 0001	Interactions Between Compression and Prefetching in Chip Multiprocessors.	HPCA	2007	DBLP DOI BibTeX RDF
18	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Adaptive L2 Cache for Chip Multiprocessors.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
18	John Cieslewicz, Kenneth A. Ross, Ioannis Giannakakis	Parallel buffers for chip multiprocessors.	DaMoN	2007	DBLP DOI BibTeX RDF
18	Martin Karlsson, Erik Hagersten	Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution.	IPDPS	2007	DBLP DOI BibTeX RDF
18	Hyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen	Synchronization for an optimal real-time scheduling algorithm on multiprocessors.	SIES	2007	DBLP DOI BibTeX RDF
18	Björn Andersson, Eduardo Tovar	Competitive Analysis of Static-Priority Partitioned Scheduling on Uniform Multiprocessors.	RTCSA	2007	DBLP DOI BibTeX RDF
18	Marco Galluzzi, Enrique Vallejo 0001, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith 0001, Mateo Valero	Implicit Transactional Memory in Kilo-Instruction Multiprocessors.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
18	Ruibin Xu, Rami G. Melhem, Daniel Mossé	Energy-Aware Scheduling for Streaming Applications on Chip Multiprocessors.	RTSS	2007	DBLP DOI BibTeX RDF
18	Sebastian Herbert, Diana Marculescu	Analysis of dynamic voltage/frequency scaling in chip-multiprocessors.	ISLPED	2007	DBLP DOI BibTeX RDF	chip-multiprocessor, dynamic voltage/frequency scaling
18	Michela Becchi, Mark A. Franklin, Patrick Crowley	Performance/area efficiency in chip multiprocessors with micro-caches.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	networking workload, chip multiprocessor, cache hierarchies
18	Lakshmana Rao Vittanala, Mainak Chaudhuri	Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors.	ICPP	2007	DBLP DOI BibTeX RDF
18	Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos	Mechanisms for store-wait-free multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	store buffer design, memory consistency models
18	Sanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen	Carbon: architectural support for fine-grained parallelism on chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	loop and task parallelism, CMP, architectural support
18	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	Efficient Synchronization for Embedded On-Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
18	JoAnn M. Paul, Donald E. Thomas, Alex Bobrek	Scenario-oriented design for single-chip heterogeneous multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
18	Jyh-Biau Chang, Ce-Kuen Shieh, Tyng-Yeu Liang	A Transparent Distributed Shared Memory for Clustered Symmetric Multiprocessors.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	thread architecture, reconfiguration, cluster computing, distributed shared memory, symmetric multiprocessor
18	Brian Rogers, Milos Prvulovic, Yan Solihin	Efficient data protection for distributed shared memory multiprocessors.	PACT	2006	DBLP DOI BibTeX RDF	DSM multiprocessor, memory encryption and authentication, data security
18	Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven	Throughput optimization via cache partitioning for embedded multiprocessors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
18	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
18	Michael R. Marty, Mark D. Hill	Coherence Ordering for Ring-based Chip Multiprocessors.	MICRO	2006	DBLP DOI BibTeX RDF
18	Jian Li 0059, José F. Martínez	Dynamic power-performance adaptation of parallel computation on chip multiprocessors.	HPCA	2006	DBLP DOI BibTeX RDF
18	Haakon Dybdahl, Per Stenström, Lasse Natvig	A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors.	HiPC	2006	DBLP DOI BibTeX RDF
18	Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope	Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors.	ARCS	2006	DBLP DOI BibTeX RDF
18	Hou Rui, Longbing Zhang, Weiwu Hu	A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors.	Euro-Par	2006	DBLP DOI BibTeX RDF
18	Navid Imani, Hamid Sarbazi-Azad	A physical particle and plane framework for load balancing in multiprocessors.	IPDPS	2006	DBLP DOI BibTeX RDF
18	Matthew Curtis-Maury, James Dzierwa, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Online strategies for high-performance power-aware thread execution on emerging multiprocessors.	IPDPS	2006	DBLP DOI BibTeX RDF
18	Xudong Shi 0003, Zhen Yang, Jih-Kwon Peir, Lu Peng 0001, Yen-Kuang Chen, Victor W. Lee, B. Liang	Coterminous locality and coterminous group data prefetching on chip-multiprocessors.	IPDPS	2006	DBLP DOI BibTeX RDF
18	Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren	Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors.	ICS	2006	DBLP DOI BibTeX RDF	Gauss-Seidel, temporal blocking, CMP, OpenMP, relaxation, orderings, multigrid, Poisson equation, cache blocking
18	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun	Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
18	Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha	SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors.	ICPADS (1)	2006	DBLP DOI BibTeX RDF	SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality
18	Chao-Chin Wu, Kuan-Chou Lai	A Loop Optimization Technique for Speculative Chip Multiprocessors.	IWNAS	2006	DBLP DOI BibTeX RDF
18	Martin Thuresson, Per Stenström	Scalable Value-Cache Based Compression Schemes for Multiprocessors.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
18	Raphael Fonte Boa, Alexandre Marques Amaral, Dulcinéia Oliveira da Penha, Carlos Augusto Paiva da Silva Martins, Petr Ekel	Parallel Image Segmentation in Reconfigurable Chip Multiprocessors.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
18	Rana Ejaz Ahmed	Energy-Aware Cache Coherence Protocol for Chip-Multiprocessors.	CCECE	2006	DBLP DOI BibTeX RDF
18	Luis Ceze, James Tuck 0001, Josep Torrellas, Calin Cascaval	Bulk Disambiguation of Speculative Threads in Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
18	Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie 0001, Narayanan Vijaykrishnan, Mahmut T. Kandemir	Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.	ISCA	2006	DBLP DOI BibTeX RDF
18	John D. Davis, Cong Fu 0010, James Laudon	The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
18	Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe	Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	performance analysis, low-power design, power management, System architectures, energy-aware systems, integration and modeling, design aids
18	Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Ozcan Ozturk 0001, Mustafa Karaköy, Ugur Sezer	Optimizing Array-Intensive Applications for On-Chip Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	On-chip multiprocessor, adaptive loop parallelization, embedded systems, energy consumption, integer linear programming, constrained optimization
18	Jian Li 0059, José F. Martínez	Power-performance considerations of parallel computing on chip multiprocessors.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	Voltage/frequency scaling, granularity, parallel efficiency
18	Juan Chen 0001, Yong Dong, Xuejun Yang, Dan Wu	A Compiler-Directed Energy Saving Strategy for Parallelizing Applications in On-Chip Multiprocessors.	ISPDC	2005	DBLP DOI BibTeX RDF
18	Lawrence Spracklen, Yuan Chou, Santosh G. Abraham	Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications.	HPCA	2005	DBLP DOI BibTeX RDF
18	David A. Bader, Kamesh Madduri	Design and Implementation of the HPCS Graph Analysis Benchmark on Symmetric Multiprocessors.	HiPC	2005	DBLP DOI BibTeX RDF
18	Mahmut T. Kandemir, Guangyu Chen, Feihui Li, I. Demirkiran	Using data replication to reduce communication energy on chip multiprocessors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
18	Ozcan Ozturk 0001, Mahmut T. Kandemir, G. Chen, Mary Jane Irwin, Mustafa Karaköy	Customized on-chip memories for embedded chip multiprocessors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
18	Scott Schneider 0001, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Factory: An Object-Oriented Parallel Programming Substrate for Deep Multiprocessors.	HPCC	2005	DBLP DOI BibTeX RDF	Multithreading substrate, Object-oriented parallel programming, Deep parallel architectures, Multiparadigm parallelism, Portability, Programmability
18	Alberto Ros 0001, Manuel E. Acacio, José M. García 0001	A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors.	Euro-Par	2005	DBLP DOI BibTeX RDF
18	Guojing Cong, David A. Bader	An Experimental Study of Parallel Biconnected Components Algorithms on Symmetric Multiprocessors (SMPs).	IPDPS	2005	DBLP DOI BibTeX RDF
18	Robert L. McGregor, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors.	IPDPS	2005	DBLP DOI BibTeX RDF
18	UmaMaheswari C. Devi, James H. Anderson	Desynchronized Pfair Scheduling on Multiprocessors.	IPDPS	2005	DBLP DOI BibTeX RDF
18	Neal K. Bambha, Shuvra S. Bhattacharyya	Communication strategies for shared-bus embedded multiprocessors.	EMSOFT	2005	DBLP DOI BibTeX RDF	scheduling, dataflow, interprocessor communication