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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9063 occurrences of 3443 keywords
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Results
Found 16149 publication records. Showing 16145 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Mary L. Bailey |
A time-based model for investigating parallel logic-level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7), pp. 816-824, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
30 | Byron Krauter, David Widiger |
Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 665-668, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
GCD frequency, LCM window, frequency-dependent noise, timing orthogonality, crosstalk, noise analysis, timing windows |
30 | Abhijit Das |
On the Transistor Sizing Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 258-261, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Timing Analysis, Timing Optimization, Transistor Sizing, Delay Constraint |
30 | Chanjung Park, Seog Park |
A multiversion locking protocol for real-time databases with multilevel security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30 - November 01, 1996, Seoul, Korea, pp. 136-143, 1996, IEEE Computer Society, 0-8186-7626-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiversion locking protocol, processes transactions, explicit timing constraints, logical data consistency, compatibility matrix, version selection algorithm, data integrity, timing constraints, multilevel security, real-time databases, temporal consistency |
30 | Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng |
Automatic synthesis of gate-level timed circuits with choice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 42-58, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates |
30 | Bernd J. Krämer, Luqi, Valdis Berzins |
Compositional Semantics of a Real-Time Prototyping Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 19(5), pp. 543-477, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
real-time prototyping language, PSDL, data flow notation, application-orientation timing, control constraints, algebraic high-level Petri nets, concurrency concepts, real-time systems, formal specification, Petri nets, synchronization, specification languages, abstract data types, abstract data types, formal semantics, algebraic specifications, software prototyping, hard real-time systems, compositional semantics, timing behavior |
29 | Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng |
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 566-569, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
critical path selection, statistical timing analysis, false path |
28 | John Sartori, Rakesh Kumar 0002 |
Overscaling-friendly timing speculation architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 209-214, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
stochastic processors, timing speculation, adaptability |
28 | Guihai Yan, Xiaoyao Liang, Yinhe Han 0001, Xiaowei Li 0001 |
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 485-496, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
complimentary effects, delay sensor, pvt variations, timing emergency, thread migration |
28 | Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li |
Static timing analysis for flexible TFT circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 799-802, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
flexible electronics, static timing analysis |
28 | Scott A. Crosby, Dan S. Wallach, Rudolf H. Riedi |
Opportunities and Limits of Remote Timing Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Inf. Syst. Secur. ![In: ACM Trans. Inf. Syst. Secur. 12(3), pp. 17:1-17:29, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
jitter, timing attacks, Information leakage |
28 | Eun Cheol Kim, Jae Sang Cha, Jin Young Kim 0001, Young Dae Lee, YouSik Hong, Jeong Jin Kang |
Robust timing jitter control method for network synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHIT ![In: Proceedings of the 2009 International Conference on Hybrid Information Technology, ICHIT 2009, Daejeon, Korea, August 27-29, 2009, pp. 647-651, 2009, ACM, 978-1-60558-662-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
network synchronization, slave, timing jitter control, delay, master |
28 | Wei Dong, Jiandong Li 0001, Zhuo Lu |
Joint timing error, frequency offset and channel estimation for MIMO systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, IWCMC 2009, Leipzig, Germany, June 21-24, 2009, pp. 878-882, 2009, ACM, 978-1-60558-569-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
frequency offset, MIMO, channel estimation, timing error |
28 | Billy Bob Brumley, Risto M. Hakala |
Cache-Timing Template Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIACRYPT ![In: Advances in Cryptology - ASIACRYPT 2009, 15th International Conference on the Theory and Application of Cryptology and Information Security, Tokyo, Japan, December 6-10, 2009. Proceedings, pp. 667-684, 2009, Springer, 978-3-642-10365-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cache-timing attacks, elliptic curve cryptography, side channel attacks |
28 | Emilia Käsper, Peter Schwabe |
Faster and Timing-Attack Resistant AES-GCM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2009, 11th International Workshop, Lausanne, Switzerland, September 6-9, 2009, Proceedings, pp. 1-17, 2009, Springer, 978-3-642-04137-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Galois/Counter mode, cache-timing attacks, AES, fast implementations |
28 | Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik |
A parametric approach for handling local variation effects in timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 126-129, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on chip variation (OCV), timing, parametric analysis |
28 | Mihir R. Choudhury, Kartik Mohanram |
Timing-driven optimization using lookahead logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 390-395, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
logic synthesis, timing optimization, lookahead |
28 | Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty |
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 43-46, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design space exploration, timing analysis, automotive |
28 | Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu |
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 70-75, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Verilog-AMS, Static timing analysis, Look-up table |
28 | Hao Li, Yue Zhuo |
Criticality history guided FPGA placement algorithm for timing optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 267-272, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
fpga, placement, timing optimization |
28 | Safar Hatami, Hamed Abrishami, Massoud Pedram |
Statistical timing analysis of flip-flops considering codependent setup and hold times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 101-106, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
codependency, hold time, piecewise linear, statistical static timing analysis (SSTA), probability, process variations, setup time |
28 | Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir |
Statistical diagnosis of unmodeled systematic timing effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 355-360, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
statistical diagnosis, learning, timing, delay test |
28 | Onur Aciiçmez, Werner Schindler, Çetin Kaya Koç |
Cache Based Remote Timing Attack on the AES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2007, The Cryptographers' Track at the RSA Conference 2007, San Francisco, CA, USA, February 5-9, 2007, Proceedings, pp. 271-286, 2007, Springer, 3-540-69327-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Remote Attack, AES, Timing Analysis, Side Channel Analysis, Cache Attack |
28 | Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang |
Timing-driven Steiner trees are (practically) free. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 389-392, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
arborescence, timing-driven, rectilinear Steiner tree |
28 | Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei |
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(6), pp. 621-630, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis |
28 | Onur Aciiçmez, Werner Schindler, Çetin Kaya Koç |
Improving Brumley and Boneh timing attack on unprotected SSL implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: Proceedings of the 12th ACM Conference on Computer and Communications Security, CCS 2005, Alexandria, VA, USA, November 7-11, 2005, pp. 139-146, 2005, ACM, 1-59593-226-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RSA, timing attacks, side-channel cryptanalysis |
28 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 426-430, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay |
28 | Yaping Zhan, Andrzej J. Strojwas, Xin Li 0001, Lawrence T. Pileggi, David Newmark, Mahesh Sharma |
Correlation-aware statistical timing analysis with non-gaussian delay distributions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 77-82, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
process variation, statistical timing |
28 | Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail |
Statistical static timing analysis: how simple can we get? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 652-657, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
statistical static timing analysis (SSTA), process variations |
28 | Serdar Cabuk, Carla E. Brodley, Clay Shields |
IP covert timing channels: design and detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: Proceedings of the 11th ACM Conference on Computer and Communications Security, CCS 2004, Washington, DC, USA, October 25-29, 2004, pp. 178-187, 2004, ACM, 1-58113-961-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
network covert channels, TCP/IP, detection, covert timing channels |
28 | Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein |
RESTA: a robust and extendable symbolic timing analysis tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 407-412, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
input constraints, symbolic CAD, timing analysis, decision diagrams |
28 | An Yu, David S. Brée |
A Clock-less Implementation of the AES Resists to Power and Timing Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (2) ![In: International Conference on Information Technology: Coding and Computing (ITCC'04), Volume 2, April 5-7, 2004, Las Vegas, Nevada, USA, pp. 525-532, 2004, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clock-less circuits, AES, timing attacks, cryptosystems, power attacks |
28 | Jiayong Le, Xin Li 0001, Lawrence T. Pileggi |
STAC: statistical timing analysis with correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 343-348, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
process variation, statistical timing |
28 | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha |
Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(2), pp. 183-193, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
communication devices test, high frequency test, jitter test, timing jitter |
28 | Jia Xu |
Making Software Timing Properties Easier to Inspect and Verify. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Softw. ![In: IEEE Softw. 20(4), pp. 34-41, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
preruntime scheduling, verification, real time, predictability, software, code, inspection, undecidability, timing properties, state space explosion |
28 | Yasuyuki Sakai, Kouichi Sakurai |
Timing Attack against Implementation of a Parallel Algorithm for Modular Exponentiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACNS ![In: Applied Cryptography and Network Security, First International Conference, ACNS 2003. Kunming, China, October 16-19, 2003, Proceedings, pp. 319-330, 2003, Springer, 3-540-20208-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Parallel modular exponentiation, Side channel attack, Montgomery multiplication, Timing attack, RSA cryptosystems |
28 | Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin |
Timing driven force directed placement with physical net constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 60-66, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
net constraints, timing driven placement, force directed placement |
28 | Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak |
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 668-673, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
delay ATPG, delay fault diagnosis, statistical timing models |
28 | Seokjin Lee, D. F. Wong 0001 |
Timing-driven routing for FPGAs based on Lagrangian relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 176-181, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
timing-driven routing, FPGA, Lagrangian relaxation |
28 | Oded Goldreich 0001 |
Concurrent zero-knowledge with timing, revisited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings on 34th Annual ACM Symposium on Theory of Computing, May 19-21, 2002, Montréal, Québec, Canada, pp. 332-340, 2002, ACM, 1-58113-495-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
black-box simulation, proofs versus arguments, timing assumptions, zero-Knowledge, parallel composition, concurrent composition |
28 | Jörg Fischer 0002, Stefan Conrad 0001 |
Formalizing Timing Diagrams as Causal Dependencies for Verification Purposes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFM ![In: Integrated Formal Methods, Second International Conference, IFM 2000, Dagstuhl Castle, Germany, November 1-3, 2000, Proceedings, pp. 45-60, 2000, Springer, 3-540-41196-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hardware and software design, relational semantics, formal semantics, dynamic logic, timing diagrams, integrated verification, causal dependencies |
28 | Peivand F. Tehrani, Shang Woo Chyou, Uma Ekambaram |
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 505-512, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
simulation, VLSI, timing, Crosstalk, DSM, static, transistor |
28 | Byungwoo Choi, D. M. H. Walker |
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 49-54, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
interconnect coupling, delay fault model, process variation, timing analysis, delay fault test |
28 | Werner Schindler |
A Timing Attack against RSA with the Chinese Remainder Theorem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2000, Second International Workshop, Worcester, MA, USA, August 17-18, 2000, Proceedings, pp. 109-124, 2000, Springer, 3-540-41455-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RSA, Chinese Remainder Theorem, Montgomery multiplication, Timing attack |
28 | Helena Handschuh, Howard M. Heys |
A Timing Attack on RC5. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Selected Areas in Cryptography ![In: Selected Areas in Cryptography '98, SAC'98, Kingston, Ontario, Canada, August 17-18, 1998, Proceedings, pp. 306-318, 1998, Springer, 3-540-65894-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Cryptanalysis, Block Cipher, Timing Attacks |
28 | Maroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel |
Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 796-802, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Waveforms, Graph Dominators, Domain narrowing, Formal Verification, Timing Verification, Combinational Logic circuits |
28 | Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton |
Approximate timing analysis of combinational circuits under the XBD0 model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 176-181, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
delay computation, timing analysis, False path |
28 | Minsoo Ryu, Seongsoo Hong, Manas Saksena |
Streamlining real-time controller design: From performance specifications to end-to-end timing constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 3rd IEEE Real-Time Technology and Applications Symposium, RTAS '97, Montreal, Canada, June 9-11, 1997, pp. 91-99, 1997, IEEE Computer Society, 0-8186-8016-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
real-time controller design, performance specifications, end-to-end timing constraints, control theoretic approach, schedulability constraint, control output responses, steady state error maximum overshoot, rise time, loop processing periods, input-to-output latency, heuristic optimization algorithm, embedded real-time controller, period calibration method, real-time systems, performance requirements, control performance, real-time control system, temporal requirements, settling time |
28 | Paul C. Kocher |
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO '96, 16th Annual International Cryptology Conference, Santa Barbara, California, USA, August 18-22, 1996, Proceedings, pp. 104-113, 1996, Springer, 3-540-61512-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
cryptanalysis, DSS, RSA, Timing attack, Diffie-Hellman |
28 | Sheng-Tzong Cheng, Chia-Mei Chen |
A Cyclic Scheduling for Relative Timing Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 2nd IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '96), 21-25 October 1996, Montreal, Canada, pp. 160-163, 1996, IEEE Computer Society, 0-8186-7614-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
relative timing constraints, Scheduling, real-time, jitters, allocation |
28 | Jaewon Kim, Sung-Mo Kang |
A timing-driven data path layout synthesis with integer programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 716-719, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
routing, integer programming, timing-driven placement, data path, bit-slice |
28 | P. Johannes, P. Das, Luc J. M. Claesen, Hugo De Man |
SLOCOP-II: a versatile timing verification system for MOSVLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 518-523, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Static timing verification |
28 | Abhik Sarkar, Frank Mueller 0001, Harini Ramaprasad, Sibin Mohan |
Push-assisted migration of real-time tasks in multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 80-89, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
task migration., real-time systems, timing analysis, multi-core architectures |
28 | Joachim Haß, Stefan Blaschke, Thomas Rammsayer, J. Michael Herrmann |
A neurocomputational model for optimal temporal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Neurosci. ![In: J. Comput. Neurosci. 25(3), pp. 449-464, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Representation of time, Synaptic competition, STDP, Timing errors, Synfire chains |
28 | Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen |
Sensitivity guided net weighting for placement driven synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 124-131, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight |
28 | Haoxing Ren, David Zhigang Pan, David S. Kung 0001 |
Sensitivity guided net weighting for placement driven synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 10-17, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight |
28 | Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev |
Formal Verification of Safety Properties in Timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 2-11, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Formal verification, asynchronous circuits, timing analysis |
27 | Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou 0001 |
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 486-491, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang |
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 148-159, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula |
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 125-137, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | William R. Roberts, Dimitrios Velenis |
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 508-517, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Masahiro Murakawa, Eiichi Takahashi, Tatsuya Susa, Tetsuya Higuchi |
Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC (4) ![In: Proceedings of the IEEE International Conference on Systems, Man & Cybernetics: The Hague, Netherlands, 10-13 October 2004, pp. 3670-3674, 2004, IEEE, 0-7803-8566-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Howard Chen 0001, Daniel L. Ostapko |
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 809-818, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long |
Timing Yield Estimation from Static Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 437-442, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Min Zhao 0001, Sachin S. Sapatnekar |
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1322-1336, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Jacques Benkoski, Andrzej J. Strojwas |
Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 668-673, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
27 | Huaiyu Zhu 0002, Yong Chen 0001, Xian-He Sun |
Timing local streams: improving timeliness in data prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 169-178, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
prefetching performance, prefetching simulation, cache memory, data prefetching |
27 | Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim |
Statistical static timing analysis considering leakage variability in power gated designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 57-62, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
process variations, leakage, power gating, ssta |
27 | Gregor Leander, Erik Zenner, Philip Hawkes |
Cache Timing Analysis of LFSR-Based Stream Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMACC ![In: Cryptography and Coding, 12th IMA International Conference, Cryptography and Coding 2009, Cirencester, UK, December 15-17, 2009. Proceedings, pp. 433-445, 2009, Springer, 978-3-642-10867-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki |
Safe clocking for the setup and hold timing constraints in datapath synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 27-32, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ordered clocking, register assignment, datapath synthesis |
27 | Lei Ju 0001, Bach Khoa Huynh, Samarjit Chakraborty, Abhik Roychoudhury |
Context-sensitive timing analysis of Esterel programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 870-873, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
worst-case execution time (WCET) analysis, Esterel, synchronous programming |
27 | David A. Papa, Tao Luo 0002, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li 0001, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov |
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12), pp. 2156-2168, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Jin-Tai Yan |
Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 26:1-26:18, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
octilinear Steiner tree, Global routing, Elmore delay, Steiner points |
27 | Sebastian Altmeyer, Christian Humbert, Björn Lisper, Reinhard Wilhelm |
Parametric Timing Analysis for Complex Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: The Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2008, Kaohisung, Taiwan, 25-27 August 2008, Proceedings, pp. 367-376, 2008, IEEE Computer Society, 978-0-7695-3349-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Farinaz Koushanfar, Petros Boufounos, Davood Shamsi |
Post-silicon timing characterization by compressed sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 185-189, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | An Hu, Fei Yuan |
Inter-signal timing skew compensation of parallel links with voltage-mode incremental signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1740-1743, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham |
A timing methodology considering within-die clock skew variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 351-356, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Ke Cao, Jiang Hu, Mosong Cheng |
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(12), pp. 1332-1340, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Yuki Wakuda, Akiko Noda, Kosuke Sekiyama, Yasuhisa Hasegawa, Toshio Fukuda |
Biorhythm-Based Awakening Timing Modulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2007 IEEE International Conference on Robotics and Automation, ICRA 2007, 10-14 April 2007, Roma, Italy, pp. 1232-1237, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Ruiming Chen, Hai Zhou 0001 |
Timing budgeting under arbitrary process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 344-349, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Hongjiang Wang, Fei Ji, Shengming Jiang, Liying Huang, Gang Wei |
stability analysis of timing acquisition methods with multi-hypothesis in indoor UWB multipath and MAI channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SNPD (3) ![In: Proceedings of the 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2007, July 30 - August 1, 2007, Qingdao, China, pp. 478-483, 2007, IEEE Computer Society, 0-7695-2909-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Tim Schattkowsky, Gregor Engels, Alexander Förster |
A Model-Based Approach for Platform-Independent Binary Components with Precise Timing and Fine-Grained Concurrency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 40th Hawaii International International Conference on Systems Science (HICSS-40 2007), CD-ROM / Abstracts Proceedings, 3-6 January 2007, Waikoloa, Big Island, HI, USA, pp. 286, 2007, IEEE Computer Society, 0-7695-2755-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Ricardo de Moraes, Paulo Portugal, Stefano Vitturi, Francisco Vasques, Pedro F. Souto |
Real-Time Communication in IEEE 802.11 Networks: Timing Analysis and a Ring Management Scheme for the VTP-CSMA Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: 32nd Annual IEEE Conference on Local Computer Networks (LCN 2007), 15-18 October 2007, Clontarf Castle, Dublin, Ireland, Proceedings, pp. 107-116, 2007, IEEE Computer Society, 0-7695-3000-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski |
Test Generation in the Presence of Timing Exceptions and Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 688-693, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert |
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(4), pp. 370-379, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Debjit Sinha, Hai Zhou 0001 |
Gate-size optimization under timing constraints for coupling-noise reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6), pp. 1064-1074, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen |
Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2437-2449, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Uzoma Onunkwo, Ye (Geoffrey) Li, Ananthram Swami |
Effect of timing jitter on OFDM-based UWB systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 24(4), pp. 787-793, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Yeonsu Kang, Do-Seob Ahn, Ho-Jin Lee |
OFDM channel estimation with timing offset for satellite plus terrestrial multipath channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 63rd IEEE Vehicular Technology Conference, VTC Spring 2006, 7-10 May 2006, Melbourne, Australia, pp. 2592-2596, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Rafik Henia, Rolf Ernst |
Improved offset-analysis using multiple timing-references. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 450-455, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
Parameterized block-based non-gaussian statistical gate timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 947-952, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Minsik Cho, David Z. Pan, Hua Xiang 0001, Ruchir Puri |
Wire density driven global routing for CMP variation and timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 487-492, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
performance, VLSI, manufacturability, global routing |
27 | Honguk Woo, Aloysius K. Mok, Chan-Gun Lee |
A Generic Framework for Monitoring Timing Constraints over Uncertain Events. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), 5-8 December 2006, Rio de Janeiro, Brazil, pp. 435-444, 2006, IEEE Computer Society, 0-7695-2761-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen |
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 147-152, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Tao Luo 0002, David Newmark, David Z. Pan |
A new LP based incremental timing driven placement for high performance designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1115-1120, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Sibin Mohan, Frank Mueller 0001, William Hawkins, Michael Root, Christopher A. Healy, David B. Whalley |
ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 26th IEEE Real-Time Systems Symposium (RTSS 2005), 6-8 December 2005, Miami, FL, USA, pp. 233-242, 2005, IEEE Computer Society, 0-7695-2490-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Jingyu Xu, Xianlong Hong, Tong Jing |
Timing-driven global routing with efficient buffer insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2449-2452, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Hao Zhou, Yih-Fang Huang |
Fine timing synchronization using power delay profile for OFDM systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2623-2626, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng |
Critical path selection for delay fault testing based upon a statistical timing model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11), pp. 1550-1565, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
Delay Fault Diagnosis Using Timing Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 485-490, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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