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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9063 occurrences of 3443 keywords
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Results
Found 16149 publication records. Showing 16145 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Mary L. Bailey |
A time-based model for investigating parallel logic-level simulation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
30 | Byron Krauter, David Widiger |
Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
GCD frequency, LCM window, frequency-dependent noise, timing orthogonality, crosstalk, noise analysis, timing windows |
30 | Abhijit Das |
On the Transistor Sizing Problem. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
Timing Analysis, Timing Optimization, Transistor Sizing, Delay Constraint |
30 | Chanjung Park, Seog Park |
A multiversion locking protocol for real-time databases with multilevel security. |
RTCSA |
1996 |
DBLP DOI BibTeX RDF |
multiversion locking protocol, processes transactions, explicit timing constraints, logical data consistency, compatibility matrix, version selection algorithm, data integrity, timing constraints, multilevel security, real-time databases, temporal consistency |
30 | Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng |
Automatic synthesis of gate-level timed circuits with choice. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates |
30 | Bernd J. Krämer, Luqi, Valdis Berzins |
Compositional Semantics of a Real-Time Prototyping Language. |
IEEE Trans. Software Eng. |
1993 |
DBLP DOI BibTeX RDF |
real-time prototyping language, PSDL, data flow notation, application-orientation timing, control constraints, algebraic high-level Petri nets, concurrency concepts, real-time systems, formal specification, Petri nets, synchronization, specification languages, abstract data types, abstract data types, formal semantics, algebraic specifications, software prototyping, hard real-time systems, compositional semantics, timing behavior |
29 | Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng |
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
critical path selection, statistical timing analysis, false path |
28 | John Sartori, Rakesh Kumar 0002 |
Overscaling-friendly timing speculation architectures. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
stochastic processors, timing speculation, adaptability |
28 | Guihai Yan, Xiaoyao Liang, Yinhe Han 0001, Xiaowei Li 0001 |
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
complimentary effects, delay sensor, pvt variations, timing emergency, thread migration |
28 | Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li |
Static timing analysis for flexible TFT circuits. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
flexible electronics, static timing analysis |
28 | Scott A. Crosby, Dan S. Wallach, Rudolf H. Riedi |
Opportunities and Limits of Remote Timing Attacks. |
ACM Trans. Inf. Syst. Secur. |
2009 |
DBLP DOI BibTeX RDF |
jitter, timing attacks, Information leakage |
28 | Eun Cheol Kim, Jae Sang Cha, Jin Young Kim 0001, Young Dae Lee, YouSik Hong, Jeong Jin Kang |
Robust timing jitter control method for network synchronization. |
ICHIT |
2009 |
DBLP DOI BibTeX RDF |
network synchronization, slave, timing jitter control, delay, master |
28 | Wei Dong, Jiandong Li 0001, Zhuo Lu |
Joint timing error, frequency offset and channel estimation for MIMO systems. |
IWCMC |
2009 |
DBLP DOI BibTeX RDF |
frequency offset, MIMO, channel estimation, timing error |
28 | Billy Bob Brumley, Risto M. Hakala |
Cache-Timing Template Attacks. |
ASIACRYPT |
2009 |
DBLP DOI BibTeX RDF |
cache-timing attacks, elliptic curve cryptography, side channel attacks |
28 | Emilia Käsper, Peter Schwabe |
Faster and Timing-Attack Resistant AES-GCM. |
CHES |
2009 |
DBLP DOI BibTeX RDF |
Galois/Counter mode, cache-timing attacks, AES, fast implementations |
28 | Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik |
A parametric approach for handling local variation effects in timing analysis. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
on chip variation (OCV), timing, parametric analysis |
28 | Mihir R. Choudhury, Kartik Mohanram |
Timing-driven optimization using lookahead logic circuits. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
logic synthesis, timing optimization, lookahead |
28 | Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty |
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
design space exploration, timing analysis, automotive |
28 | Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu |
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Verilog-AMS, Static timing analysis, Look-up table |
28 | Hao Li, Yue Zhuo |
Criticality history guided FPGA placement algorithm for timing optimization. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
fpga, placement, timing optimization |
28 | Safar Hatami, Hamed Abrishami, Massoud Pedram |
Statistical timing analysis of flip-flops considering codependent setup and hold times. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
codependency, hold time, piecewise linear, statistical static timing analysis (SSTA), probability, process variations, setup time |
28 | Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir |
Statistical diagnosis of unmodeled systematic timing effects. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
statistical diagnosis, learning, timing, delay test |
28 | Onur Aciiçmez, Werner Schindler, Çetin Kaya Koç |
Cache Based Remote Timing Attack on the AES. |
CT-RSA |
2007 |
DBLP DOI BibTeX RDF |
Remote Attack, AES, Timing Analysis, Side Channel Analysis, Cache Attack |
28 | Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang |
Timing-driven Steiner trees are (practically) free. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
arborescence, timing-driven, rectilinear Steiner tree |
28 | Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei |
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis |
28 | Onur Aciiçmez, Werner Schindler, Çetin Kaya Koç |
Improving Brumley and Boneh timing attack on unprotected SSL implementations. |
CCS |
2005 |
DBLP DOI BibTeX RDF |
RSA, timing attacks, side-channel cryptanalysis |
28 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay |
28 | Yaping Zhan, Andrzej J. Strojwas, Xin Li 0001, Lawrence T. Pileggi, David Newmark, Mahesh Sharma |
Correlation-aware statistical timing analysis with non-gaussian delay distributions. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
process variation, statistical timing |
28 | Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail |
Statistical static timing analysis: how simple can we get? |
DAC |
2005 |
DBLP DOI BibTeX RDF |
statistical static timing analysis (SSTA), process variations |
28 | Serdar Cabuk, Carla E. Brodley, Clay Shields |
IP covert timing channels: design and detection. |
CCS |
2004 |
DBLP DOI BibTeX RDF |
network covert channels, TCP/IP, detection, covert timing channels |
28 | Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein |
RESTA: a robust and extendable symbolic timing analysis tool. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
input constraints, symbolic CAD, timing analysis, decision diagrams |
28 | An Yu, David S. Brée |
A Clock-less Implementation of the AES Resists to Power and Timing Attacks. |
ITCC (2) |
2004 |
DBLP DOI BibTeX RDF |
clock-less circuits, AES, timing attacks, cryptosystems, power attacks |
28 | Jiayong Le, Xin Li 0001, Lawrence T. Pileggi |
STAC: statistical timing analysis with correlation. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
process variation, statistical timing |
28 | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha |
Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
communication devices test, high frequency test, jitter test, timing jitter |
28 | Jia Xu |
Making Software Timing Properties Easier to Inspect and Verify. |
IEEE Softw. |
2003 |
DBLP DOI BibTeX RDF |
preruntime scheduling, verification, real time, predictability, software, code, inspection, undecidability, timing properties, state space explosion |
28 | Yasuyuki Sakai, Kouichi Sakurai |
Timing Attack against Implementation of a Parallel Algorithm for Modular Exponentiation. |
ACNS |
2003 |
DBLP DOI BibTeX RDF |
Parallel modular exponentiation, Side channel attack, Montgomery multiplication, Timing attack, RSA cryptosystems |
28 | Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin |
Timing driven force directed placement with physical net constraints. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
net constraints, timing driven placement, force directed placement |
28 | Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak |
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
delay ATPG, delay fault diagnosis, statistical timing models |
28 | Seokjin Lee, D. F. Wong 0001 |
Timing-driven routing for FPGAs based on Lagrangian relaxation. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
timing-driven routing, FPGA, Lagrangian relaxation |
28 | Oded Goldreich 0001 |
Concurrent zero-knowledge with timing, revisited. |
STOC |
2002 |
DBLP DOI BibTeX RDF |
black-box simulation, proofs versus arguments, timing assumptions, zero-Knowledge, parallel composition, concurrent composition |
28 | Jörg Fischer 0002, Stefan Conrad 0001 |
Formalizing Timing Diagrams as Causal Dependencies for Verification Purposes. |
IFM |
2000 |
DBLP DOI BibTeX RDF |
hardware and software design, relational semantics, formal semantics, dynamic logic, timing diagrams, integrated verification, causal dependencies |
28 | Peivand F. Tehrani, Shang Woo Chyou, Uma Ekambaram |
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
simulation, VLSI, timing, Crosstalk, DSM, static, transistor |
28 | Byungwoo Choi, D. M. H. Walker |
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
interconnect coupling, delay fault model, process variation, timing analysis, delay fault test |
28 | Werner Schindler |
A Timing Attack against RSA with the Chinese Remainder Theorem. |
CHES |
2000 |
DBLP DOI BibTeX RDF |
RSA, Chinese Remainder Theorem, Montgomery multiplication, Timing attack |
28 | Helena Handschuh, Howard M. Heys |
A Timing Attack on RC5. |
Selected Areas in Cryptography |
1998 |
DBLP DOI BibTeX RDF |
Cryptanalysis, Block Cipher, Timing Attacks |
28 | Maroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel |
Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Waveforms, Graph Dominators, Domain narrowing, Formal Verification, Timing Verification, Combinational Logic circuits |
28 | Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton |
Approximate timing analysis of combinational circuits under the XBD0 model. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
delay computation, timing analysis, False path |
28 | Minsoo Ryu, Seongsoo Hong, Manas Saksena |
Streamlining real-time controller design: From performance specifications to end-to-end timing constraints. |
IEEE Real Time Technology and Applications Symposium |
1997 |
DBLP DOI BibTeX RDF |
real-time controller design, performance specifications, end-to-end timing constraints, control theoretic approach, schedulability constraint, control output responses, steady state error maximum overshoot, rise time, loop processing periods, input-to-output latency, heuristic optimization algorithm, embedded real-time controller, period calibration method, real-time systems, performance requirements, control performance, real-time control system, temporal requirements, settling time |
28 | Paul C. Kocher |
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems. |
CRYPTO |
1996 |
DBLP DOI BibTeX RDF |
cryptanalysis, DSS, RSA, Timing attack, Diffie-Hellman |
28 | Sheng-Tzong Cheng, Chia-Mei Chen |
A Cyclic Scheduling for Relative Timing Requirements. |
ICECCS |
1996 |
DBLP DOI BibTeX RDF |
relative timing constraints, Scheduling, real-time, jitters, allocation |
28 | Jaewon Kim, Sung-Mo Kang |
A timing-driven data path layout synthesis with integer programming. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
routing, integer programming, timing-driven placement, data path, bit-slice |
28 | P. Johannes, P. Das, Luc J. M. Claesen, Hugo De Man |
SLOCOP-II: a versatile timing verification system for MOSVLSI. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
Static timing verification |
28 | Abhik Sarkar, Frank Mueller 0001, Harini Ramaprasad, Sibin Mohan |
Push-assisted migration of real-time tasks in multi-core processors. |
LCTES |
2009 |
DBLP DOI BibTeX RDF |
task migration., real-time systems, timing analysis, multi-core architectures |
28 | Joachim Haß, Stefan Blaschke, Thomas Rammsayer, J. Michael Herrmann |
A neurocomputational model for optimal temporal processing. |
J. Comput. Neurosci. |
2008 |
DBLP DOI BibTeX RDF |
Representation of time, Synaptic competition, STDP, Timing errors, Synfire chains |
28 | Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen |
Sensitivity guided net weighting for placement driven synthesis. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight |
28 | Haoxing Ren, David Zhigang Pan, David S. Kung 0001 |
Sensitivity guided net weighting for placement driven synthesis. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight |
28 | Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev |
Formal Verification of Safety Properties in Timed Circuits. |
ASYNC |
2000 |
DBLP DOI BibTeX RDF |
Formal verification, asynchronous circuits, timing analysis |
27 | Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou 0001 |
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang |
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula |
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | William R. Roberts, Dimitrios Velenis |
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Masahiro Murakawa, Eiichi Takahashi, Tatsuya Susa, Tetsuya Higuchi |
Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins. |
SMC (4) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Howard Chen 0001, Daniel L. Ostapko |
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long |
Timing Yield Estimation from Static Timing Analysis. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Min Zhao 0001, Sachin S. Sapatnekar |
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Jacques Benkoski, Andrzej J. Strojwas |
Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
27 | Huaiyu Zhu 0002, Yong Chen 0001, Xian-He Sun |
Timing local streams: improving timeliness in data prefetching. |
ICS |
2010 |
DBLP DOI BibTeX RDF |
prefetching performance, prefetching simulation, cache memory, data prefetching |
27 | Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim |
Statistical static timing analysis considering leakage variability in power gated designs. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
process variations, leakage, power gating, ssta |
27 | Gregor Leander, Erik Zenner, Philip Hawkes |
Cache Timing Analysis of LFSR-Based Stream Ciphers. |
IMACC |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki |
Safe clocking for the setup and hold timing constraints in datapath synthesis. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
ordered clocking, register assignment, datapath synthesis |
27 | Lei Ju 0001, Bach Khoa Huynh, Samarjit Chakraborty, Abhik Roychoudhury |
Context-sensitive timing analysis of Esterel programs. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
worst-case execution time (WCET) analysis, Esterel, synchronous programming |
27 | David A. Papa, Tao Luo 0002, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li 0001, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov |
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Jin-Tai Yan |
Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
octilinear Steiner tree, Global routing, Elmore delay, Steiner points |
27 | Sebastian Altmeyer, Christian Humbert, Björn Lisper, Reinhard Wilhelm |
Parametric Timing Analysis for Complex Architectures. |
RTCSA |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Farinaz Koushanfar, Petros Boufounos, Davood Shamsi |
Post-silicon timing characterization by compressed sensing. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
27 | An Hu, Fei Yuan |
Inter-signal timing skew compensation of parallel links with voltage-mode incremental signaling. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham |
A timing methodology considering within-die clock skew variations. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Ke Cao, Jiang Hu, Mosong Cheng |
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Yuki Wakuda, Akiko Noda, Kosuke Sekiyama, Yasuhisa Hasegawa, Toshio Fukuda |
Biorhythm-Based Awakening Timing Modulation. |
ICRA |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Ruiming Chen, Hai Zhou 0001 |
Timing budgeting under arbitrary process variations. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Hongjiang Wang, Fei Ji, Shengming Jiang, Liying Huang, Gang Wei |
stability analysis of timing acquisition methods with multi-hypothesis in indoor UWB multipath and MAI channel. |
SNPD (3) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Tim Schattkowsky, Gregor Engels, Alexander Förster |
A Model-Based Approach for Platform-Independent Binary Components with Precise Timing and Fine-Grained Concurrency. |
HICSS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Ricardo de Moraes, Paulo Portugal, Stefano Vitturi, Francisco Vasques, Pedro F. Souto |
Real-Time Communication in IEEE 802.11 Networks: Timing Analysis and a Ring Management Scheme for the VTP-CSMA Architecture. |
LCN |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski |
Test Generation in the Presence of Timing Exceptions and Constraints. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert |
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Debjit Sinha, Hai Zhou 0001 |
Gate-size optimization under timing constraints for coupling-noise reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen |
Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Uzoma Onunkwo, Ye (Geoffrey) Li, Ananthram Swami |
Effect of timing jitter on OFDM-based UWB systems. |
IEEE J. Sel. Areas Commun. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Yeonsu Kang, Do-Seob Ahn, Ho-Jin Lee |
OFDM channel estimation with timing offset for satellite plus terrestrial multipath channels. |
VTC Spring |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Rafik Henia, Rolf Ernst |
Improved offset-analysis using multiple timing-references. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
Parameterized block-based non-gaussian statistical gate timing analysis. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Minsik Cho, David Z. Pan, Hua Xiang 0001, Ruchir Puri |
Wire density driven global routing for CMP variation and timing. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
performance, VLSI, manufacturability, global routing |
27 | Honguk Woo, Aloysius K. Mok, Chan-Gun Lee |
A Generic Framework for Monitoring Timing Constraints over Uncertain Events. |
RTSS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen |
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Tao Luo 0002, David Newmark, David Z. Pan |
A new LP based incremental timing driven placement for high performance designs. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Sibin Mohan, Frank Mueller 0001, William Hawkins, Michael Root, Christopher A. Healy, David B. Whalley |
ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling. |
RTSS |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Jingyu Xu, Xianlong Hong, Tong Jing |
Timing-driven global routing with efficient buffer insertion. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Hao Zhou, Yih-Fang Huang |
Fine timing synchronization using power delay profile for OFDM systems. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng |
Critical path selection for delay fault testing based upon a statistical timing model. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
Delay Fault Diagnosis Using Timing Information. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
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