Search results for "ETS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Irith Pomeranz, Sudhakar M. Reddy	Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation.	ETS	2009	DBLP DOI BibTeX RDF
1	Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso, Edgar E. Sánchez, Matteo Sonza Reorda	Automatic Functional Stress Pattern Generation for SoC Reliability Characterization.	ETS	2009	DBLP DOI BibTeX RDF	SoC reliability characterization
1	Janusz Rajski	We Have Got Compression, What Next?	ETS	2009	DBLP DOI BibTeX RDF
1	Rajeshwary Tayade, Jacob A. Abraham	Critical Path Selection for Delay Test Considering Coupling Noise.	ETS	2009	DBLP DOI BibTeX RDF
1	Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich	Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead.	ETS	2009	DBLP DOI BibTeX RDF	Concurrent self test, test generation, BIST
1	Sehun Kook, Vishwanath Natarajan, Abhijit Chatterjee, Shalabh Goyal, Le Jin	Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function Estimation.	ETS	2009	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean-Michel Portal, Christophe Muller	Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections.	ETS	2009	DBLP DOI BibTeX RDF	ReRAM, Defect Injection, Electrical Simulation, Memory Testing
1	Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara	Partial Scan Approach for Secret Information Protection.	ETS	2009	DBLP DOI BibTeX RDF	Cryptographic circuits, Security, Testability, Balanced structure
1	Frank-Uwe Faber, Matthias Beck, Markus Rudack, Olivier Barondeau, Thomas Rabenalt, Michael Gössel, Andreas Leininger	Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment.	ETS	2009	DBLP DOI BibTeX RDF
1	Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal	On Minimization of Peak Power for Scan Circuit during Test.	ETS	2009	DBLP DOI BibTeX RDF	Power droop, Test vector re-ordering, Low power test, Peak Power
1	Mohammed Ashfaq Shukoor, Vishwani D. Agrawal	A Two Phase Approach for Minimal Diagnostic Test Set Generation.	ETS	2009	DBLP DOI BibTeX RDF	generalized fault independence, Fault diagnosis, integer linear programming, fault dictionary, test minimization
1	Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar	Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors.	ETS	2009	DBLP DOI BibTeX RDF	Chip multithreading, micro-processor testing, functional self-testing, test time optimization, multiprocessors, software-based self-testing
1	Stephan Eggersglüß, Rolf Drechsler	Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques.	ETS	2009	DBLP DOI BibTeX RDF	ATPG, SAT, Delay Test, Boolean Satisfiability, Dynamic Learning
1	Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai	Speed-Path Debug Using At-Speed Scan Test Patterns.	ETS	2009	DBLP DOI BibTeX RDF
1		14th IEEE European Test Symposium, ETS 2009, Sevilla, Spain, May 25-29, 2009	ETS	2009	DBLP BibTeX RDF
1	Christian Landrault	Something I Always Wanted to Know About Test, But Was Afraid to Ask.	ETS	2009	DBLP DOI BibTeX RDF
1	Kihyuk Han, Joonsung Park, Jae Wook Lee, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh	Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.	ETS	2009	DBLP DOI BibTeX RDF
1	Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev	Defect Filter for Alternate RF Test.	ETS	2009	DBLP DOI BibTeX RDF	alternate test, defect filter, density estimation, RF test
1	Vezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner	Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications.	ETS	2009	DBLP DOI BibTeX RDF	Gate Stress Test, Gate Oxide Reliability, Low Side Switch, Burn-In
1	Josep Rius 0001, Luis Elvira Villagra, Maurice Meijer	A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits.	ETS	2009	DBLP DOI BibTeX RDF	IDDQ testing
1	Ho Fai Ko, Nicola Nicolici	Resource-Efficient Programmable Trigger Units for Post-Silicon Validation.	ETS	2009	DBLP DOI BibTeX RDF	programmable trigger unit, false trigger analysis, post-silicon validation
1	Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido Gronthoud	Algorithms for ADC Multi-site Test with Digital Input Stimulus.	ETS	2009	DBLP DOI BibTeX RDF
1	Yasser Sedaghat, Seyed Ghassem Miremadi	Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers.	ETS	2009	DBLP DOI BibTeX RDF	FlexRay protocol, Fault injection, Distributed embedded systems, Safety-critical applications
1	Qais Al-Gayem, Hongyuan Liu 0001, Andrew Richardson 0001, Nick Burd	Built-in Test Solutions for the Electrode Structures in Bio-Fluidic Microsystems.	ETS	2009	DBLP DOI BibTeX RDF	bio-fluidics, MNT, self-test, microfluidics, embedded test
1	Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada	Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links.	ETS	2009	DBLP DOI BibTeX RDF	digitally-assisted adaptive equalizers, static signature-based testing, dynamic signature-based testing
1	Thomas Rabenalt, Michael Gössel, Andreas Leininger	Masking of X-values by Use of a Hierarchically Configurable Register.	ETS	2009	DBLP DOI BibTeX RDF	X-values, X-masking, DFT
1	Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich	Test Encoding for Extreme Response Compaction.	ETS	2009	DBLP DOI BibTeX RDF	Embedded Diagnosis, Design for Test, Test Compression, Response Compaction
1	Vladimir A. Zivkovic, Frank van der Heyden, Guido Gronthoud, Frans G. M. de Jong	Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design.	ETS	2008	DBLP DOI BibTeX RDF	Modular Test, Analog Test, Test Architecture
1	Rajarajan Senguttuvan, Hyun Woo Choi, Donghoon Han, Abhijit Chatterjee	Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass Filters.	ETS	2008	DBLP DOI BibTeX RDF
1	Swapnil Bahl, Vishal Srivastava	Self-Programmable Shared BIST for Testing Multiple Memories.	ETS	2008	DBLP DOI BibTeX RDF	Memory testing and Semiconductor memory, Built-in Self-test (BIST), Pipeline architecture
1	Martin Hilscher, Michael Braun, Michael Richter 0002, Andreas Leininger, Michael Gössel	Accelerated Shift Registers for X-tolerant Test Data Compaction.	ETS	2008	DBLP DOI BibTeX RDF	X-tolerant, Test Compaction, MISR
1	Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre	A Reliable Architecture for the Advanced Encryption Standard.	ETS	2008	DBLP DOI BibTeX RDF	AES cryptochip, On-Line Self-Test, Reliability
1	Nathan Kupp, Petros Drineas, Mustapha Slamani, Yiorgos Makris	Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction.	ETS	2008	DBLP DOI BibTeX RDF
1	Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli	Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories.	ETS	2008	DBLP DOI BibTeX RDF	NOR flash memories, reliabilty management, markov modeling
1	Stefan Holst, Hans-Joachim Wunderlich	Adaptive Debug and Diagnosis without Fault Dictionaries.	ETS	2008	DBLP DOI BibTeX RDF	VLSI, Test, Debug, Diagnosis
1	Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja	A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.	ETS	2008	DBLP DOI BibTeX RDF	At-Speed Scan Testing, Test Relaxation, X-Filling, Capture Mode, Yield Loss
1	Rajeshwary Tayade, Jacob A. Abraham	Critical Path Selection for Delay Test Considering Coupling Noise.	ETS	2008	DBLP DOI BibTeX RDF	Coupling noise, weighted partial max sat, critical path selection, delay test
1	Esa Korhonen, Juha Kostamovaara	An Improved Algorithm to Identify the Test Stimulus in Histogram-Based A/D Converter Testing.	ETS	2008	DBLP DOI BibTeX RDF	histogram test, integral non-linearity (INL), stimulus identification, built-in self-test (BIST), A/D converter (ADC)
1	Laura Frigerio, Matteo Alan Radaelli, Fabio Salice	Convolutional Coding for SEU mitigation.	ETS	2008	DBLP DOI BibTeX RDF	SEU mitigation, convolutional coding
1	Seongmoon Wang, Wenlong Wei	Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns.	ETS	2008	DBLP DOI BibTeX RDF	Transition delay fault, broadside, skewed-load, enhanced scan
1	Cecilia Metra, Daniele Rossi 0001, Martin Omaña 0001, Abhijit Jas, Rajesh Galivanche	Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.	ETS	2008	DBLP DOI BibTeX RDF	microprocessor, error detecting codes, on-line testing, control logic
1	Eduardo Aldrete-Vidrio, M. Amine Salhi, Josep Altet, Stéphane Grauby, Diego Mateo, H. Michel, L. Clerjaud, Jean-Michel Rampnoux, Antonio Rubio 0001, Wilfrid Claeys, Stefan Dilhaire	Using Temperature as Observable of the Frequency Response of RF CMOS Amplifiers.	ETS	2008	DBLP DOI BibTeX RDF	system debug, analog test, Thermal test, RF test, temperature measurements
1	Antonio Rubio 0001	The Role of Test in Circuits Built with Unreliable Components.	ETS	2008	DBLP DOI BibTeX RDF
1		13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008	ETS	2008	DBLP BibTeX RDF
1	Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso	An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs.	ETS	2008	DBLP DOI BibTeX RDF	reliability characterization, dft, soc
1	Yu Huang 0005, Wu-Tung Cheng, Ruifeng Guo	Diagnose Multiple Stuck-at Scan Chain Faults.	ETS	2008	DBLP DOI BibTeX RDF	chain diagnosis, multiple faults, dynamic learning
1	Daniele Rossi 0001, Paolo Angelini, Cecilia Metra, Giovanni Campardo, Gian Pietro Vanalli	Risks for Signal Integrity in System in Package and Possible Remedies.	ETS	2008	DBLP DOI BibTeX RDF	Crosstalk, Error Detecting Codes, Signal Integrity, System in Package
1	Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens	Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism.	ETS	2008	DBLP DOI BibTeX RDF	testing, reuse, modular, Network-on-Chip, integrated circuit, test access mechanism
1	Thomas W. Williams	The Future Is Low Power and Test.	ETS	2008	DBLP DOI BibTeX RDF
1	Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar	Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation.	ETS	2008	DBLP DOI BibTeX RDF	assertion checking, decision diagrams, Property Specification Language
1	Qingqi Dou, Jacob A. Abraham	Jitter Decomposition in High-Speed Communication Systems.	ETS	2008	DBLP DOI BibTeX RDF	Jitter Test, Jitter Analysis, Jitter Decomposition, Autocorrelation, Time domain
1	Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker 0001	Selective Hardening in Early Design Steps.	ETS	2008	DBLP DOI BibTeX RDF	Soft error mitigation, reliability
1	Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker 0001	A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.	ETS	2008	DBLP DOI BibTeX RDF	Small-delay defects, resistive opens, probabilistic fault coverage, bridging fault simulation
1	Irith Pomeranz, Sudhakar M. Reddy	Safe Fault Collapsing Based on Dominance Relations.	ETS	2008	DBLP DOI BibTeX RDF	test generation, bridging faults, fault collapsing, dominance relations
1	Quming Zhou, Mihir R. Choudhury, Kartik Mohanram	Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits.	ETS	2008	DBLP DOI BibTeX RDF	filters, soft errors, circuit optimization, radiation hardening, fault avoidance
1	Ehab Anis Daoud, Nicola Nicolici	On Bypassing Blocking Bugs during Post-Silicon Validation.	ETS	2008	DBLP DOI BibTeX RDF
1	Simone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino	Applying March Tests to K-Way Set-Associative Cache Memories.	ETS	2008	DBLP DOI BibTeX RDF	cache memories, memory test, march test
1	S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod	Bridge Defect Diagnosis for Multiple-Voltage Design.	ETS	2008	DBLP DOI BibTeX RDF	Logic based Diagnosis, Multiple-Vdd designs, Resistive Bridging Faults
1	Luca Sterpone, Massimo Violante	Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.	ETS	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Diagnostic Test Generation Based on Subsets of Faults.	ETS	2007	DBLP DOI BibTeX RDF
1	Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara	Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.	ETS	2007	DBLP DOI BibTeX RDF
1	Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab	Automatic Generation of Instructions to Robustly Test Delay Defects in Processors.	ETS	2007	DBLP DOI BibTeX RDF
1	Ivo Koren, Frank Demmerle, Roland May, Martin Kaibel, Sebastian Sattler	FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests.	ETS	2007	DBLP DOI BibTeX RDF
1	Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware	Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement.	ETS	2007	DBLP DOI BibTeX RDF
1	Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero	PPM Reduction on Embedded Memories in System on Chip.	ETS	2007	DBLP DOI BibTeX RDF	static faults, PPM reduction, memory testing, dynamic faults
1	Andreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	Selecting Power-Optimal SBST Routines for On-Line Processor Testing.	ETS	2007	DBLP DOI BibTeX RDF
1	Philippe Cauvet, Serge Bernard, Michel Renovell	System-in-Package, a Combination of Challenges and Solutions.	ETS	2007	DBLP DOI BibTeX RDF
1	Erik Schüler, Marcelo Negreiros, Pascal Nouet, Luigi Carro	A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter.	ETS	2007	DBLP DOI BibTeX RDF
1	Rene Segers	If It's All about Yield, Why Talk about Testing?	ETS	2007	DBLP DOI BibTeX RDF
1	Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich	An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.	ETS	2007	DBLP DOI BibTeX RDF
1	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Digital Generation of Signals for Low Cost RF BIST.	ETS	2007	DBLP DOI BibTeX RDF
1	Tao Xu 0002, Krishnendu Chakrabarty	Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips.	ETS	2007	DBLP DOI BibTeX RDF
1	Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek	Communication-Centric SoC Debug Using Transactions.	ETS	2007	DBLP DOI BibTeX RDF
1		12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007	ETS	2007	DBLP BibTeX RDF
1	Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel	Computation and Application of Absolute Dominators in Industrial Designs.	ETS	2007	DBLP DOI BibTeX RDF
1	Norbert Dumas, Zhou Xu, Kostas Georgopoulos, R. John T. Bunyan, Andrew Richardson 0001	A Novel Approach for Online Sensor Testing Based on an Encoded Test Stimulus.	ETS	2007	DBLP DOI BibTeX RDF	correlation, Online testing, covariance, pseudorandom sequence, MEMS testing
1	Klaus Luther	Embedded Tutorial: IC Test Cost Benchmarking.	ETS	2007	DBLP DOI BibTeX RDF	benchmarking, cost, best practice, test time
1	Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda	On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores.	ETS	2007	DBLP DOI BibTeX RDF
1	Nicola Nicolici, Xiaoqing Wen	Embedded Tutorial on Low Power Test.	ETS	2007	DBLP DOI BibTeX RDF
1	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.	ETS	2007	DBLP DOI BibTeX RDF
1	Stephen K. Sunter, Aubin Roy	Purely Digital BIST for Any PLL or DLL.	ETS	2007	DBLP DOI BibTeX RDF
1	Stefan Holst, Hans-Joachim Wunderlich	Adaptive Debug and Diagnosis without Fault Dictionaries.	ETS	2007	DBLP DOI BibTeX RDF	VLSI, Test, Debug, Diagnosis
1	Alexandre Rousset, Alberto Bosio, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	DERRIC: A Tool for Unified Logic Diagnosis.	ETS	2007	DBLP DOI BibTeX RDF
1	Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell	"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.	ETS	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.	ETS	2007	DBLP DOI BibTeX RDF
1	Peter C. Maxwell	Wafer Level Reliability Screens.	ETS	2007	DBLP DOI BibTeX RDF
1	Jaan Raik, Raimund Ubar, Vineeth Govind	Test Configurations for Diagnosing Faulty Links in NoC Switches.	ETS	2007	DBLP DOI BibTeX RDF
1	Ben Bennetts	Electronics Design-for-Test: Past, Present and Future.	ETS	2007	DBLP DOI BibTeX RDF
1	Shaji Krishnan, Rene Jonker, Leon van de Logt	Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives.	ETS	2007	DBLP DOI BibTeX RDF
1	Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara	Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.	ETS	2007	DBLP DOI BibTeX RDF	Dynamically reconfigurable processors, optimal contexts, test frames, self-test, test application time
1	Zhanglei Wang, Krishnendu Chakrabarty, Michael Bienek	A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression.	ETS	2007	DBLP DOI BibTeX RDF
1	Carlos Arthur Lang Lisbôa, Marcelo Ienczczak Erigson, Luigi Carro	System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies.	ETS	2007	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.	ETS	2007	DBLP DOI BibTeX RDF
1	Kentaroh Katoh, Hideo Ito	Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.	ETS	2006	DBLP DOI BibTeX RDF	Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
1	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi	Enhancing Delay Fault Coverage through Low Power Segmented Scan.	ETS	2006	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes 0001	Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.	ETS	2006	DBLP DOI BibTeX RDF
1	Matthew Collins, Bashir M. Al-Hashimi	On-Chip Time Measurement Architecture with Femtosecond Timing Resolution.	ETS	2006	DBLP DOI BibTeX RDF
1	Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez	Testing and Diagnosis of Power Switches in SOCs.	ETS	2006	DBLP DOI BibTeX RDF
1	Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers	Deterministic Logic BIST for Transition Fault Testing.	ETS	2006	DBLP DOI BibTeX RDF	Deterministic logic BIST, delay test
1	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena	Fault Injection-based Reliability Evaluation of SoPCs.	ETS	2006	DBLP DOI BibTeX RDF

Publications at "ETS"( http://dblp.L3S.de/Venues/ETS )