Search results for "LUT"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Jeongbin Kim 0001, Ki Tae Kim, Eui-Young Chung	CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA.	ICSCA	2018	DBLP DOI BibTeX RDF
17	Maike Taddiken, Theodor Hillebrand, Steffen Paul, Dagmar Peters-Drolshagen	LUT-Based Stochastic Modeling for Non-Normal Performance Distributions.	SMACD	2018	DBLP DOI BibTeX RDF
17	Yixiong Yang, Zhibo Wang 0004, Pei Yang, Meng-Fan Chang, Mon-Shu Ho, Huazhong Yang, Yongpan Liu	A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation.	ISCAS	2018	DBLP DOI BibTeX RDF
17	Minyoung Jeong, Jaeheum Lee, Eungu Jung, Young Hwan Kim, Kyoung-Rok Cho	Extract LUT Logics from a Downloaded Bitstream Data in FPGA.	ISCAS	2018	DBLP DOI BibTeX RDF
17	Jiayan Gan, Jun Zhou 0017, Ning Wang	A FPGA-based RO PUF with LUT-Based Self-Compare Structure and Adaptive Counter Time Period Tuning.	ISCAS	2018	DBLP DOI BibTeX RDF
17	Zihua Wu, Qiming Qin	Retrieving LAI and LCC Simultaneously from Sentinel-2 Data Using Prosail and PSO-Coupled BI-Lut.	IGARSS	2018	DBLP DOI BibTeX RDF
17	Alexander Barkalov 0001, Larysa Titarenko, Kamil Mielcarek	Twofold State Assignment for LUT-based Mealy FSMs.	MIXDES	2018	DBLP DOI BibTeX RDF
17	Alexander Barkalov 0001, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek	Encoding of Terms in LUT-based Mealy FSMs.	MIXDES	2018	DBLP DOI BibTeX RDF
17	Vishal Sharma 0004, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma	A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design.	VDAT	2018	DBLP DOI BibTeX RDF
17	Saeed Ghasemi, Jeison Tabares, Victor Polo 0001, Josep Prat	LUT-Free Carrier Recovery for Intradyne Optical DPSK Receivers in udWDM-PON.	ECOC	2018	DBLP DOI BibTeX RDF
17	Burhan Khurshid	LUT based realization of fixed-point multipliers targeting state-of-art FPGAs.	Des. Autom. Embed. Syst.	2017	DBLP DOI BibTeX RDF
17	Marcin Kubica, Dariusz Kania	Area-oriented technology mapping for LUT-based logic blocks.	Int. J. Appl. Math. Comput. Sci.	2017	DBLP DOI BibTeX RDF
17	Ahmet Kakacak, Aydin Emre Guzel, Ozan Cihangir, Sezer Gören 0001, H. Fatih Ugurdag	Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression.	Integr.	2017	DBLP DOI BibTeX RDF
17	Toshiki Higashi, Hiroyuki Ochi	Area-Efficient LUT-Like Programmable Logic Using Atom Switch and Its Delay-Optimal Mapping Algorithm.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
17	Burhan Khurshid, Roohie Naaz Mir	An Efficient FIR Filter Structure Based on Technology-Optimized Multiply-Adder Unit Targeting LUT-Based FPGAs.	Circuits Syst. Signal Process.	2017	DBLP DOI BibTeX RDF
17	Yoon-Jee Kim, Sung-Eun Cho, Ji-Yong Um, Min-Kyun Chae, Jihoon Bang, Jongkeun Song, Taeho Jeon, Byungsub Kim, Jae-Yoon Sim, Hong-June Park	A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation.	IEEE Trans. Biomed. Circuits Syst.	2017	DBLP DOI BibTeX RDF
17	V. Vinod, K. Eswar, P. Vishnuvardhan, G. Srikanth, S. R. Ramesh	VLSI implementation of LNS arithmetic unit by LUT partitioning.	ICACCI	2017	DBLP DOI BibTeX RDF
17	Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas	An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem.	ISVLSI	2017	DBLP DOI BibTeX RDF
17	Gai Liu, Zhiru Zhang	A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping.	FPGA	2017	DBLP BibTeX RDF
17	Matheus Nachtigall, Paulo Ferreira, Felipe S. Marques 0001	Simulated Annealing Applied to LUT-Based FPGA Technology Mapping.	MICAI (Special Session)	2017	DBLP DOI BibTeX RDF
17	Stephan Nolting, Lin Liu, Guillermo Payá Vayá	Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices.	FPL	2017	DBLP DOI BibTeX RDF
17	Ziyao Liu, Zhijie Wang, Jun Wang, Di Huang, Nangen Zhang	LUT-Based Efficient Impulse Shaping for Direct Synthesizing Digital Communication Signals at Arbitrary Symbol Rate.	ChinaCom (2)	2017	DBLP DOI BibTeX RDF
17	Oleksandr Drozd, Miroslav Drozd, Oleksandr Martynyuk, Mykola Kuznietsov	Improving of a Circuit Checkability and Trustworthiness of Data Processing Results in LUT-based FPGA Components of Safety-Related Systems.	ICTERI	2017	DBLP BibTeX RDF
17	Junwen Zhang, Jianjun Yu, Hung-Chang Chien	1.6Tb/s (4×400G) unrepeatered transmission over 205-km SSMF using 65-GBaud PDM-16QAM with joint LUT pre-distortion and post DBP nonlinearity compensation.	OFC	2017	DBLP BibTeX RDF
17	Junwen Zhang, Jianjun Yu, Hung-Chang Chien	EML-based IM/DD 400G (4×112.5-Gbit/s) PAM-4 over 80 km SSMF based on linear pre-equalization and nonlinear LUT pre-distortion for inter-DCI applications.	OFC	2017	DBLP BibTeX RDF
17	Junwen Zhang, Jianjun Yu, Hung-Chang Chien	Single-carrier 400G based on 84-GBaud PDM-8QAM transmission over 2, 125 km SSMF enhanced by pre-equalization, LUT and DBP.	OFC	2017	DBLP BibTeX RDF
17	Seungjin Lee, Taegun Yim, Choong Keun Lee, Kyungseon Cho, Hongil Yoon	Energy-efficient write circuit in STT-MRAM based look-up table (LUT) using comparison write scheme.	ISOCC	2017	DBLP DOI BibTeX RDF
17	Kyungseon Cho, Seungjin Lee, Choong Keun Lee, Taegun Yim, Hongil Yoon	Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA.	ISOCC	2017	DBLP DOI BibTeX RDF
17	Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid	Logic algebra for exploiting shared SRAM-table based FPGAs for large LUT inputs.	INTELLECT	2017	DBLP DOI BibTeX RDF
17	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto	An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k).	J. Multiple Valued Log. Soft Comput.	2016	DBLP BibTeX RDF
17	T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi	Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs.	Integr.	2016	DBLP DOI BibTeX RDF
17	Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel	LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
17	S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson	Hybrid LUT/Multiplexer FPGA Logic Architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
17	Burhan Khurshid, Roohie Naaz Mir	Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs.	Int. J. High Perform. Syst. Archit.	2016	DBLP DOI BibTeX RDF
17	Xiaowen Feng, Yide Wang, Bruno Feuvrie, Anne-Sophie Descamps, Yuehua Ding, Zhiwen Yu 0002	Analysis on LUT based digital predistortion using direct learning architecture for linearizing power amplifiers.	EURASIP J. Wirel. Commun. Netw.	2016	DBLP DOI BibTeX RDF
17	Daniel Mealha Cabrita, Carlos Raimundo Erig Lima	A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF
17	T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi	Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT.	J. Electron. Test.	2016	DBLP DOI BibTeX RDF
17	J. N. Swaminathan, P. Kumar	A Novel ML-2D-LUT Based Adaptive Predistorter of High Power Amplifier Using New Improved RLS Algorithm.	Wirel. Pers. Commun.	2016	DBLP DOI BibTeX RDF
17	Mohammad Naouss, François Marc	FPGA LUT delay degradation due to HCI: Experiment and simulation results.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
17	Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura	LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2016	DBLP DOI BibTeX RDF
17	Sebastian Fischer, Paul Myland, M. Szarafanowicz, Péter Bodrogi, Tran Quoc Khanh	Strengths and limitations of a uniform 3D-LUT approach for digital camera characterization.	CIC	2016	DBLP DOI BibTeX RDF
17	Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee	Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture.	NAS	2016	DBLP DOI BibTeX RDF
17	Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich	A LUT-Based Approximate Adder.	FCCM	2016	DBLP DOI BibTeX RDF
17	Christian Krieg, Clifford Wolf, Axel Jantsch	Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow.	ICCAD	2016	DBLP DOI BibTeX RDF
17	Yufeng Lu, Xiaohua Luo, Yimu Wang, Luc Claesen	Line buffer reduction for LUT-based real-time image inverse warping.	NEWCAS	2016	DBLP DOI BibTeX RDF
17	Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener	FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
17	Alexander V. Drozd, Miroslav Drozd, Mykola Kuznietsov	Use of Natural LUT Redundancy to Improve Trustworthiness of FPGA Design.	ICTERI	2016	DBLP BibTeX RDF
17	Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu	A LUT-based matrix multiplication using neural networks.	ISCAS	2016	DBLP DOI BibTeX RDF
17	Jiadong Wang, Aijiao Cui, Mengyang Li, Gang Qu 0001, Huawei Li 0001	An ultra-low overhead LUT-based PUF for FPGA.	AsianHOST	2016	DBLP DOI BibTeX RDF
17	Juexiao Su, Ju-Yueh Lee, Chang Wu, Lei He	In-place LUT polarity inVersion to mitigate soft errors for FPGAs.	DFT	2016	DBLP DOI BibTeX RDF
17	Theodore Winograd, Hassan Salmani, Hamid Mahmoodi, Houman Homayoun	Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates.	ISQED	2016	DBLP DOI BibTeX RDF
17	Kangwook Jo, Kyungseon Cho, Hongil Yoon	Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA).	ISOCC	2016	DBLP DOI BibTeX RDF
17	Deepak Kapoor, Rahul Yamasani, Saket Saurav, Abhishek Bajpai	LUT Optimization In Implementation Of Combinational Karatsuba Ofman On Virtex-6 FPGA.	SEM4HPC@HPDC	2016	DBLP DOI BibTeX RDF
17	Md. Mahbub Alam, Mark M. Tehranipoor, Domenic Forte	Recycled FPGA detection using exhaustive LUT path delay characterization.	ITC	2016	DBLP DOI BibTeX RDF
17	Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu	An Improved Design of a Reversible Fault Tolerant LUT-based FPGA.	VLSID	2016	DBLP DOI BibTeX RDF
17	Theodor Hillebrand, Nico Hellwege, Maike Taddiken, Konstantin Tscherkaschin, Steffen Paul, Dagmar Peters-Drolshagen	Stochastic LUT-based reliability-aware design method for operation point dependent CMOS circuits.	MIXDES	2016	DBLP DOI BibTeX RDF
17	Alessandro Bria, Claudio Marrocco, Jan-Jurre Mordang, Nico Karssemeijer, Mario Molinara, Francesco Tortorella	LUT-QNE: Look-Up-Table Quantum Noise Equalization in Digital Mammograms.	Digital Mammography / IWDM	2016	DBLP DOI BibTeX RDF
17	Matthias Locherer, Tobias Hank, Martin Danner, Wolfram Mauser	Retrieval of Seasonal Leaf Area Index from Simulated EnMAP Data through Optimized LUT-Based Inversion of the PROSAIL Model.	Remote. Sens.	2015	DBLP DOI BibTeX RDF
17	Igor Lemberski	Literal Decomposition for LUT-Oriented Asynchronous Dual-Rail Logic Synthesis.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
17	Asim Banskota, Shawn P. Serbin, Randolph H. Wynne, Valerie A. Thomas, Michael J. Falkowski, Nilam Kayastha, Jean-Philippe Gastellu-Etchegorry, Philip A. Townsend	An LUT-Based Inversion of DART Model to Estimate Forest LAI from Hyperspectral Data.	IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens.	2015	DBLP DOI BibTeX RDF
17	Ji Zhou 0001, Fengnan Dai, Xiaodong Zhang 0019, Shaojie Zhao, Mingsong Li	Developing a temporally land cover-based look-up table (TL-LUT) method for estimating land surface temperature based on AMSR-E data over the Chinese landmass.	Int. J. Appl. Earth Obs. Geoinformation	2015	DBLP DOI BibTeX RDF
17	Debapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger, Debdeep Mukhopadhyay	Reconfigurable LUT: Boon or Bane for Secure Applications.	IACR Cryptol. ePrint Arch.	2015	DBLP BibTeX RDF
17	Andreas Karlsson, Joar Sohl, Dake Liu	Software-based QPP interleaving for baseband DSPs with LUT-accelerated addressing.	DSP	2015	DBLP DOI BibTeX RDF
17	Mingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang	Mapping-Aware Constrained Scheduling for LUT-Based FPGAs.	FPGA	2015	DBLP DOI BibTeX RDF
17	Masahiro Fujita	On Implementation of LUT with Large Numbers of Inputs (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
17	T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi	Operational fault detection and monitoring of a memristor-based LUT.	DATE	2015	DBLP BibTeX RDF
17	Debapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger, Debdeep Mukhopadhyay, Xuan Thuy Ngo, Zakaria Najm	Reconfigurable LUT: A Double Edged Sword for Security-Critical Applications.	SPACE	2015	DBLP DOI BibTeX RDF
17	Ugur Cini, Olcay Kurt	A MAC unit with double carry-save scheme suitable for 6-input LUT based reconfigurable systems.	ICECS	2015	DBLP DOI BibTeX RDF
17	Ugur Cini, Mustafa Aktan	High performance FIR filter design for 6-input LUT based FPGAs.	ICECS	2015	DBLP DOI BibTeX RDF
17	Rakesh Mehta, Manuel Günther, Sébastien Marcel	Gender Classification by LUT Based Boosting of Overlapping Block Patterns.	SCIA	2015	DBLP DOI BibTeX RDF
17	Kostiantyn Zashcholkin, Olena Ivanova	The Control Technology of Integrity and Legitimacy of LUT-Oriented Information Object Usage by Self-Recovering Digital Watermark.	ICTERI	2015	DBLP BibTeX RDF
17	Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai	An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD.	ISMVL	2015	DBLP DOI BibTeX RDF
17	Shaoliang Zhang, Fatih Yaman, Yue-Kai Huang, Takanori Inoue, Kohei Nakamura, Eduardo Mateo, Yoshihisa Inada, Ting Wang, Takaaki Ogata	Trans-pacific transmission of quad-carrier 1Tb/s DP-8QAM assisted by LUT-based MAP algorithm.	OFC	2015	DBLP BibTeX RDF
17	Toshiki Higashi, Hiroyuki Ochi	Area-efficient LUT-like programmable logic using atom switch and its mapping algorithm.	ISCIT	2015	DBLP DOI BibTeX RDF
17	Shota Sekine, Shigeki Matsumoto, Katsutoshi Yoshida	Improvement of an LUT-based intelligent motion controller by underestimation of reachable sets.	SII	2015	DBLP DOI BibTeX RDF
17	Matthias Locherer, Tobias Hank, Martin Danner, Wolfram Mauser	Systematic analysis of the LUT-based inversion of PROSAIL using full range hyperspectral data for the retrieval of leaf area index in view of the future EnMAP mission.	IGARSS	2015	DBLP DOI BibTeX RDF
17	Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita	SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions.	IPSJ Trans. Syst. LSI Des. Methodol.	2014	DBLP DOI BibTeX RDF
17	Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu	Hybrid LUT and SOP Reconfigurable Architecture.	J. Inf. Sci. Eng.	2014	DBLP BibTeX RDF
17	Anh-Tuan Hoang, Takeshi Fujino	Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA.	ACM Trans. Reconfigurable Technol. Syst.	2014	DBLP DOI BibTeX RDF
17	Jochem Verrelst, Juan Pablo Rivera, Ganna Leonenko, Luis Alonso 0002, José F. Moreno	Optimizing LUT-Based RTM Inversion for Semiautomatic Mapping of Crop Biophysical Parameters from Sentinel-2 and -3 Data: Role of Cost Functions.	IEEE Trans. Geosci. Remote. Sens.	2014	DBLP DOI BibTeX RDF
17	Ken-Fu Liang, Jau-Horng Chen, Yi-Jan Emery Chen	A Quadratic-Interpolated LUT-Based Digital Predistortion Technique for Cellular Power Amplifiers.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
17	Meng Yang 0013, Jinmei Lai, A. E. A. Almaini	An Architecture Independent Packing Method for LUT-based Commercial FPGA.	J. Comput.	2014	DBLP BibTeX RDF
17	Kaifeng Zhang, Huanzhang Lu, Weidong Hu, Jian Wang	A LUT manipulation based intrinsic evolvable system.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
17	Monther Abusultan, Sunil P. Khatri	FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
17	Lei Xu 0012, Pham Dang Khoa, Seung-Hun Kim, Won Woo Ro, Weidong Shi	LUT based secure cloud computing - An implementation using FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
17	Roberto Piazza, Bhavani Shankar Mysore Rama Rao, Björn E. Ottersten	Multicarrier LUT-based data predistortion for non-linear satellite channels.	ICC	2014	DBLP DOI BibTeX RDF
17	Yuwen He, Yan Ye, Jie Dong	Robust 3D LUT estimation method for SHVC color gamut scalability.	VCIP	2014	DBLP DOI BibTeX RDF
17	Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang	Exploring architecture parameters for dual-output LUT based FPGAs.	FPL	2014	DBLP DOI BibTeX RDF
17	Kenneth M. Zick, Sen Li, Matthew French	High-precision self-characterization for the LUT burn-in information leakage threat.	FPL	2014	DBLP DOI BibTeX RDF
17	Xinqiang Luo, Yue Qi, Yadong Wan, Qin Wang 0004, Hong Zhang	A Fast AES Encryption Method Based on Single LUT for Industrial Wireless Network.	IIKI	2014	DBLP DOI BibTeX RDF
17	Haider A. F. Almurib, T. Nandha Kumar, Fabrizio Lombardi	A memristor-based LUT for FPGAs.	NEMS	2014	DBLP DOI BibTeX RDF
17	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K).	ISMVL	2014	DBLP DOI BibTeX RDF
17	Bastian Mohr, Ye Zhang 0003, Jan Henning Mueller, Stefan Heinen	Compensating imperfections in RF-DAC based transmitters using LUT-based predistortion.	SoCC	2014	DBLP DOI BibTeX RDF
17	Jing Yu 0014, Paul Beckett	A dual-rail LUT for reconfigurable logic using null convention logic.	ACM Great Lakes Symposium on VLSI	2014	DBLP DOI BibTeX RDF
17	Adarsh Reddy Ashammagari, Hamid Mahmoodi, Tinoosh Mohsenin, Houman Homayoun	Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors.	ACM Great Lakes Symposium on VLSI	2014	DBLP DOI BibTeX RDF
17	Monther Abusultan, Sunil P. Khatri	A comparison of FinFET based FPGA LUT designs.	ACM Great Lakes Symposium on VLSI	2014	DBLP DOI BibTeX RDF
17	Yingying Dong, Jinkai Zhang, Zhijie Wang, Karl Staenz, Craig A. Coburn, Wei Xu, Xiaodong Yang, Jihua Wang	Method to speed up LUT-based crop canopy parameter mapping.	IGARSS	2014	DBLP DOI BibTeX RDF
17	Srinivasa Reddy Kotha, Sumit Bajaj, Sahoo Subhendu Kumar	An LUT based RNS FIR filter implementation for reconfigurable applications.	VDAT	2014	DBLP DOI BibTeX RDF
17	T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi	A novel design of a memristor-based look-up table (LUT) for FPGA.	APCCAS	2014	DBLP DOI BibTeX RDF
17	Arpitam Chatterjee, Bipan Tudu, Kanai Ch. Paul	Binary genetic algorithm-based pattern LUT for grayscale digital half-toning.	Signal Image Video Process.	2013	DBLP DOI BibTeX RDF