Search results for "MRAM"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Soheil Salehi, Ramtin Zand, Alireza Zaeemzadeh, Nazanin Rahnavard, Ronald F. DeMara	AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Sparse Signals.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
16	Hao Li, Hongmei Yu, Dongsheng Liu, Peng Liu, Bo Liu 0063	A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module.	ASICON	2019	DBLP DOI BibTeX RDF
16	Kaiwen Lu, Fengze Yan, Xingjie Liu, Dongsheng Liu, Peng Liu, Bo Liu 0063	Novel smart card SoC memory architecture based on embedded STT-MRAM.	ASICON	2019	DBLP DOI BibTeX RDF
16	Sonal Shreya, Brajesh Kumar Kaushik	Low Restoration-Energy Differential Spin Hall Effect MRAM for High-Speed Nonvolatile SRAM Application.	ISQED	2019	DBLP DOI BibTeX RDF
16	Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta	Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.	DAC	2019	DBLP DOI BibTeX RDF
16	Shaahin Angizi, Jiao Sun, Wei Zhang 0076, Deliang Fan	AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM.	DAC	2019	DBLP DOI BibTeX RDF
16	Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou	NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge.	DAC	2019	DBLP DOI BibTeX RDF
16	Hung-Ju Lai, Yao-Tung Tsou	STT-MRAM Co-design Deep Learning Model for IoT Applications.	GCCE	2019	DBLP DOI BibTeX RDF
16	Jin Woong Kwak, Andrew Marshall, Harvey Stiegler	28nm STT-MRAM Array and Sense Amplifier.	MOCAST	2019	DBLP DOI BibTeX RDF
16	Kazi Asifuzzaman	Evaluation of STT-MRAM main memory for HPC and real-time systems.		2019	RDF
16	Zhezhi He, Yang Zhang 0035, Shaahin Angizi, Boqing Gong, Deliang Fan	Exploring a SOT-MRAM Based In-Memory Computing for Data Processing.	IEEE Trans. Multi Scale Comput. Syst.	2018	DBLP DOI BibTeX RDF
16	Engin Ipek, Florian Longnos, Shihai Xiao, Wei Yang	Bit-Level Load Balancing: A New Technique for Improving the Write Throughput of Deeply Scaled STT-MRAM.	IEEE Comput. Archit. Lett.	2018	DBLP DOI BibTeX RDF
16	Engin Ipek, Florian Longnos, Shihai Xiao, Wei Yang	Vertical Writes: Closing the Throughput Gap between Deeply Scaled STT-MRAM and DRAM.	IEEE Comput. Archit. Lett.	2018	DBLP DOI BibTeX RDF
16	Rashidah Funke Olanrewaju, Burhan Ul Islam Khan, Abdul Raouf Khan, Mashkuri Yaacob, Md. Moktarul Alam	Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches.	Int. J. Grid Util. Comput.	2018	DBLP DOI BibTeX RDF
16	Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung H. Kang, Yuan Xie 0001	An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
16	Ing-Chao Lin, Yun Kae Law, Yuan Xie 0001	Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
16	Yeongkyo Seo, Kaushik Roy 0001	High-Density SOT-MRAM Based on Shared Bitline Structure.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
16	Alessandro Grossi, Cristian Zambelli, Piero Olivo, Paolo Pellati, Michele Ramponi, Christian Wenger, Jérémy Alvarez-Herault, Ken Mackay	An Automated Test Equipment for Characterization of Emerging MRAM and RRAM Arrays.	IEEE Trans. Emerg. Top. Comput.	2018	DBLP DOI BibTeX RDF
16	Xiaochen Guo, Mahdi Nazm Bojnordi, Qing Guo 0004, Engin Ipek	Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
16	Insik Yoon, Arijit Raychowdhury	Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
16	Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori	VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
16	Farhana Parveen, Shaahin Angizi, Deliang Fan	IMFlexCom: Energy Efficient In-Memory Flexible Computing Using Dual-Mode SOT-MRAM.	ACM J. Emerg. Technol. Comput. Syst.	2018	DBLP DOI BibTeX RDF
16	Liwen Liu, Yiqi Zhuang, Li Zhang, Hualian Tang, Siwan Dong	Proactive correction coset decoding scheme based on SEC-DED code for multibit asymmetric errors in STT-MRAM.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
16	Ali Zarei, Farshad Safaei	Power and area-efficient design of VCMA-MRAM based full-adder using approximate computing for IoT applications.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
16	Liuyang Zhang, Erya Deng, Hao Cai, You Wang 0002, Lionel Torres, Aida Todri-Sanial, Youguang Zhang	A high-reliability and low-power computing-in-memory implementation within STT-MRAM.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
16	Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar	SOT-MRAM 300mm integration for low power and ultrafast embedded memories.	CoRR	2018	DBLP BibTeX RDF
16	Xin Ma, Liang Chang 0002, Shuangchen Li, Lei Deng 0003, Yufei Ding, Yuan Xie 0001	In-memory multiplication engine with SOT-MRAM based stochastic computing.	CoRR	2018	DBLP BibTeX RDF
16	Rafatul Faria, Kerem Yunus Camsari, Supriyo Datta	Implementing Bayesian Networks with Embedded Stochastic MRAM.	CoRR	2018	DBLP BibTeX RDF
16	Mesut Atasoyu, Mustafa Altun, Serdar Özoguz	High Speed and Low Power Sensing Schemes for STT-MRAM with IPMTJs.	CoRR	2018	DBLP BibTeX RDF
16	Ramtin Zand, Kerem Yunus Camsari, Supriyo Datta, Ronald F. DeMara	Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons.	CoRR	2018	DBLP BibTeX RDF
16	Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Behzad Zeinali, Farshad Moradi	A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
16	Kien Trinh Quang, Sergio Ruocco, Massimo Alioto	Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
16	Simon Van Beek, Philippe Roussel, Barry J. O'Sullivan, Robin Degraeve, Stefan Cosemans, Dimitri Linten, Gouri Sankar Kar	Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit.	ESSDERC	2018	DBLP DOI BibTeX RDF
16	Mohammad Sabbah, Mostafa Rizk, Ali Chamas Al Ghouwayel, Samir-Mohamad Omar, Zouhair El-Bazzal	Enhanced Throughput and Energy-Efficient MRAM-Based NB-LDPC Decoder.	ICCA	2018	DBLP DOI BibTeX RDF
16	Y. A. Belay, Alessandro Cabrini, Guido Torelli	A Variability-Aware Analysis and Design Guideline for Write and Read Operations in Crosspoint STT-MRAM Arrays.	PRIME	2018	DBLP DOI BibTeX RDF
16	Liuyang Zhang, Wang Kang 0001, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao	A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.	ISVLSI	2018	DBLP DOI BibTeX RDF
16	Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao	Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization.	ISVLSI	2018	DBLP DOI BibTeX RDF
16	Zhezhi He, Shaahin Angizi, Deliang Fan	Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM.	ISVLSI	2018	DBLP DOI BibTeX RDF
16	Hao Cai, You Wang 0002, Wang Kang 0001, Lirida A. B. Naviner, Xinning Liu, Jun Yang 0006, Weisheng Zhao	MRAM-on-FDSOI Integration: A Bit-Cell Perspective.	ISVLSI	2018	DBLP DOI BibTeX RDF
16	Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy 0001	Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
16	Erya Deng, Zhaohao Wang, Wang Kang 0001, Shaoqian Wei, Weisheng Zhao	Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
16	Andres F. Gomez, Freddy Forero, Kaushik Roy 0001, Víctor H. Champac	Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
16	Barry J. O'Sullivan, Simon Van Beek, Philippe J. Roussel, Sidharth Rao, Wonsub Kim, S. Couet, Johan Swerts, Farrukh Yasin, Dimitri Crotti, Dimitri Linten, Gouri Sankar Kar	Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown.	IRPS	2018	DBLP DOI BibTeX RDF
16	Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah	ORIENT: Organized interleaved ECCs for new STT-MRAM caches.	DATE	2018	DBLP DOI BibTeX RDF
16	Manu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenllado, José Ignacio Gómez, Gouri Sankar Kar, Arnaud Furnémont, Francky Catthoor, Sophiane Senni, David Novo, Abdoulaye Gamatié, Lionel Torres	Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.	DATE	2018	DBLP DOI BibTeX RDF
16	Nour Sayed, Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori	A cross-layer adaptive approach for performance and power optimization in STT-MRAM.	DATE	2018	DBLP DOI BibTeX RDF
16	Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori	Parametric failure modeling and yield analysis for STT-MRAM.	DATE	2018	DBLP DOI BibTeX RDF
16	Rana Alhalabi, Etienne Nowak, Ioan Lucian Prejbeanu, Gregory di Pendina	High density SOT-MRAM memory array based on a single transistor.	NVMTS	2018	DBLP DOI BibTeX RDF
16	Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh	Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system.	NVMTS	2018	DBLP DOI BibTeX RDF
16	Pierre-Yves Péneau, David Novo, Florent Bruguier, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié	Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy.	ARCS	2018	DBLP DOI BibTeX RDF
16	Nour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori	Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM.	ASP-DAC	2018	DBLP DOI BibTeX RDF
16	Farhana Parveen, Zhezhi He, Shaahin Angizi, Deliang Fan	HielM: Highly flexible in-memory computing using STT MRAM.	ASP-DAC	2018	DBLP DOI BibTeX RDF
16	Jeongbin Kim 0001, Ki Tae Kim, Eui-Young Chung	CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA.	ICSCA	2018	DBLP DOI BibTeX RDF
16	Seungjin Lee, Taegun Yim, Hongil Yoon	Low-Energy Consumption Write Circuit using Comparing Operation in STT-MRAM.	TENCON	2018	DBLP DOI BibTeX RDF
16	Hao Yan, Hebin R. Cherian, Ethan C. Ahn, Lide Duan	CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration.	ICS	2018	DBLP DOI BibTeX RDF
16	Sanjay Prajapati, Zeljko Zilic, Brajesh Kumar Kaushik	Area and Energy Efficient Magnetic Full Adder based on Differential Spin Hall MRAM.	NEWCAS	2018	DBLP DOI BibTeX RDF
16	Chaoxin Ding, Wang Kang 0001, He Zhang 0011, Youguang Zhang, Weisheng Zhao	A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation.	NANOARCH	2018	DBLP DOI BibTeX RDF
16	Qing Dong 0001, Zhehong Wang, Jongyup Lim, Yiqun Zhang 0002, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester	A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination.	ISSCC	2018	DBLP DOI BibTeX RDF
16	Tzu-Hsien Yang, Kai-Xiang Li, Yen-Ning Chiang, Wei-Yu Lin, Huan-Ting Lin, Meng-Fan Chang	A 28nm 32Kb embedded 2T2MTJ STT-MRAM macro with 1.3ns read-access time for fast and reliable read applications.	ISSCC	2018	DBLP DOI BibTeX RDF
16	Kevin Garello, Kevin Garello Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, Kris Croes, N. Jossart, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Fumemont, Pietro Gambardella, Gouri Sankar Kar	SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
16	Kaiyuan Yang 0001, Qing Dong 0001, Zhehong Wang, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester	A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
16	Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang	Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
16	Chen Liu, Yuanqing Cheng, Ying Wang 0001, Youguang Zhang, Weisheng Zhao	NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs.	ISCAS	2018	DBLP DOI BibTeX RDF
16	Gyuseong Kang, Yunho Jang, Jongsun Park 0001	Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM.	ISCAS	2018	DBLP DOI BibTeX RDF
16	Artur Antonyan, Suk-Soo Pyo, Hyuntaek Jung, Taejoong Song	Embedded MRAM Macro for eFlash Replacement.	ISCAS	2018	DBLP DOI BibTeX RDF
16	Mounia Kharbouche-Harrari, Jérémy Postel-Pellerin, Gregory di Pendina, Romain Wacquez, Driss Aboulkassimi, Marc Bocquet, R. Sousa, R. Delattre, Jean-Michel Portal	Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues.	IOLTS	2018	DBLP DOI BibTeX RDF
16	Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui	Electrical Modeling of STT-MRAM Defects.	ITC	2018	DBLP DOI BibTeX RDF
16	Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutyunyan, Yervant Zorian	Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.	ITC	2018	DBLP DOI BibTeX RDF
16	Mohammad Gh. Alfailakawi, Imtiaz Ahmad, Sarah Elghandour	Energy-Efficient Dynamic Data Encoding for Multi-level STT-MRAM.	VLSID	2018	DBLP DOI BibTeX RDF
16	Ashwani Kumar, Shubham Sahay, Manan Suri	Switching-Time Dependent PUF Using STT-MRAM.	VLSID	2018	DBLP DOI BibTeX RDF
16	Mounia Kharbouche-Harrari, Rana Alhalabi, Jérémy Postel-Pellerin, Romain Wacquez, Driss Aboulkassimi, Etienne Nowak, Ioan Lucian Prejbeanu, Guillaume Prenat, Gregory di Pendina	MRAM: from STT to SOT, for security and memory.	DCIS	2018	DBLP DOI BibTeX RDF
16	Keerthi Sagar Kokkiligadda, Yogendra Gupta, Lava Bhargava	Efficient and Failure Aware ECC for STT-MRAM Cache Memory.	VDAT	2018	DBLP DOI BibTeX RDF
16	Xue Liu, Kui Cai 0001, Zhen Mei	FPGA Implementation of A Hybrid Decoder for STT-MRAM.	APCCAS	2018	DBLP DOI BibTeX RDF
16	Menglin Han, Hao Cai, Jun Yang 0006, Lirida A. B. Naviner, You Wang 0002, Weisheng Zhao	Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.	APCCAS	2018	DBLP DOI BibTeX RDF
16	Jiawang Hu, Dongsheng Liu, Cong Zhang, Changxing Li, Hualong Zhao	Design and Hardware Implementation of a STT-MRAM Based SoC Architecture for Smart Card Chip.	APCCAS	2018	DBLP DOI BibTeX RDF
16	Raf Appeltans, Praveen Raghavan, Gouri Sankar Kar, Arnaud Furnémont, Liesbet Van der Perre, Wim Dehaene	A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
16	Ramtin Zand, Arman Roohi, Ronald F. DeMara	Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
16	Imtiaz Ahmad, Mahmoud Imdoukh, Mohammad AlFailakawi	Extending multi-level STT-MRAM cell lifetime by minimising two-step and hard state transitions in hot bits.	IET Comput. Digit. Tech.	2017	DBLP DOI BibTeX RDF
16	Wang Kang 0001, Liang Chang 0002, Zhaohao Wang, Weifeng Lv, Guangyu Sun 0003, Weisheng Zhao	Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
16	Hao Yan, Lei Jiang 0001, Lide Duan, Wei-Ming Lin, Eugene John	FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance.	ACM Trans. Embed. Comput. Syst.	2017	DBLP DOI BibTeX RDF
16	Soheil Salehi, Deliang Fan, Ronald F. DeMara	Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency.	ACM J. Emerg. Technol. Comput. Syst.	2017	DBLP DOI BibTeX RDF
16	Abhishek Chakraborty 0001, Ankit Mondal, Ankur Srivastava 0001	Correlation Power Analysis Attack against STT-MRAM Based Cyptosystems.	IACR Cryptol. ePrint Arch.	2017	DBLP BibTeX RDF
16	Wang Kang 0001, Tingting Pang, Weifeng Lv, Weisheng Zhao	Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
16	Behzad Zeinali, Mahsa Esmaeili, Jens Kargaard Madsen, Farshad Moradi	Multilevel SOT-MRAM cell with a novel sensing scheme for high-density memory applications.	ESSDERC	2017	DBLP DOI BibTeX RDF
16	Lohith Kumar Vemula, Nahid M. Hossain, Masud H. Chowdhury	Error free sense amplifier circuit design for STT-MRAM nonvolatile memory.	MWSCAS	2017	DBLP DOI BibTeX RDF
16	Lohith Kumar Vemula, Nahid M. Hossain, Masud H. Chowdhury	Emerging STT-MRAM circuit and architecture co-design in 45nm technology.	MWSCAS	2017	DBLP DOI BibTeX RDF
16	David H. K. Hoe	Bayesian inference using spintronic technology: A proposal for an MRAM-based stochastic logic gate.	MWSCAS	2017	DBLP DOI BibTeX RDF
16	Mohammad Sabbah, Ali Chamas Al Ghouwayel, Mostafa Rizk, Zouhair El-Bazzal	MRAM-based memorization system for NB-LDPC decoder.	ICM	2017	DBLP DOI BibTeX RDF
16	Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Peneau, Lionel Torres, Abdoulaye Gamatié, Pascal Benoit, Gilles Sassatelli	Embedded systems to high performance computing using STT-MRAM.	DATE	2017	DBLP DOI BibTeX RDF
16	Nour Sayed, Mojtaba Ebrahimi, Rajendra Bishnoi, Mehdi Baradaran Tahoori	Opportunistic write for fast and reliable STT-MRAM.	DATE	2017	DBLP DOI BibTeX RDF
16	Ashish Ranjan 0001, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy 0001, Anand Raghunathan	STAxCache: An approximate, energy efficient STT-MRAM cache.	DATE	2017	DBLP DOI BibTeX RDF
16	Wang Kang 0001, Liang Chang 0002, Youguang Zhang, Weisheng Zhao	Voltage-controlled MRAM for working memory: Perspectives and challenges.	DATE	2017	DBLP DOI BibTeX RDF
16	Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori	VAET-STT: A variation aware estimator tool for STT-MRAM based memories.	DATE	2017	DBLP DOI BibTeX RDF
16	Nikita Gupta, Pragati Thakur, Shashank Kumar Dubey, Aminul Islam 0002	Design of nonvolatile MRAM bitcell.	ISED	2017	DBLP DOI BibTeX RDF
16	Wenlong Cai, Kaihua Cao, Mengxing Wang, Shouzhong Peng, Jiaqi Zhou 0002, Anni Cao, Boyu Zhang, Lezhi Wang, Yu Zhang, Jiaqi Wei, Xiaobin He, Hushan Cui, Chao Zhao, Weisheng Zhao	Interfacial property tuning of heavy metal/CoFeB for large density STT-MRAM.	NVMTS	2017	DBLP DOI BibTeX RDF
16	Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras	Mitigating read & write errors in STT-MRAM memories under DVS.	ETS	2017	DBLP DOI BibTeX RDF
16	Nour Sayed, Fabian Oboril, Azadeh Shirvanian, Rajendra Bishnoi, Mehdi Baradaran Tahoori	Exploiting STT-MRAM for approximate computing.	ETS	2017	DBLP DOI BibTeX RDF
16	Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto	Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories.	IVSW	2017	DBLP DOI BibTeX RDF
16	Kazi Asifuzzaman, Rommel Sánchez Verdejo, Petar Radojkovic	Enabling a reliable STT-MRAM main memory simulation.	MEMSYS	2017	DBLP DOI BibTeX RDF
16	Hengyu Zhao, Linuo Xue, Ping Chi, Jishen Zhao	Approximate image storage with multi-level cell STT-MRAM main memory.	ICCAD	2017	DBLP DOI BibTeX RDF