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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 62 occurrences of 45 keywords
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Results
Found 708 publication records. Showing 707 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Soheil Salehi, Ramtin Zand, Alireza Zaeemzadeh, Nazanin Rahnavard, Ronald F. DeMara |
AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Sparse Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019, pp. 359-362, 2019, ACM, 978-1-4503-6252-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Hao Li, Hongmei Yu, Dongsheng Liu, Peng Liu, Bo Liu 0063 |
A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0735-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Kaiwen Lu, Fengze Yan, Xingjie Liu, Dongsheng Liu, Peng Liu, Bo Liu 0063 |
Novel smart card SoC memory architecture based on embedded STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0735-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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16 | Sonal Shreya, Brajesh Kumar Kaushik |
Low Restoration-Energy Differential Spin Hall Effect MRAM for High-Speed Nonvolatile SRAM Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, CA, USA, March 6-7, 2019, pp. 58-63, 2019, IEEE, 978-1-7281-0392-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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16 | Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta |
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, pp. 13, 2019, ACM, 978-1-4503-6725-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Shaahin Angizi, Jiao Sun, Wei Zhang 0076, Deliang Fan |
AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, pp. 144, 2019, ACM, 978-1-4503-6725-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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16 | Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou |
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, pp. 30, 2019, ACM, 978-1-4503-6725-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Hung-Ju Lai, Yao-Tung Tsou |
STT-MRAM Co-design Deep Learning Model for IoT Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCCE ![In: IEEE 8th Global Conference on Consumer Electronics, GCCE 2019, Osaka, Japan, October 15-18, 2019, pp. 421-422, 2019, IEEE, 978-1-7281-3575-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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16 | Jin Woong Kwak, Andrew Marshall, Harvey Stiegler |
28nm STT-MRAM Array and Sense Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, Thessaloniki, Greece, May 13-15, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1184-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Kazi Asifuzzaman |
Evaluation of STT-MRAM main memory for HPC and real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2019 |
RDF |
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16 | Zhezhi He, Yang Zhang 0035, Shaahin Angizi, Boqing Gong, Deliang Fan |
Exploring a SOT-MRAM Based In-Memory Computing for Data Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multi Scale Comput. Syst. ![In: IEEE Trans. Multi Scale Comput. Syst. 4(4), pp. 676-685, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Engin Ipek, Florian Longnos, Shihai Xiao, Wei Yang |
Bit-Level Load Balancing: A New Technique for Improving the Write Throughput of Deeply Scaled STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 17(2), pp. 139-142, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Engin Ipek, Florian Longnos, Shihai Xiao, Wei Yang |
Vertical Writes: Closing the Throughput Gap between Deeply Scaled STT-MRAM and DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 17(2), pp. 151-154, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Rashidah Funke Olanrewaju, Burhan Ul Islam Khan, Abdul Raouf Khan, Mashkuri Yaacob, Md. Moktarul Alam |
Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Grid Util. Comput. ![In: Int. J. Grid Util. Comput. 9(4), pp. 307-321, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung H. Kang, Yuan Xie 0001 |
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(3), pp. 484-495, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Ing-Chao Lin, Yun Kae Law, Yuan Xie 0001 |
Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(1), pp. 50-62, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Yeongkyo Seo, Kaushik Roy 0001 |
High-Density SOT-MRAM Based on Shared Bitline Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(8), pp. 1600-1603, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Alessandro Grossi, Cristian Zambelli, Piero Olivo, Paolo Pellati, Michele Ramponi, Christian Wenger, Jérémy Alvarez-Herault, Ken Mackay |
An Automated Test Equipment for Characterization of Emerging MRAM and RRAM Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 6(2), pp. 269-277, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Xiaochen Guo, Mahdi Nazm Bojnordi, Qing Guo 0004, Engin Ipek |
Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 67(6), pp. 847-860, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Insik Yoon, Arijit Raychowdhury |
Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2), pp. 337-349, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori |
VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7), pp. 1396-1407, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Farhana Parveen, Shaahin Angizi, Deliang Fan |
IMFlexCom: Energy Efficient In-Memory Flexible Computing Using Dual-Mode SOT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 14(3), pp. 35:1-35:18, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Liwen Liu, Yiqi Zhuang, Li Zhang, Hualian Tang, Siwan Dong |
Proactive correction coset decoding scheme based on SEC-DED code for multibit asymmetric errors in STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 82, pp. 92-100, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Ali Zarei, Farshad Safaei |
Power and area-efficient design of VCMA-MRAM based full-adder using approximate computing for IoT applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 82, pp. 62-70, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Liuyang Zhang, Erya Deng, Hao Cai, You Wang 0002, Lionel Torres, Aida Todri-Sanial, Youguang Zhang |
A high-reliability and low-power computing-in-memory implementation within STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 81, pp. 69-75, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar |
SOT-MRAM 300mm integration for low power and ultrafast embedded memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1810.10356, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
16 | Xin Ma, Liang Chang 0002, Shuangchen Li, Lei Deng 0003, Yufei Ding, Yuan Xie 0001 |
In-memory multiplication engine with SOT-MRAM based stochastic computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1809.08358, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
16 | Rafatul Faria, Kerem Yunus Camsari, Supriyo Datta |
Implementing Bayesian Networks with Embedded Stochastic MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1801.00497, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
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16 | Mesut Atasoyu, Mustafa Altun, Serdar Özoguz |
High Speed and Low Power Sensing Schemes for STT-MRAM with IPMTJs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1803.07037, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
16 | Ramtin Zand, Kerem Yunus Camsari, Supriyo Datta, Ronald F. DeMara |
Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1811.11390, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
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16 | Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Behzad Zeinali, Farshad Moradi |
A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(11), pp. 1708-1712, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Kien Trinh Quang, Sergio Ruocco, Massimo Alioto |
Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10), pp. 3338-3348, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Simon Van Beek, Philippe Roussel, Barry J. O'Sullivan, Robin Degraeve, Stefan Cosemans, Dimitri Linten, Gouri Sankar Kar |
Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, September 3-6, 2018, pp. 146-149, 2018, IEEE, 978-1-5386-5401-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Mohammad Sabbah, Mostafa Rizk, Ali Chamas Al Ghouwayel, Samir-Mohamad Omar, Zouhair El-Bazzal |
Enhanced Throughput and Energy-Efficient MRAM-Based NB-LDPC Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCA ![In: 2018 International Conference on Computer and Applications (ICCA), Beirut, Lebanon, August 25-26, 2018, pp. 172-176, 2018, IEEE, 978-1-5386-4371-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Y. A. Belay, Alessandro Cabrini, Guido Torelli |
A Variability-Aware Analysis and Design Guideline for Write and Read Operations in Crosspoint STT-MRAM Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018, Prague, Czech Republic, July 2-5, 2018, pp. 73-76, 2018, IEEE, 978-1-5386-5387-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Liuyang Zhang, Wang Kang 0001, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao |
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 275-280, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao |
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 333-338, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Zhezhi He, Shaahin Angizi, Deliang Fan |
Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 533-538, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Hao Cai, You Wang 0002, Wang Kang 0001, Lirida A. B. Naviner, Xinning Liu, Jun Yang 0006, Weisheng Zhao |
MRAM-on-FDSOI Integration: A Bit-Cell Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 263-268, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy 0001 |
Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers, pp. 207-231, 2018, Springer, 978-3-030-23424-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Erya Deng, Zhaohao Wang, Wang Kang 0001, Shaoqian Wei, Weisheng Zhao |
Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, pp. 184-187, 2018, IEEE, 978-1-5386-4756-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Andres F. Gomez, Freddy Forero, Kaushik Roy 0001, Víctor H. Champac |
Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, pp. 65-70, 2018, IEEE, 978-1-5386-4756-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Barry J. O'Sullivan, Simon Van Beek, Philippe J. Roussel, Sidharth Rao, Wonsub Kim, S. Couet, Johan Swerts, Farrukh Yasin, Dimitri Crotti, Dimitri Linten, Gouri Sankar Kar |
Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 5-1, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah |
ORIENT: Organized interleaved ECCs for new STT-MRAM caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 1187-1190, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Manu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenllado, José Ignacio Gómez, Gouri Sankar Kar, Arnaud Furnémont, Francky Catthoor, Sophiane Senni, David Novo, Abdoulaye Gamatié, Lionel Torres |
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 103-108, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Nour Sayed, Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori |
A cross-layer adaptive approach for performance and power optimization in STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 791-796, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori |
Parametric failure modeling and yield analysis for STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 265-268, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Rana Alhalabi, Etienne Nowak, Ioan Lucian Prejbeanu, Gregory di Pendina |
High density SOT-MRAM memory array based on a single transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NVMTS ![In: Non-Volatile Memory Technology Symposium, NVMTS 2018, Sendai, Japan, October 22-24, 2018, pp. 1-3, 2018, IEEE, 978-1-5386-7783-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh |
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NVMTS ![In: Non-Volatile Memory Technology Symposium, NVMTS 2018, Sendai, Japan, October 22-24, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-7783-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Pierre-Yves Péneau, David Novo, Florent Bruguier, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié |
Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 9-12, 2018, Proceedings, pp. 168-180, 2018, Springer, 978-3-319-77609-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Nour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori |
Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, pp. 203-208, 2018, IEEE, 978-1-5090-0602-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Farhana Parveen, Zhezhi He, Shaahin Angizi, Deliang Fan |
HielM: Highly flexible in-memory computing using STT MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, pp. 361-366, 2018, IEEE, 978-1-5090-0602-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Jeongbin Kim 0001, Ki Tae Kim, Eui-Young Chung |
CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSCA ![In: Proceedings of the 7th International Conference on Software and Computer Applications, ICSCA 2018, Kuantan, Malaysia, February 08-10, 2018, pp. 312-316, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Seungjin Lee, Taegun Yim, Hongil Yoon |
Low-Energy Consumption Write Circuit using Comparing Operation in STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TENCON ![In: TENCON 2018 - 2018 IEEE Region 10 Conference, Jeju, South Korea, October 28-31, 2018, pp. 1367-1370, 2018, IEEE, 978-1-5386-5457-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Hao Yan, Hebin R. Cherian, Ethan C. Ahn, Lide Duan |
CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 32nd International Conference on Supercomputing, ICS 2018, Beijing, China, June 12-15, 2018, pp. 149-159, 2018, ACM, 978-1-4503-5783-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Sanjay Prajapati, Zeljko Zilic, Brajesh Kumar Kaushik |
Area and Energy Efficient Magnetic Full Adder based on Differential Spin Hall MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018, Montréal, QC, Canada, June 24-27, 2018, pp. 317-321, 2018, IEEE, 978-1-5386-4859-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Chaoxin Ding, Wang Kang 0001, He Zhang 0011, Youguang Zhang, Weisheng Zhao |
A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018, Athens, Greece, July 17-19, 2018, pp. 72-78, 2018, ACM, 978-1-4503-5815-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Qing Dong 0001, Zhehong Wang, Jongyup Lim, Yiqun Zhang 0002, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester |
A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 480-482, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Tzu-Hsien Yang, Kai-Xiang Li, Yen-Ning Chiang, Wei-Yu Lin, Huan-Ting Lin, Meng-Fan Chang |
A 28nm 32Kb embedded 2T2MTJ STT-MRAM macro with 1.3ns read-access time for fast and reliable read applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 482-484, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Kevin Garello, Kevin Garello Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, Kris Croes, N. Jossart, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Fumemont, Pietro Gambardella, Gouri Sankar Kar |
SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018, pp. 81-82, 2018, IEEE, 978-1-5386-4214-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Kaiyuan Yang 0001, Qing Dong 0001, Zhehong Wang, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester |
A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018, pp. 171-172, 2018, IEEE, 978-1-5386-4214-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang |
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018, pp. 79-80, 2018, IEEE, 978-1-5386-4214-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Chen Liu, Yuanqing Cheng, Ying Wang 0001, Youguang Zhang, Weisheng Zhao |
NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Gyuseong Kang, Yunho Jang, Jongsun Park 0001 |
Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-4, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Artur Antonyan, Suk-Soo Pyo, Hyuntaek Jung, Taejoong Song |
Embedded MRAM Macro for eFlash Replacement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-4, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Mounia Kharbouche-Harrari, Jérémy Postel-Pellerin, Gregory di Pendina, Romain Wacquez, Driss Aboulkassimi, Marc Bocquet, R. Sousa, R. Delattre, Jean-Michel Portal |
Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 24th IEEE International Symposium on On-Line Testing And Robust System Design, IOLTS 2018, Platja D'Aro, Spain, July 2-4, 2018, pp. 243-244, 2018, IEEE, 978-1-5386-5992-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui |
Electrical Modeling of STT-MRAM Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2018, Phoenix, AZ, USA, October 29 - Nov. 1, 2018, pp. 1-10, 2018, IEEE, 978-1-5386-8382-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutyunyan, Yervant Zorian |
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2018, Phoenix, AZ, USA, October 29 - Nov. 1, 2018, pp. 1-10, 2018, IEEE, 978-1-5386-8382-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Gh. Alfailakawi, Imtiaz Ahmad, Sarah Elghandour |
Energy-Efficient Dynamic Data Encoding for Multi-level STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018, pp. 428-433, 2018, IEEE Computer Society, 978-1-5386-3692-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Ashwani Kumar, Shubham Sahay, Manan Suri |
Switching-Time Dependent PUF Using STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018, pp. 434-438, 2018, IEEE Computer Society, 978-1-5386-3692-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Mounia Kharbouche-Harrari, Rana Alhalabi, Jérémy Postel-Pellerin, Romain Wacquez, Driss Aboulkassimi, Etienne Nowak, Ioan Lucian Prejbeanu, Guillaume Prenat, Gregory di Pendina |
MRAM: from STT to SOT, for security and memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCIS ![In: Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, pp. 1-6, 2018, IEEE, 978-1-7281-0171-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Keerthi Sagar Kokkiligadda, Yogendra Gupta, Lava Bhargava |
Efficient and Failure Aware ECC for STT-MRAM Cache Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers, pp. 509-520, 2018, Springer, 978-981-13-5949-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Xue Liu, Kui Cai 0001, Zhen Mei |
FPGA Implementation of A Hybrid Decoder for STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018, pp. 325-328, 2018, IEEE, 978-1-5386-8240-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Menglin Han, Hao Cai, Jun Yang 0006, Lirida A. B. Naviner, You Wang 0002, Weisheng Zhao |
Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018, pp. 386-389, 2018, IEEE, 978-1-5386-8240-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Jiawang Hu, Dongsheng Liu, Cong Zhang, Changxing Li, Hualong Zhao |
Design and Hardware Implementation of a STT-MRAM Based SoC Architecture for Smart Card Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018, pp. 309-312, 2018, IEEE, 978-1-5386-8240-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Raf Appeltans, Praveen Raghavan, Gouri Sankar Kar, Arnaud Furnémont, Liesbet Van der Perre, Wim Dehaene |
A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(4), pp. 1204-1214, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Ramtin Zand, Arman Roohi, Ronald F. DeMara |
Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(9), pp. 2394-2401, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Imtiaz Ahmad, Mahmoud Imdoukh, Mohammad AlFailakawi |
Extending multi-level STT-MRAM cell lifetime by minimising two-step and hard state transitions in hot bits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 11(6), pp. 214-220, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Wang Kang 0001, Liang Chang 0002, Zhaohao Wang, Weifeng Lv, Guangyu Sun 0003, Weisheng Zhao |
Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(3), pp. 531-544, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Hao Yan, Lei Jiang 0001, Lide Duan, Wei-Ming Lin, Eugene John |
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 16(5s), pp. 132:1-132:20, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Soheil Salehi, Deliang Fan, Ronald F. DeMara |
Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 13(3), pp. 48:1-48:16, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Abhishek Chakraborty 0001, Ankit Mondal, Ankur Srivastava 0001 |
Correlation Power Analysis Attack against STT-MRAM Based Cyptosystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2017, pp. 413, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
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16 | Wang Kang 0001, Tingting Pang, Weifeng Lv, Weisheng Zhao |
Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(1), pp. 122-132, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Behzad Zeinali, Mahsa Esmaeili, Jens Kargaard Madsen, Farshad Moradi |
Multilevel SOT-MRAM cell with a novel sensing scheme for high-density memory applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, September 11-14, 2017, pp. 172-175, 2017, IEEE, 978-1-5090-5978-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Lohith Kumar Vemula, Nahid M. Hossain, Masud H. Chowdhury |
Error free sense amplifier circuit design for STT-MRAM nonvolatile memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 703-706, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Lohith Kumar Vemula, Nahid M. Hossain, Masud H. Chowdhury |
Emerging STT-MRAM circuit and architecture co-design in 45nm technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 719-722, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | David H. K. Hoe |
Bayesian inference using spintronic technology: A proposal for an MRAM-based stochastic logic gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 1521-1524, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Mohammad Sabbah, Ali Chamas Al Ghouwayel, Mostafa Rizk, Zouhair El-Bazzal |
MRAM-based memorization system for NB-LDPC decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 29th International Conference on Microelectronics, ICM 2017, Beirut, Lebanon, December 10-13, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-4049-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Peneau, Lionel Torres, Abdoulaye Gamatié, Pascal Benoit, Gilles Sassatelli |
Embedded systems to high performance computing using STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 536-541, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Nour Sayed, Mojtaba Ebrahimi, Rajendra Bishnoi, Mehdi Baradaran Tahoori |
Opportunistic write for fast and reliable STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 554-559, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Ashish Ranjan 0001, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy 0001, Anand Raghunathan |
STAxCache: An approximate, energy efficient STT-MRAM cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 356-361, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Wang Kang 0001, Liang Chang 0002, Youguang Zhang, Weisheng Zhao |
Voltage-controlled MRAM for working memory: Perspectives and challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 542-547, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori |
VAET-STT: A variation aware estimator tool for STT-MRAM based memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 1456-1461, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Nikita Gupta, Pragati Thakur, Shashank Kumar Dubey, Aminul Islam 0002 |
Design of nonvolatile MRAM bitcell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: 7th International Symposium on Embedded Computing and System Design, ISED 2017, Durgapur, India, December 18-20, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-3032-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Wenlong Cai, Kaihua Cao, Mengxing Wang, Shouzhong Peng, Jiaqi Zhou 0002, Anni Cao, Boyu Zhang, Lezhi Wang, Yu Zhang, Jiaqi Wei, Xiaobin He, Hushan Cui, Chao Zhao, Weisheng Zhao |
Interfacial property tuning of heavy metal/CoFeB for large density STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NVMTS ![In: 17th Non-Volatile Memory Technology Symposium, NVMTS 2017, Aachen, Germany, August 30 - Sept. 1, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-0477-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras |
Mitigating read & write errors in STT-MRAM memories under DVS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, pp. 1-2, 2017, IEEE, 978-1-5090-5457-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Nour Sayed, Fabian Oboril, Azadeh Shirvanian, Rajendra Bishnoi, Mehdi Baradaran Tahoori |
Exploiting STT-MRAM for approximate computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-5457-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto |
Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IVSW ![In: IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, pp. 128-133, 2017, IEEE, 978-1-5386-1708-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Kazi Asifuzzaman, Rommel Sánchez Verdejo, Petar Radojkovic |
Enabling a reliable STT-MRAM main memory simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the International Symposium on Memory Systems, MEMSYS 2017, Alexandria, VA, USA, October 02 - 05, 2017, pp. 283-292, 2017, ACM, 978-1-4503-5335-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Hengyu Zhao, Linuo Xue, Ping Chi, Jishen Zhao |
Approximate image storage with multi-level cell STT-MRAM main memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017, pp. 268-275, 2017, IEEE, 978-1-5386-3093-8. The full citation details ...](Pics/full.jpeg) |
2017 |
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