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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 84 occurrences of 72 keywords
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Results
Found 927 publication records. Showing 927 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Néstor Suárez, Gustavo Marrero Callicó, Roberto Sarmiento, Octavio Santana, Anteneh A. Abbo |
Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino |
Data-Driven Clock Gating for Digital Filters. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Monica Figueiredo, Rui L. Aguiar |
Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels |
Product On-Chip Process Compensation for Low Power and Yield Enhancement. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Ritej Bachhawat, Pankaj Golani, Peter A. Beerel |
Crosstalk in High-Performance Asynchronous Designs. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Fabio Frustaci, Marco Lanuzza |
A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard |
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Chih-Hsiang Lin, James B. Kuo |
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Wei Liu 0016, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino |
On-chip Thermal Modeling Based on SPICE Simulation. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Delong Shang, Fei Xia, Stanislavs Golubcovs, Alexandre Yakovlev |
The Magic Rule of Tiles: Virtual Delay Insensitivity. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Alexandros Bartzas, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, Fragkiskos Ieromnimon, Nikolaos S. Voros |
Dynamic Data Type Optimization and Memory Assignment Methodologies. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel |
Low Energy Voltage Dithering in Dual VDD Circuits. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Joachim Neves Rodrigues, Omer Can Akgun, Puneet Acharya, Adolfo de la Calle, Yusuf Leblebici, Viktor Öwall |
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Toby Doorn, Roelof Salters |
Robust Low Power Embedded SRAM Design: From System to Memory Cell. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Martin Barnasconi, Markus Damm, Karsten Einwich |
SystemC AMS Extensions: New Language - New Methods - New Applications. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Nikolaos Zompakis, Martin Trautmann, Alexandros Bartzas, Stylianos Mamagkakis, Dimitrios Soudris, Liesbet Van der Perre, Francky Catthoor |
Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Yoni Aizik, Gila Kamhi, Yael Zbar, Hadas Ronen, Muhammad Abozaed |
Power-Aware Design via Micro-architectural Link to Implementation. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Walter Schneider 0001, Manuel Schmidt, Bing Li 0005, Ulf Schlichtmann |
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo |
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
CMOS analog integrated circuits, frequency compensation, operational amplifiers, transient response |
1 | Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien |
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk |
Smart Enumeration: A Systematic Approach to Exhaustive Search. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Thomas Ordas, Mathieu Lisart, Etienne Sicard, Philippe Maurine, Lionel Torres |
Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Maurice Keller, William P. Marnane |
Energy Efficient Elliptic Curve Processor. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Roni Wiener, Gila Kamhi, Moshe Y. Vardi |
Intelligate: Scalable Dynamic Invariant Learning for Power Reduction. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici |
Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Sub-VToperation, variation compensation, logic style, active-mode leakage, process variations |
1 | Giorgio Boselli, Valentina Ciriani, Valentino Liberali, Gabriella Trucco |
A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki |
Power Optimization of Parallel Multipliers in Systems with Variable Word-Length. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Vasily G. Moshnyaga |
Untraditional Approach to Computer Energy Reduction. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Kostas Siozios, Dimitrios Soudris |
An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
P? CAD Algorithm, FPGA, Management, Power, 3D |
1 | Ted Vucurevic |
Power and Profit: Engineering in the Envelope. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Marco Bucci, Raimondo Luzzi, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti |
Differential Capacitance Analysis. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
security, cryptography, side-channel attacks, power analysis, DCA |
1 | Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi |
Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Mladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest |
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Rostislav (Reuven) Dobkin, Ran Ginosar |
Fast Universal Synchronizers. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
MCD, Synchronization, SoC |
1 | Yan Li 0030, Helmut Schneider, Florian Schnabel 0002, Roland Thewes, Doris Schmitt-Landsiedel |
Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro 0001, Luís Miguel Silveira |
Generating Worst-Case Stimuli for Accurate Power Grid Analysis. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Monica Figueiredo, Rui L. Aguiar |
A Study on CMOS Time Uncertainty with Technology Scaling. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Uncertainty, Noise, CMOS, Scaling, Jitter |
1 | Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija |
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis |
1 | Bing Li 0005, Christoph Knoth, Walter Schneider 0001, Manuel Schmidt, Ulf Schlichtmann |
Static Timing Model Extraction for Combinational Circuits. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Sani R. Nassif |
Model to Hardware Matching for nm Scale Technologies. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner 0001, Jürgen Becker 0001 |
Towards Novel Approaches in Design Automation for FPGA Power Optimization. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel |
A Design Space Comparison of 6T and 8T SRAM Core-Cells. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Gustavo Rau de Almeida Callou, Paulo Romero Martins Maciel, Ermeson Carneiro de Andrade, Bruno Costa e Silva Nogueira, Eduardo Tavares, Meuse N. Oliveira Jr. |
A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Energy Consumption and Execution Time, Simulation, Embedded System, Coloured Petri Net |
1 | Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala |
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
coarse-grain array, DSP, Reconfigurable systems |
1 | Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich |
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Ioannis Kouretas, Vassilis Paliouras |
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Omid Mirmotahari, Yngvar Berg |
Ultra Low Voltage High Speed Differential CMOS Inverter. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Floating-Gate (FG), High-Speed, Ultra Low Voltage (ULV) |
1 | Ruzica Jevtic, Carlos Carreras |
Analytical High-Level Power Model for LUT-Based Components. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Francisco Fernández-Nogueira, Josep Carmona 0001 |
Logic Synthesis of Handshake Components Using Structural Clustering Techniques. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner |
PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Alejandro Millán 0001, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo |
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Tsung-Yi Ho |
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Felipe Machado, Teresa Riesgo, Yago Torroja |
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
activity estimation, CAD, VHDL, BDD, power estimation, RTL, Switching activity, circuit partition, digital circuit design |
1 | Nuno Dias, Marcelino B. Santos, Floriberto A. Lima, Beatriz Vieira Borges, Júlio Paisana |
Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
DC-DC power conversion, light-load efficiency, Step-Down, Buck, low swing |
1 | Biswajit Mishra, Bashir M. Al-Hashimi |
Subthreshold FIR Filter Architecture for Ultra Low Power Applications. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Subthreshold design, Minimum Energy Point, Ultra Low Power Design, Leakage, FIR |
1 | Howard Chen 0001, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah |
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Statistical power analysis |
1 | Martin Simlastík, Viera Stopjaková |
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT |
1 | Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura |
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Arrival time variation, coupling power, power estiamtion, low power coding, on-chip bus |
1 | Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici |
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Francesc Moll, Joan Figueras, Antonio Rubio 0001 |
Data Dependence of Delay Distribution for a Planar Bus. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Floriberto A. Lima |
Integration of Power Management Units onto the SoC. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Yijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li |
The Design and Implementation of a Power Efficient Embedded SRAM. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Mini Nanua, David T. Blaauw |
Crosstalk Waveform Modeling Using Wave Fitting. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Björn Lipka, Ulrich Kleine |
Design of a Linear Power Amplifier with +/-1.5V Power Supply Using ALADIN. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, Andreas Mühlberger |
Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Ioannis Panagopoulos, Christos Pavlatos, George Manis, George K. Papakonstantinou |
A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Christer Svensson |
Analog Power Modelling. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Anders Emrich |
System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | J. M. Daga |
Design and Industrialization Challenges of Memory Dominated SOCs. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Zoltán Herczeg, Ákos Kiss 0001, Daniel Schmidt 0001, Norbert Wehn, Tibor Gyimóthy |
XEEMU: An Improved XScale Power Simulator. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Christophe Lucarz, Marco Mattavelli |
A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang |
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Marko Hoyer, Domenik Helms, Wolfgang Nebel |
Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Allan Crone, Gabriel Chidolue |
Functional Verification of Low Power Designs at RTL. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
Low power aware management, Corruption, UPF, Simulation, Retention, PCF |
1 | Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula |
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Davide Pandini, Guido A. Repetto, Vincenzo Sinisi |
Clock Distribution Techniques for Low-EMI Design. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | F. Dahlgren |
Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Ming-che Lai, Zhiying Wang 0003, Jianjun Guo, Kui Dai, Shen Li |
Template Vertical Dictionary-Based Program Compression Scheme on the TTA. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
transport triggered architecture, dictionary-based, power consumption, code compression, spatial locality |
1 | Henrik Lipskoch, Karsten Albers, Frank Slomka |
Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Noureddine Chabini |
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Nadine Azémard, Lars J. Svensson (eds.) |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine |
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | C. R. Parthasarathy, Alain Bravaix, Chloe Guérin, M. Denais, Vincent Huard |
Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Alin Razafindraibe, Michel Robert, Philippe Maurine |
Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Delong Shang, Chi-Hoon Shin, Ping Wang, Fei Xia, Albert Koelmans, Myeong-Hoon Oh, Seongwoon Kim, Alexandre Yakovlev |
Asynchronous Functional Coupling for Low Power Sensor Network Processors. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Jon Alfredsson, Snorre Aunet |
Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Julien Delorme |
An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram |
A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu |
Weakness Identification for Effective Repair of Power Distribution Network. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Lazaros Papadopoulos, Dimitrios Soudris |
System-Level Application-Specific NoC Design for Network and Multimedia Applications. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner |
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Toshinori Sato, Yuji Kunitake |
Exploiting Input Variations for Energy Reduction. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
typical-case design, dynamic retiming, reliable microarchitecture, robust microarchitecture, DVFS, deep sub-micron |
1 | Maurice Keller, William P. Marnane |
Low Power Elliptic Curve Cryptography. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Davide Pandini |
Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Jian Ruan, Zhiying Wang 0003, Kui Dai, Yong Li 0006 |
Design and Test of Self-checking Asynchronous Control Circuit. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest |
Semi Custom Design: A Case Study on SIMD Shufflers. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
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