Search results for "Verilog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Mile K. Stojcev	Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
18	Tun Li, Yang Guo 0003, GongJie Liu, Sikun Li	Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming.	DSD	2005	DBLP DOI BibTeX RDF
18	Peter Jamieson, Jonathan Rose	A Verilog RTL Synthesis Tool for Heterogeneous FPGAs.	FPL	2005	DBLP DOI BibTeX RDF
18	Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao 0001, Hamid R. Arabnia	Verilog Coding Style for Efficient Synthesis In FPGA.	CDES	2005	DBLP BibTeX RDF
18	S. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski	Behavioral test benches for digital clock and data recovery circuits using Verilog-A.	CICC	2005	DBLP DOI BibTeX RDF
18	Arash Saifhashemi, Peter A. Beerel	High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog.	CPA	2005	DBLP BibTeX RDF
18	Janick Bergeron	Modeling Usable and Reusable Transactors in System Verilog.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	Romeo Urbieta Parrazales, Enrique Guzmán-Ramírez	Diseño de Control Difuso Usando Promedio de Pesos e Implementado con Lenguaje Verilog.	Polibits	2004	DBLP DOI BibTeX RDF
18	Yuan-Bin Sha, Mu-Shun Matt Lee, Chien-Nan Jimmy Liu	On code coverage measurement for Verilog-A.	HLDVT	2004	DBLP DOI BibTeX RDF
18	Meinrad Fiedler	Ein Ubersetzungsverfahren von Verilog-Kausalspezifikationen in Signalflankengraph-basierte Spezifikationen zum Entwurf asynchroner Schaltwerke.	MBMV	2004	DBLP BibTeX RDF
18	Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu	A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code.	ISCAS (5)	2004	DBLP BibTeX RDF
18	Lubomir Ivanov	Automatic Extraction of Non-Iterated System Behavior from Verilog Specifications.	ESA/VLSI	2004	DBLP BibTeX RDF
18	Naohiko Shimizu	Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
18	Jay Lawrence	Orthogonality of Verilog Data Types and Object Kinds.	IEEE Des. Test Comput.	2003	DBLP BibTeX RDF
18	Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada	Comparative Study On Verilog-Based And C-Based Hardware Design Education.	MSE	2003	DBLP DOI BibTeX RDF
18	Junjun Li, Sopan Joshi, Elyse Rosenbaum	A Verilog-A compact model for ESD protection NMOSTs.	CICC	2003	DBLP DOI BibTeX RDF
18	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.	Embedded Systems and Applications	2003	DBLP BibTeX RDF
18	Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai	A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
18		Verilog and Other Standards.	IEEE Des. Test Comput.	2002	DBLP BibTeX RDF
18	Jordan Dimitriov	Developing semantics of Verilog HDL in formal compositional design of mixed hardware/software systems.		2002	RDF
18	Daryl Stewart	A uniform semantics for verilog and VHDL suitable for both simulation and verification		2002	RDF
18	Lionel Bening, Harry Foster	Principles of verifiable RTL design - a functional coding style supporting verification processes in Verilog.		2001	RDF
18	Jifeng He 0001, Huibiao Zhu	Formalising VERILOG.	ICECS	2000	DBLP DOI BibTeX RDF
18	Erik Lauwers, Georges G. E. Gielen, Koen Lampaert, Paolo Miliozzi	High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A.	BMAS	2000	DBLP DOI BibTeX RDF
18	Peter Frey, Donald O'Riordan	Verilog-AMS: Mixed-Signal Simulation and Cross Domain Connect Modules.	BMAS	2000	DBLP DOI BibTeX RDF
18	Zainalabedin Navabi	Hardware Description in Verilog.	The VLSI Handbook	1999	DBLP DOI BibTeX RDF
18	John Howard Eli Fiskio-Lasseter, Amr Sabry	Putting Operational Techniques to the Test: A Syntactic Theory for Behavioral Verilog.	HOOTS	1999	DBLP DOI BibTeX RDF
18	Françoise Martinolle, Charles Dawson 0002, Debra Corlette, Mike Floyd	Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI.	DATE	1999	DBLP DOI BibTeX RDF
18	Hisashi Sasaki	A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine.	DATE	1999	DBLP DOI BibTeX RDF
18	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001	Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique.	VTS	1999	DBLP DOI BibTeX RDF
18	Peter Wohl, John A. Waicukauski	Using Verilog simulation libraries for ATPG.	ITC	1999	DBLP DOI BibTeX RDF
18	Daniel C. Hyde	Using verilog HDL to teach computer architecture concepts.	WCAE@ISCA	1998	DBLP DOI BibTeX RDF
18	Gordon G. Pace	Hardware design based on Verilog HDL.		1998	RDF
18	James M. Lee	Verilog quickstart.		1997	RDF
18	Dominique Borrione, F. Vestman, H. Bouamama	An approach to Verilog-VHDL interoperability for synchronous designs.	CHARME	1997	DBLP BibTeX RDF
18	Ulrich Golze	VLSI chip design with the hardware description language VERILOG - an introduction based on a large RISC processor design.		1996	RDF
18	Donald E. Thomas, Philip Moorby	The Verilog hardware description language (3. ed.).		1996	RDF
18	Ulrich Golze	VLSI-Entwurf eines RISC-Prozessors - eine Einführung in das Design großer Chips und die Hardware-Beschreibungssprache VERILOG HDL.		1995	RDF
18	Donald E. Thomas, Philip Moorby	The Verilog hardware description language (2. ed.).		1995	RDF
18	Michael J. C. Gordon	The Semantic Challenge of Verilog HDL	LICS	1995	DBLP DOI BibTeX RDF
18	David J. Greaves	The CSYN Verilog Compiler and Other Tools.	FPL	1995	DBLP DOI BibTeX RDF
18	Raymond P. Voith	The PowerPC 603 C++ Verilog Interface Model.	COMPCON	1994	DBLP DOI BibTeX RDF
18	Felice Balarin, Gary York	Verilog HDL Modeling Styles for Formal Verification.	CHDL	1993	DBLP BibTeX RDF
18	Serge Maginot	Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I & M.	EURO-DAC	1992	DBLP DOI BibTeX RDF
10	Marc Schlickling, Markus Pister 0002	Semi-automatic derivation of timing models for WCET analysis.	LCTES	2010	DBLP DOI BibTeX RDF	vhdl, worst-case execution time, hard real-time
10	Shiuh-Jer Huang, Shian-Shin Wu	Vision-Based Robotic Motion Control for Non-autonomous Environment.	J. Intell. Robotic Syst.	2009	DBLP DOI BibTeX RDF	Self-organizing fuzzy control, FPGA chip, Visual servo, Robotic system
10	Miloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko	Experience in Virtual Testing of RSD cyclic A/D converters.	DDECS	2009	DBLP DOI BibTeX RDF
10	Warren A. Hunt Jr., Sol Swords	Centaur Technology Media Unit Verification.	CAV	2009	DBLP DOI BibTeX RDF
10	Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner	Fpga-based face detection system using Haar classifiers.	FPGA	2009	DBLP DOI BibTeX RDF	haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost
10	Jinsil Kim, Wonyoung Chung, Junghee Lee, Yongsurk Lee	An implementation of the CQS supporting multimedia traffic.	ICHIT	2009	DBLP DOI BibTeX RDF	CQS, dequeue, enqueue, scheduler
10	Rishiyur S. Nikhil	Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design).	GPCE	2009	DBLP DOI BibTeX RDF	bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing
10	Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik	Supporting RTL flow compatibility in a microarchitecture-level design framework.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	microarchitecture level, transactions, formal models, hierarchical design, hardware resources
10	Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro	Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm.	ARC	2009	DBLP DOI BibTeX RDF	Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED
10	Jamie Cullen	Evolutionary meta programming.	GEC Summit	2009	DBLP DOI BibTeX RDF	evolutionary meta compilation, evolutionary meta programming, genetic programming, evolutionary computation, grammatical evolution
10	Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David T. Blaauw	Low power circuit design based on heterojunction tunneling transistors (HETTs).	ISLPED	2009	DBLP DOI BibTeX RDF	SRAM design, low power applications, tunneling transistor
10	Syed Zafar Shazli, Mehdi Baradaran Tahoori	Soft error rate computation in early design stages using boolean satisfiability.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	soft error, hardware description language, reliability modeling
10	Adithya V. Kodati, Koneswara S. Vemuri, Lili He 0001, Morris Jones	Implementation of power managed hyper transport system for transmission of HD video.	ISQED	2009	DBLP DOI BibTeX RDF
10	Jesse D. Bingham, John Erickson, Gaurav Singh, Flemming Andersen	Industrial strength refinement checking.	FMCAD	2009	DBLP DOI BibTeX RDF
10	Zurab Khasidashvili, Gavriel Gavrielov, Tom Melham	Assume-guarantee validation for STE properties within an SVA environment.	FMCAD	2009	DBLP DOI BibTeX RDF
10	Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham	Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL.	VLSI Design	2009	DBLP DOI BibTeX RDF
10	Hong Lu, A. Forin	Automatic Processor Customization for Zero-Overhead Online Software Verification.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Hiren D. Patel, Sandeep K. Shukla	On Cosimulating Multiple Abstraction-Level System-Level Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
10	Reza M. Rad, Mohammad Tehranipoor	SCT: A novel approach for testing and configuring nanoscale devices.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Configuration and testing, reconfigurable nanoscale devices, fault tolerance, crossbar, nanowire
10	Chun-Lung Hsu, Yu-Sheng Huang	A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter
10	Grant Martin	Learning to assert yourself [review of Creating Assertion-Based IP (H.D. Foster and A.C. Krolnik; 2008)].	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
10	Santiago De Pablo, Santiago Cáceres, Jesús A. Cebrián, Manuel Berrocal, F. Sanz	ASM++ diagrams used on teaching electronic design.	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF
10	Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina	xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures.	PDP	2008	DBLP DOI BibTeX RDF	NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques
10	Jamie Cullen	Evolving Digital Circuits in an Industry Standard Hardware Description Language.	SEAL	2008	DBLP DOI BibTeX RDF
10	Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew D. Brown	A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits.	DATE	2008	DBLP DOI BibTeX RDF
10	Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi	Fault Effects in FlexRay-Based Networks with Hybrid Topology.	ARES	2008	DBLP DOI BibTeX RDF	FlexRay Protocol, Fault Injection, Error Propagation, Distributed Embedded Systems, Dependability Evaluation
10	Ansuman Banerjee, Kausik Datta, Pallab Dasgupta	CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications.	ATVA	2008	DBLP DOI BibTeX RDF
10	Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes	BenCGen: a digital circuit generation tool for benchmarks.	SBCCI	2008	DBLP DOI BibTeX RDF	benchmarks, sat solvers, combinational equivalence checking
10	Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Lei Zhang 0014, Yulu Yang, Enyue Lu, Xiao-chun Yun	Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs.	ITNG	2008	DBLP DOI BibTeX RDF	PRDT, router, NoC
10	Naoki Iwasaki, Katsumi Wasaki	A Meta Hardware Description Language Melasy for Model-Checking Systems.	ITNG	2008	DBLP DOI BibTeX RDF	Hardware/Software co-design and co-verification, Model Checking, Haskell, Design-for-test, Hardware Compilers
10	Ruchika Verma, Ali Akoglu	A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation.	IPDPS	2008	DBLP DOI BibTeX RDF
10	Jamie Cullen	Evolutionary Meta Compilation: Evolving Programs Using Real World Engineering Tools.	ICES	2008	DBLP DOI BibTeX RDF
10	David J. Greaves, Satnam Singh	Kiwi: Synthesis of FPGA Circuits from Parallel Programs.	FCCM	2008	DBLP DOI BibTeX RDF
10	Satnam Singh, David J. Greaves	Synthesizing FPGA Circuits from Parallel Programs.	ARC	2008	DBLP DOI BibTeX RDF
10	Wolfram Büttner	Complex Hardware Modules Can Now be Made Free of Functional Errors without Sacrificing Productivity.	ABZ	2008	DBLP DOI BibTeX RDF	Formal Verification, Design Process, Abstract State Machine
10	Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi	An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm.	Public Key Cryptography	2008	DBLP DOI BibTeX RDF	MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication
10	Michal Karczmarek, Arvind	Synthesis from multi-cycle atomic actions as a solution to the timing closure problem.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King Liu, Vladimir Stojanovic, Elad Alon	Integrated circuit design with NEM relays.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee	De-synchronization of a point-of-sales digital-logic controller.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Balaji V. Iyer, Thomas M. Conte	A Power Model for Register-Sharing Structures.	DIPES	2008	DBLP DOI BibTeX RDF
10	Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito	A Tiny Processing System for Education and Small Embedded Systems on the FPGAs.	EUC (2)	2008	DBLP DOI BibTeX RDF
10	Drew C. Ness, David J. Lilja	Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	fault distribution, reliability analysis, SEU, SER
10	Nathaniel J. August	A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips.	ISQED	2008	DBLP DOI BibTeX RDF	pre-silicon, validation, mixed-signal
10	Jalaj Jain	A Scalable and Reconfigurable Coprocessor for Image Composition.	VLSI Design	2008	DBLP DOI BibTeX RDF
10	Yogesh Singh Chauhan, Dimitrios Tsamados, Nicolas Abelé, Christoph Eggimann, Michel J. Declercq, Adrian M. Ionescu	Compact Modeling of Suspended Gate FET.	VLSI Design	2008	DBLP DOI BibTeX RDF
10	Shahid Rizwan	Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding.	VLSI Design	2008	DBLP DOI BibTeX RDF
10	Kyller Costa Gorgônio, Jordi Cortadella	Hardware Synthesis for Asynchronous Communications Mechanisms.	SCCC	2008	DBLP DOI BibTeX RDF
10	Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang 0009, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips	A MIPS R2000 implementation.	DAC	2008	DBLP DOI BibTeX RDF	RISC, MIPS
10	Xiang Xiao, Jaehwan John Lee	A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip.	IEEE Comput. Archit. Lett.	2007	DBLP DOI BibTeX RDF
10	Chen Shoushun, Amine Bermak	Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
10	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	An Overview of a Compiler for Mapping Software Binaries to Hardware.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
10	Edmund M. Clarke, Himanshu Jain, Daniel Kroening	Verification of SpecC using predicate abstraction.	Formal Methods Syst. Des.	2007	DBLP DOI BibTeX RDF	Verification, System level design, Predicate abstraction
10	Aggelos Ioannou, Manolis Katevenis	Pipelined heap (priority queue) management for advanced scheduling in high-speed networks.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	high-speed network scheduling, pipelined hard-ware heap, synthesizable core, weighted fair queueing, priority queue, weighted round robin
10	Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham	Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Register Transfer Level implementation, Verification, Hardware Description Languages, arithmetic logic unit
10	Felice Balarin, Roberto Passerone	Specification, Synthesis, and Simulation of Transactor Processes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
10	Maria Stepanova, Feng Lin 0002, Valerie C.-L. Lin	A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	DNA motifs, sequence structure identification, hopfield classifier, field-programmable gate arrays, recurrent neural network