Search results for "array"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Cheol-Hoon Lee, Kang G. Shin	Optimal Task Assignment in Homogeneous Networks.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Array and tree networks, homogeneous networks, network flow, task assignment, maximum flows, cutsets
23	D. L. Grundy, M. Bozic, John V. Hatfield	Development of an Analogue Microprocessor.	VLSI Design	1997	DBLP DOI BibTeX RDF	Analogue array, Analogue microprocessor, Analogue signal processing, Programmable Logarithmic, Instruction set
23	Sy-Yen Kuo, Kuochen Wang	Fault diagnosis in reconfigurable VLSI and WSI processor arrays.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF	design for diagnosability, VLSI/WSI processor array, fault diagnosis, reconfiguration, yield enhancement
23	Hsin-Chuan Kuo, Jeun-Len Wu	A new approach with orthogonal array for global optimization in design of experiments.	J. Glob. Optim.	2009	DBLP DOI BibTeX RDF	Taguchi approach, Design of experiments, Orthogonal array, Factorial
23	Yanteng Sun, Peng Li 0031, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu	HMMer acceleration using systolic array based reconfigurable architecture.	FPGA	2009	DBLP DOI BibTeX RDF	reconfigurable., systolic array, acceleration, hmmer
23	Nicoletta Dessì, Barbara Pes	A Framework for Multi-class Learning in Micro-array Data Analysis.	AIME	2009	DBLP DOI BibTeX RDF	Micro-array data analysis, Multi-class learning, Feature Selection
23	Zhai Zhang, Youren Wang, Shanshan Yang, Rui Yao, Jiang Cui	The research of self-repairing digital circuit based on embryonic cellular array.	Neural Comput. Appl.	2008	DBLP DOI BibTeX RDF	Self-repairing digital circuit, Embryonic cellular array, Fault-tolerance design, Digital circuit design
23	Zhong Wen, Liping Li, Tianqi Chen, Xixiang Zhang	Joint multiple parameters estimation for coherent chirp signals using vector sensor array.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	vector sensor array, FRFT, coherence
23	Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala	Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.	PATMOS	2008	DBLP DOI BibTeX RDF	coarse-grain array, DSP, Reconfigurable systems
23	Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Srinivas Katkoori, Pradeep Fernando, Hariharan Sankaran, Mohammad M. Mojarradi, Taher Daud	Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.	ICES	2008	DBLP DOI BibTeX RDF	Self-Healing and Compensation, Self-reconfigurable, Field Programmable Analog Array
23	Sen Zhang, Ge Nong	Fast and Space Efficient Linear Suffix Array Construction.	DCC	2008	DBLP DOI BibTeX RDF	algorithm, Suffix array, linear complexity
23	Jay B. Brockman, Sheng Li 0007, Peter M. Kogge, Amit Kashyap, Mohammad M. Mojarradi	Design of a mask-programmable memory/multiplier array using G4-FET technology.	DAC	2008	DBLP DOI BibTeX RDF	G4-FET, gate array
23	Hachiro Fujita, Kohichi Sakaniwa	Modified Low-Density MDS Array Codes for Tolerating Double Disk Failures in Disk Arrays.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	MDS array codes, double disk failures, RAID
23	Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai	An Integrated Memory Array Processor for Embedded Image Recognition Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Parallel SIMD processor, memory array processor, image processing, image recognition, parallel language
23	Simon J. Puglisi, William F. Smyth, Andrew Turpin	A taxonomy of suffix array construction algorithms.	ACM Comput. Surv.	2007	DBLP DOI BibTeX RDF	suffix sorting, suffix tree, Suffix array, Burrows-Wheeler transform
23	Keeseong Lee	3-D Object Recognition Using an Ultrasonic Sensor Array and Neural Networks.	Analysis and Design of Intelligent Systems using Soft Computing Techniques	2007	DBLP DOI BibTeX RDF	Ultrasonic Sensor Array, Invariant Moment Vectors, Neural Networks, 3-D Object Recognition
23	Minoru Watanabe, Fuminori Kobayashi	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
23	Juha Kärkkäinen, Peter Sanders 0001, Stefan Burkhardt	Linear work suffix array construction.	J. ACM	2006	DBLP DOI BibTeX RDF	Difference cover, suffix array, external memory algorithms
23	Lami Kaya, Mohammad Al-Qudah	A visual tool for trellis construction and Viterbi decoder of augmented RAC array codes.	IWCMC	2006	DBLP DOI BibTeX RDF	array codes, row and column code, trellis decoding, Viterbi decoding
23	Hari Krishna Maganti, Daniel Gatica-Perez	Speaker localization for microphone array-based ASR: the effects of accuracy on overlapping speech.	ICMI	2006	DBLP DOI BibTeX RDF	audio-visual speaker tracking, microphone array ASR
23	Ting Qin, Haitao Zhang, Zonghai Chen, Wei Xiang	Continuous CMAC-QRLS and Its Systolic Array.	Neural Process. Lett.	2005	DBLP DOI BibTeX RDF	CMAC-QRLS, systolic array, B-splines, QR decomposition
23	Gui Liang Feng, Robert H. Deng, Feng Bao 0001, Jia-Chen Shen	New Efficient MDS Array Codes for RAID Part II: Rabin-Like Codes for Tolerating Multiple (greater than or equal to 4) Disk Failures.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Rabin codes, MDS array codes, multiple disk failures, RAID
23	Chenglie Hu	2D array implementation of sorted lists.	ACM SIGCSE Bull.	2005	DBLP DOI BibTeX RDF	2D array implementation, sorted list
23	Zhenyu Liu 0001, Yang Song 0002, Takeshi Ikenaga, Satoshi Goto	A VLSI array processing oriented fast fourier transform algorithm and hardware implementation.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	singleton algorithm, fast fourier transform (FFT), array processing
23	Jen-Tzung Chien, Jain-Ray Lai	Use of Microphone Array and Model Adaptation for Hands-Free Speech Acquisition and Recognition.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	delay-and-sum beamformer, coherence measure, speech recognition, microphone array, speech enhancement, model adaptation
23	Rashindra Manniesing, Richard P. Kleihorst, André van der Avoird, Emile A. Hendriks	Power Analysis of a General Convolution Algorithm Mapped on a Linear Processor Array.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	parallel processing, VLSI design, power estimation, linear processor array
23	Arnaud Venet, Guillaume P. Brat	Precise and efficient static array bound checking for large embedded C programs.	PLDI	2004	DBLP DOI BibTeX RDF	difference-bound matrices, abstract interpretation, program verification, pointer analysis, array-bound checking
23	Chin-Fu Kuo, Ya-Shu Chen, Tei-Wei Kuo, Phone Lin, Cheng Chang	Probabilistic Real-Time Guarantees for Component-Oriented Phased Array Radars.	ICPP	2004	DBLP DOI BibTeX RDF	Probabilistic Performance Guarantee, Dwell Scheduling, Distributed Systems, Real-Time Task Scheduling, Phased Array Radar
23	Chin-Fu Kuo, Tei-Wei Kuo, Cheng Chang	Real-Time Digital Signal Processing of Phased Array Radars.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	component-oriented signal processor, system capacity estimation, digital signal processing, real-time scheduling, Phased array radar
23	Karl-Heinz Zimmermann	A Special Purpose Array Processor Architecture for the Molecular Dynamics Simulation of Point-Mutated Proteins.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	point mutation, penicillin amidase, parallel processing, molecular dynamics, protein, array processor
23	Elaine Chew, Alexandre R. J. François	MuSA.RT: music on the spiral array. real-time.	ACM Multimedia	2003	DBLP DOI BibTeX RDF	MFSM, spiral array, system implementation, music analysis, music visualization, SAI
23	Andres Figueroa, James Borneman, Tao Jiang 0001	Clustering Binary Fingerprint Vectors with Missing Values for DNA Array Data Analysis.	CSB	2003	DBLP DOI BibTeX RDF	oligonucleotide fingerprinting, DNA clone classification, DNA array, algorithm, cluster analysis
23	Ding-Ming Kwai, Behrooz Parhami	Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	control scalability, data-driven control, pipelined implementation, image compression, systolic array, vector quantization, VLSI architecture
23	Rong Lin	Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design.	ISQED	2001	DBLP DOI BibTeX RDF	IP design, inner product processor, matrix multiplier, run-time reconfigurable architecture, SOC, array multiplier, polynomial evaluation
23	Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien	A Constructive Solution to the Juggling Problem in Processor Array Synthesis.	IPDPS	2000	DBLP DOI BibTeX RDF	Systolic array synthesis, Affine scheduling
23	Chih-Yung Chang, Jang-Ping Sheu, Hsi-Chiuen Chen	Reducing Cache Conflicts by Multi-Level Cache Partitioning and Array Elements Mapping.	ICPADS	2000	DBLP DOI BibTeX RDF	array padding, multi-level cache, cache partitioning, loop tiling, direct mapping, cache conflict
23	Keqin Li 0001, Yi Pan 0001, Si-Qing Zheng	Fast and Processor Efficient Parallel Matrix Multiplication Algorithms on a Linear Array With a Reconfigurable Pipelined Bus System.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	Compound algorithm, optical pipelined bus, Strassen's algorithm, reconfigurability, matrix multiplication, linear array
23	Eric Hung-Yu Tseng, Jean-Luc Gaudiot	Two Techniques for Static Array Partitioning on Message-Passing Parallel Machines.	IEEE PACT	1997	DBLP DOI BibTeX RDF	Automatic Array Partitioning, Communication-Free, Message-Passing, Parallel Compiler, Data Parallelism
23	K. Gopinath, R. Seshadri	Alias Analysis for Fortran90 Array Slices.	IPPS	1997	DBLP DOI BibTeX RDF	Fortran90 array slices, static alias analysis, optimising compilers, optimising compiler
23	Chandra Tan, Donald W. Bouldin, Peyman H. Dehkordi	Design Implementation of Intrinsic Area Array ICs.	ARVLSI	1997	DBLP DOI BibTeX RDF	Area-array pad, flip-chip, physical design, VLSI design, placement and routing
23	Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.	Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT.	ASAP	1996	DBLP DOI BibTeX RDF	finite word-length effects, unified systolic array, fixed-point error analysis, inverse discrete cosine transform, fixed-point rounding-errors, minimum word-length, fixed-point error, discrete cosine transforms, discrete cosine transform, systolic arrays, digital simulation, error analysis, simulation results, roundoff errors, closed form expressions, truncation-errors
23	Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger	A Synthesis System For Bus-Based Wavefront Array Architectures.	ASAP	1996	DBLP DOI BibTeX RDF	synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations
23	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	A cellular array designed from a Multiple-valued Decision Diagram and its fault tests.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults
23	Lizyamma Kurian, Daniel Brewer, Eugene John	Design of a highly reconfigurable interconnect for array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies
23	Doran Wilde, Sanjay V. Rajopadhye	The naive execution of affine recurrence equations.	ASAP	1995	DBLP DOI BibTeX RDF	algorithmic languages, regular arrays, ALPHA language, computer aided design methodology, regular array architectures, algorithmic specification, imperative sequential language C, applicative caching, 1-dimensional storage, formal specification, circuit CAD, hardware description languages, nested loops, polyhedron, transformational approach, C-code, affine recurrence equations
23	Maurice Clint, Jim Weston, J. B. Flannagan	Efficient Gram-Schmidt Orthogonalisation on an Array Processor.	CONPAR	1994	DBLP DOI BibTeX RDF	Orthogonalisation, Modified Gram-Schmidt, parallelism, array processors
23	Kichul Kim, Viktor K. Prasanna	Latin Squares for Parallel Array Access.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	parallel array access, perfect latin squares, skewing functions, self-routing Benes networks, shared memory systems, storage management, multiprocessorinterconnection networks, conflict free access, skewing scheme, parallel memory system
23	Trenchard More Jr.	Transfinite Nesting in Array-Theoretic Figures, Changes, Rigs, and Arms, Part I.	APL	1993	DBLP DOI BibTeX RDF	APL2, Nial, array theory, function arrays, nested arrays, APL, formal systems
23	Peter R. Cappello	A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	hexagon shaped, cylinder connected, processor-time-minimal systolic array, cubical meshalgorithms, time-minimal multiprocessor schedules, processor-time-minimal scheduling, triangular shaped 2-D directed mesh, 2-D directed mesh, directedgraphs, parallel algorithms, computational complexity, topology, systolic arrays, directed acyclic graph, processing elements, matrix product
23	Chris J. Scheiman, Peter R. Cappello	A Processor-Time-Minimal Systolic Array for Transitive Closure.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	processor-time-minimal multiprocessor schedules, 2-D mesh, parallel algorithms, systolic array, systolic arrays, directed acyclic graph, multiprocessor schedule, transitive closure
22	Rong Lin, Stephan Olariu	A simple array processor for binary prefix sums.	ASAP	1995	DBLP DOI BibTeX RDF	binary prefix sums, storage compaction, routing, computational complexity, parallel processing, VLSI, network routing, circuit CAD, array processor, binary sequence, special-purpose architecture, processor assignment, operating system design
22	Yang Li, Lijun Ji, Jianxing Yin	Covering arrays of strength 3 and 4 from holey difference matrices.	Des. Codes Cryptogr.	2009	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 05B20, 94C12, 05B15
22	Ricardo S. Ferreira 0001, Alex Damiany, Julio C. Goldner Vendramini, Tiago Teixeira, João M. P. Cardoso	On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks.	ARC	2009	DBLP DOI BibTeX RDF
22	Patchara Sutthiwan, Jingyu Ye, Yun Q. Shi 0001	An Enhanced Statistical Approach to Identifying Photorealistic Images.	IWDW	2009	DBLP DOI BibTeX RDF	Moments of Characteristic Functions, Computer graphics classification, boosting
22	William A. Lintz, John C. McEachen, Murali Tummala	Sensor beamforming with distributed mobile elements in a wireless sensor network.	CCECE	2009	DBLP DOI BibTeX RDF
22	Michael J. Gans	Channel Capacity Between Antenna Arrays - Part I: Sky Noise Dominates.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
22	Minoru Watanabe, Fuminori Kobayashi	A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory.	FPL	2006	DBLP DOI BibTeX RDF
22	Souradyuti Paul, Bart Preneel	On the (In)security of Stream Ciphers Based on Arrays and Modular Addition.	ASIACRYPT	2006	DBLP DOI BibTeX RDF
22	Weiwei Ma, M. E. Kaye, D. M. Luke, R. Doraiswami	An FPGA-Based Singular Value Decomposition Processor.	CCECE	2006	DBLP DOI BibTeX RDF
22	S. T. Smith	Statistical resolution limits and the complexified Cramér-Rao bound.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
22	Manuel M. T. Chakravarty, Gabriele Keller	An Approach to Fast Arrays in Haskell.	Advanced Functional Programming	2002	DBLP DOI BibTeX RDF
22	Mustafa Uysal, Guillermo A. Alvarez, Arif Merchant	A Modular, Analytical Throughput Model for Modern Disk Arrays.	MASCOTS	2001	DBLP DOI BibTeX RDF
22	Tadayoshi Horita, Itsuo Takanami	Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	The 1$frac{1}{2}$-track switch model, reconfiguration, yield enhancement, wafer scale integration, mesh-connected processor arrays
22	W. Shi, K. Kumar, Fabrizio Lombardi	On the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips.	DFT	2000	DBLP DOI BibTeX RDF
22	Nobuo Tsuda, Tatsuyuki Shimizu	Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct Replacement.	ISPAN	2000	DBLP DOI BibTeX RDF
22	Vishwani D. Agrawal, Srimat T. Chakradhar	Combinational ATPG theorems for identifying untestable faults in sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
22	Dennis Holmes, John E. Howland	APROL: a Hybrid Language.	APL	1993	DBLP DOI BibTeX RDF	APL, LISP, SCHEME
22	Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath	New algorithms for reconfiguring VLSI/WSI arrays.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
22	Xiaoxiong Zhong, Sanjay V. Rajopadhye	Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions.	PARLE (1)	1991	DBLP DOI BibTeX RDF
22	F. Evans, Jan Jantzen	A Structured Approach to Analysis and Design of Complex Systems.	APL	1990	DBLP DOI BibTeX RDF	APL
22	Adrian Vrouwenvelder, Keith R. Allen, Roy P. Pargas	Translating systolic arrays into instruction systolic arrays.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF	SAGE
22	P. Geoffrey Lowney	Carrier Arrays: An Idiom-Preserving Extension to APL.	POPL	1981	DBLP DOI BibTeX RDF
22	Junli Liang, Ding Liu, Junying Zhang	Joint frequency, 2-D DOA, and polarization estimation using parallel factor analysis.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	parallel factor analysis, polarization sensitive array, array signal processing, cumulant
22	Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005	Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array
22	Jean Paul Stromboni	Partitioning regular computational graphs.	EUROMICRO	1997	DBLP DOI BibTeX RDF	regular computational graph partitioning, massive applications, computational graph, array processing operations, strong regularity, dependence vectors, loop parameters, periodic dependence constraints, small example regular graph, parallel processing, program analysis, signal processing, parallel machine, nested loops, application program, array signal processing, application designer, loop nests
22	John M. Silkaitis, Hua Lee	Spectral segmentation and multiple frequency-band tomographic backward propagation technique for high-resolution sonar imaging.	ICIP	1995	DBLP DOI BibTeX RDF	sonar imaging, acoustic tomography, acoustic holography, acoustic wave propagation, spectral segmentation, multiple frequency band, tomographic backward propagation, high resolution sonar imaging, received array time data, plane waves superposition, wavelengths, received plane waves, holographic reconstructions, phase shift beamforming algorithm, performance, image segmentation, image reconstruction, bandwidth, spectral analysis, image resolution, array signal processing, image space, tomographic image reconstruction
22	Man-Fai Yu, Wayne Wei-Ming Dai	Single-layer fanout routing and routability analysis for Ball Grid Arrays.	ICCAD	1995	DBLP DOI BibTeX RDF	package routing, ball grid array, pin grid array, planar routing, even wiring, fanout routing, routability
22	Oscar H. Ibarra, Stephen M. Sohn	On Mapping Systolic Algorithms onto the Hypercube.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	parallel to parallel mappings, time-space graph, one way linear systolic array, systolic array algorithms, fixed-size hypercube architecture, two-dimensional systolic arrays, 64-node NCUBE/7 MIMD hypercube machine, shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, Boolean transitive closure, performance evaluation, parallel algorithms, computational complexity, parallel computers, parallel architectures, hypercube, matrix multiplication, interprocessor communication, cellular arrays, systolic algorithms, local computation
21	Esa Ollila, Visa Koivunen	Influence Function and Asymptotic Efficiency of Scatter Matrix Based Array Processors: Case MVDR Beamformer.	IEEE Trans. Signal Process.	2009	DBLP DOI BibTeX RDF
21	Enno Ohlebusch, Simon Gog	A Compressed Enhanced Suffix Array Supporting Fast String Matching.	SPIRE	2009	DBLP DOI BibTeX RDF
21	Hasan Saeed Mir	A Generalized Transfer-Function Based Array Calibration Technique for Direction Finding.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
21	Keigo Hirakawa, Patrick J. Wolfe	Spatio-Spectral Color Filter Array Design for Optimal Image Recovery.	IEEE Trans. Image Process.	2008	DBLP DOI BibTeX RDF
21	Supawat Supakwong, Athanassios Manikas, Anthony G. Constantinides	Analysis of three-parameter diversely polarized array manifold.	PIMRC	2008	DBLP DOI BibTeX RDF
21	Etan Fisher, Boaz Rafaely	The nearfield spherical microphone array.	ICASSP	2008	DBLP DOI BibTeX RDF
21	Scott Miller, Mihai Sima, Michael McGuire	VLSI implementation of a shift-enabled reconfigurable array.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Bahram Kouhi-Jelehkaran, Farbod Razzazi, Hamidreza Bakhshi	Maximum-Likelihood Phone-Based Filter Parameter Optimization for Microphone Array Speech Recognition.	CSSE (1)	2008	DBLP DOI BibTeX RDF
21	D. Dhanasekaran, K. Boopathy Bagan	Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit.	VLSI Design	2008	DBLP DOI BibTeX RDF	Virtual Reconfigurable circuit, element validation, Evolvable hardware
21	Sungbok Kim, Sanghyup Lee	Optical Mouse Array Position Calibration for Mobile Robot Velocity Estimation.	RAM	2008	DBLP DOI BibTeX RDF
21	Mika Takata, Yasuo Matsuyama	Protein Folding Classification by Committee SVM Array.	ICONIP (2)	2008	DBLP DOI BibTeX RDF
21	Sebastiaan van der Tol, Brian D. Jeffs, Alle-Jan van der Veen	Self-Calibration for the LOFAR Radio Astronomical Array.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
21	Hari Krishna Maganti, Daniel Gatica-Perez, Iain McCowan	Speech Enhancement and Recognition in Meetings With an Audio-Visual Sensor Array.	IEEE Trans. Speech Audio Process.	2007	DBLP DOI BibTeX RDF
21	Christophe Alias, Fabrice Baray, Alain Darte	Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose.	LCTES	2007	DBLP DOI BibTeX RDF	program analysis, lattices, source-to-source transformations, memory reduction
21	Ezequiel Herruzo, Emilio L. Zapata, Oscar G. Plata	Maximum and Sorted Cache Occupation Using Array Padding.	ICSAMOS	2007	DBLP DOI BibTeX RDF
21	Milan Narandzic, Martin Käske, Christian Schneider 0003, Marko Milojevic, Markus H. Landmann, Gerd Sommerkorn, Reiner S. Thomä	3D-Antenna Array Model for IST-WINNER Channel Simulations.	VTC Spring	2007	DBLP DOI BibTeX RDF
21	Mackale Joyner, Zoran Budimlic, Vivek Sarkar	Optimizing Array Accesses in High Productivity Languages.	HPCC	2007	DBLP DOI BibTeX RDF
21	Yongsheng Yin, Li Li 0003, Minglun Gao, Gaoming Du, Yu-Kun Song	On the Implementation of Virtual Array Using Configuration Plane.	APPT	2007	DBLP DOI BibTeX RDF
21	Clyde Clarke, Carl White, Ralph Etienne-Cummings	Design and Optimization of a Capacitive Micromachined Ultrasonic Transducer Micro-Array for Near Field Sensing.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu	A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.	ISQED	2007	DBLP DOI BibTeX RDF
21	Olgica Milenkovic, Navin Kashyap, David Leyba	Shortened Array Codes of Large Girth.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
21	Kai Trojahner, Clemens Grelck, Sven-Bodo Scholz	On Optimising Shape-Generic Array Programs Using Symbolic Structural Information.	IFL	2006	DBLP DOI BibTeX RDF