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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 27028 publication records. Showing 27027 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
23 | Cheol-Hoon Lee, Kang G. Shin |
Optimal Task Assignment in Homogeneous Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(2), pp. 119-129, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Array and tree networks, homogeneous networks, network flow, task assignment, maximum flows, cutsets |
23 | D. L. Grundy, M. Bozic, John V. Hatfield |
Development of an Analogue Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 420-424, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Analogue array, Analogue microprocessor, Analogue signal processing, Programmable Logarithmic, Instruction set |
23 | Sy-Yen Kuo, Kuochen Wang |
Fault diagnosis in reconfigurable VLSI and WSI processor arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 2(3), pp. 173-187, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
design for diagnosability, VLSI/WSI processor array, fault diagnosis, reconfiguration, yield enhancement |
23 | Hsin-Chuan Kuo, Jeun-Len Wu |
A new approach with orthogonal array for global optimization in design of experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Glob. Optim. ![In: J. Glob. Optim. 44(4), pp. 563-578, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Taguchi approach, Design of experiments, Orthogonal array, Factorial |
23 | Yanteng Sun, Peng Li 0031, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu |
HMMer acceleration using systolic array based reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 282, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reconfigurable., systolic array, acceleration, hmmer |
23 | Nicoletta Dessì, Barbara Pes |
A Framework for Multi-class Learning in Micro-array Data Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AIME ![In: Artificial Intelligence in Medicine, 12th Conference on Artificial Intelligence in Medicine, AIME 2009, Verona, Italy, July 18-22, 2009. Proceedings, pp. 275-284, 2009, 978-3-642-02975-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Micro-array data analysis, Multi-class learning, Feature Selection |
23 | Zhai Zhang, Youren Wang, Shanshan Yang, Rui Yao, Jiang Cui |
The research of self-repairing digital circuit based on embryonic cellular array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 17(2), pp. 145-151, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Self-repairing digital circuit, Embryonic cellular array, Fault-tolerance design, Digital circuit design |
23 | Zhong Wen, Liping Li, Tianqi Chen, Xixiang Zhang |
Joint multiple parameters estimation for coherent chirp signals using vector sensor array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(1), pp. 93-100, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
vector sensor array, FRFT, coherence |
23 | Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala |
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 297-306, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
coarse-grain array, DSP, Reconfigurable systems |
23 | Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Srinivas Katkoori, Pradeep Fernando, Hariharan Sankaran, Mohammad M. Mojarradi, Taher Daud |
Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, pp. 225-236, 2008, Springer, 978-3-540-85856-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Self-Healing and Compensation, Self-reconfigurable, Field Programmable Analog Array |
23 | Sen Zhang, Ge Nong |
Fast and Space Efficient Linear Suffix Array Construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCC ![In: 2008 Data Compression Conference (DCC 2008), 25-27 March 2008, Snowbird, UT, USA, pp. 553, 2008, IEEE Computer Society, 978-0-7695-3121-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
algorithm, Suffix array, linear complexity |
23 | Jay B. Brockman, Sheng Li 0007, Peter M. Kogge, Amit Kashyap, Mohammad M. Mojarradi |
Design of a mask-programmable memory/multiplier array using G4-FET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 337-338, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
G4-FET, gate array |
23 | Hachiro Fujita, Kohichi Sakaniwa |
Modified Low-Density MDS Array Codes for Tolerating Double Disk Failures in Disk Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(4), pp. 563-566, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MDS array codes, double disk failures, RAID |
23 | Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai |
An Integrated Memory Array Processor for Embedded Image Recognition Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(5), pp. 622-634, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Parallel SIMD processor, memory array processor, image processing, image recognition, parallel language |
23 | Simon J. Puglisi, William F. Smyth, Andrew Turpin |
A taxonomy of suffix array construction algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 39(2), pp. 4, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
suffix sorting, suffix tree, Suffix array, Burrows-Wheeler transform |
23 | Keeseong Lee |
3-D Object Recognition Using an Ultrasonic Sensor Array and Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analysis and Design of Intelligent Systems using Soft Computing Techniques ![In: Analysis and Design of Intelligent Systems using Soft Computing Techniques, a selection of papers from IFSA 2007, pp. 306-315, 2007, Springer, 978-3-540-72431-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Ultrasonic Sensor Array, Invariant Moment Vectors, Neural Networks, 3-D Object Recognition |
23 | Minoru Watanabe, Fuminori Kobayashi |
A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 124-125, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip |
23 | Juha Kärkkäinen, Peter Sanders 0001, Stefan Burkhardt |
Linear work suffix array construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 53(6), pp. 918-936, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Difference cover, suffix array, external memory algorithms |
23 | Lami Kaya, Mohammad Al-Qudah |
A visual tool for trellis construction and Viterbi decoder of augmented RAC array codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing, IWCMC 2006, Vancouver, British Columbia, Canada, July 3-6, 2006, pp. 1471-1475, 2006, ACM, 1-59593-306-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
array codes, row and column code, trellis decoding, Viterbi decoding |
23 | Hari Krishna Maganti, Daniel Gatica-Perez |
Speaker localization for microphone array-based ASR: the effects of accuracy on overlapping speech. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMI ![In: Proceedings of the 8th International Conference on Multimodal Interfaces, ICMI 2006, Banff, Alberta, Canada, November 2-4, 2006, pp. 35-38, 2006, ACM, 1-59593-541-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
audio-visual speaker tracking, microphone array ASR |
23 | Ting Qin, Haitao Zhang, Zonghai Chen, Wei Xiang |
Continuous CMAC-QRLS and Its Systolic Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Process. Lett. ![In: Neural Process. Lett. 22(1), pp. 1-16, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CMAC-QRLS, systolic array, B-splines, QR decomposition |
23 | Gui Liang Feng, Robert H. Deng, Feng Bao 0001, Jia-Chen Shen |
New Efficient MDS Array Codes for RAID Part II: Rabin-Like Codes for Tolerating Multiple (greater than or equal to 4) Disk Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(12), pp. 1473-1483, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Rabin codes, MDS array codes, multiple disk failures, RAID |
23 | Chenglie Hu |
2D array implementation of sorted lists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGCSE Bull. ![In: ACM SIGCSE Bull. 37(2), pp. 36-40, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
2D array implementation, sorted list |
23 | Zhenyu Liu 0001, Yang Song 0002, Takeshi Ikenaga, Satoshi Goto |
A VLSI array processing oriented fast fourier transform algorithm and hardware implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 291-295, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
singleton algorithm, fast fourier transform (FFT), array processing |
23 | Jen-Tzung Chien, Jain-Ray Lai |
Use of Microphone Array and Model Adaptation for Hands-Free Speech Acquisition and Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 36(2-3), pp. 141-151, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
delay-and-sum beamformer, coherence measure, speech recognition, microphone array, speech enhancement, model adaptation |
23 | Rashindra Manniesing, Richard P. Kleihorst, André van der Avoird, Emile A. Hendriks |
Power Analysis of a General Convolution Algorithm Mapped on a Linear Processor Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 37(1), pp. 5-19, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
parallel processing, VLSI design, power estimation, linear processor array |
23 | Arnaud Venet, Guillaume P. Brat |
Precise and efficient static array bound checking for large embedded C programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, Washington, DC, USA, June 9-11, 2004, pp. 231-242, 2004, ACM, 1-58113-807-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
difference-bound matrices, abstract interpretation, program verification, pointer analysis, array-bound checking |
23 | Chin-Fu Kuo, Ya-Shu Chen, Tei-Wei Kuo, Phone Lin, Cheng Chang |
Probabilistic Real-Time Guarantees for Component-Oriented Phased Array Radars. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 33rd International Conference on Parallel Processing (ICPP 2004), 15-18 August 2004, Montreal, Quebec, Canada, pp. 233-240, 2004, IEEE Computer Society, 0-7695-2197-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Probabilistic Performance Guarantee, Dwell Scheduling, Distributed Systems, Real-Time Task Scheduling, Phased Array Radar |
23 | Chin-Fu Kuo, Tei-Wei Kuo, Cheng Chang |
Real-Time Digital Signal Processing of Phased Array Radars. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(5), pp. 433-446, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
component-oriented signal processor, system capacity estimation, digital signal processing, real-time scheduling, Phased array radar |
23 | Karl-Heinz Zimmermann |
A Special Purpose Array Processor Architecture for the Molecular Dynamics Simulation of Point-Mutated Proteins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 35(3), pp. 297-309, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
point mutation, penicillin amidase, parallel processing, molecular dynamics, protein, array processor |
23 | Elaine Chew, Alexandre R. J. François |
MuSA.RT: music on the spiral array. real-time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Multimedia ![In: Proceedings of the Eleventh ACM International Conference on Multimedia, Berkeley, CA, USA, November 2-8, 2003, pp. 448-449, 2003, ACM, 1-58113-722-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
MFSM, spiral array, system implementation, music analysis, music visualization, SAI |
23 | Andres Figueroa, James Borneman, Tao Jiang 0001 |
Clustering Binary Fingerprint Vectors with Missing Values for DNA Array Data Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSB ![In: 2nd IEEE Computer Society Bioinformatics Conference, CSB 2003, Stanford, CA, USA, August 11-14, 2003, pp. 38-47, 2003, IEEE Computer Society, 0-7695-2000-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
oligonucleotide fingerprinting, DNA clone classification, DNA array, algorithm, cluster analysis |
23 | Ding-Ming Kwai, Behrooz Parhami |
Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(3), pp. 235-243, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
control scalability, data-driven control, pipelined implementation, image compression, systolic array, vector quantization, VLSI architecture |
23 | Rong Lin |
Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 325-330, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
IP design, inner product processor, matrix multiplier, run-time reconfigurable architecture, SOC, array multiplier, polynomial evaluation |
23 | Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien |
A Constructive Solution to the Juggling Problem in Processor Array Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 815-822, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Systolic array synthesis, Affine scheduling |
23 | Chih-Yung Chang, Jang-Ping Sheu, Hsi-Chiuen Chen |
Reducing Cache Conflicts by Multi-Level Cache Partitioning and Array Elements Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: Seventh International Conference on Parallel and Distributed Systems, ICPADS 2000, Iwate, Japan, July 4-7, 2000, pp. 195-202, 2000, IEEE Computer Society, 0-7695-0568-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
array padding, multi-level cache, cache partitioning, loop tiling, direct mapping, cache conflict |
23 | Keqin Li 0001, Yi Pan 0001, Si-Qing Zheng |
Fast and Processor Efficient Parallel Matrix Multiplication Algorithms on a Linear Array With a Reconfigurable Pipelined Bus System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(8), pp. 705-720, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Compound algorithm, optical pipelined bus, Strassen's algorithm, reconfigurability, matrix multiplication, linear array |
23 | Eric Hung-Yu Tseng, Jean-Luc Gaudiot |
Two Techniques for Static Array Partitioning on Message-Passing Parallel Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 225-235, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Automatic Array Partitioning, Communication-Free, Message-Passing, Parallel Compiler, Data Parallelism |
23 | K. Gopinath, R. Seshadri |
Alias Analysis for Fortran90 Array Slices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 628-632, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Fortran90 array slices, static alias analysis, optimising compilers, optimising compiler |
23 | Chandra Tan, Donald W. Bouldin, Peyman H. Dehkordi |
Design Implementation of Intrinsic Area Array ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 82-95, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Area-array pad, flip-chip, physical design, VLSI design, placement and routing |
23 | Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr. |
Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 35-, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
finite word-length effects, unified systolic array, fixed-point error analysis, inverse discrete cosine transform, fixed-point rounding-errors, minimum word-length, fixed-point error, discrete cosine transforms, discrete cosine transform, systolic arrays, digital simulation, error analysis, simulation results, roundoff errors, closed form expressions, truncation-errors |
23 | Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger |
A Synthesis System For Bus-Based Wavefront Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 274-283, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations |
23 | Naotake Kamiura, Yutaka Hata, Kazuharu Yamato |
A cellular array designed from a Multiple-valued Decision Diagram and its fault tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 20-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults |
23 | Lizyamma Kurian, Daniel Brewer, Eugene John |
Design of a highly reconfigurable interconnect for array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 321-325, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies |
23 | Doran Wilde, Sanjay V. Rajopadhye |
The naive execution of affine recurrence equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 1-12, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
algorithmic languages, regular arrays, ALPHA language, computer aided design methodology, regular array architectures, algorithmic specification, imperative sequential language C, applicative caching, 1-dimensional storage, formal specification, circuit CAD, hardware description languages, nested loops, polyhedron, transformational approach, C-code, affine recurrence equations |
23 | Maurice Clint, Jim Weston, J. B. Flannagan |
Efficient Gram-Schmidt Orthogonalisation on an Array Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 218-228, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Orthogonalisation, Modified Gram-Schmidt, parallelism, array processors |
23 | Kichul Kim, Viktor K. Prasanna |
Latin Squares for Parallel Array Access. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(4), pp. 361-370, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
parallel array access, perfect latin squares, skewing functions, self-routing Benes networks, shared memory systems, storage management, multiprocessorinterconnection networks, conflict free access, skewing scheme, parallel memory system |
23 | Trenchard More Jr. |
Transfinite Nesting in Array-Theoretic Figures, Changes, Rigs, and Arms, Part I. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Proceedings of the International Conference on APL 1993, Toronto, Ontario, Canada, August 15-19, 1993., pp. 170-184, 1993, ACM, 0-89791-612-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
APL2, Nial, array theory, function arrays, nested arrays, APL, formal systems |
23 | Peter R. Cappello |
A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(1), pp. 4-13, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
hexagon shaped, cylinder connected, processor-time-minimal systolic array, cubical meshalgorithms, time-minimal multiprocessor schedules, processor-time-minimal scheduling, triangular shaped 2-D directed mesh, 2-D directed mesh, directedgraphs, parallel algorithms, computational complexity, topology, systolic arrays, directed acyclic graph, processing elements, matrix product |
23 | Chris J. Scheiman, Peter R. Cappello |
A Processor-Time-Minimal Systolic Array for Transitive Closure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(3), pp. 257-269, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
processor-time-minimal multiprocessor schedules, 2-D mesh, parallel algorithms, systolic array, systolic arrays, directed acyclic graph, multiprocessor schedule, transitive closure |
22 | Rong Lin, Stephan Olariu |
A simple array processor for binary prefix sums. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 113-, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
binary prefix sums, storage compaction, routing, computational complexity, parallel processing, VLSI, network routing, circuit CAD, array processor, binary sequence, special-purpose architecture, processor assignment, operating system design |
22 | Yang Li, Lijun Ji, Jianxing Yin |
Covering arrays of strength 3 and 4 from holey difference matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 50(3), pp. 339-350, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classification (2000) 05B20, 94C12, 05B15 |
22 | Ricardo S. Ferreira 0001, Alex Damiany, Julio C. Goldner Vendramini, Tiago Teixeira, João M. P. Cardoso |
On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 145-156, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Patchara Sutthiwan, Jingyu Ye, Yun Q. Shi 0001 |
An Enhanced Statistical Approach to Identifying Photorealistic Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWDW ![In: Digital Watermarking, 8th International Workshop, IWDW 2009, Guildford, UK, August 24-26, 2009. Proceedings, pp. 323-335, 2009, Springer, 978-3-642-03687-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Moments of Characteristic Functions, Computer graphics classification, boosting |
22 | William A. Lintz, John C. McEachen, Murali Tummala |
Sensor beamforming with distributed mobile elements in a wireless sensor network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 323-328, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Michael J. Gans |
Channel Capacity Between Antenna Arrays - Part I: Sky Noise Dominates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 54(9), pp. 1586-1592, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Minoru Watanabe, Fuminori Kobayashi |
A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Souradyuti Paul, Bart Preneel |
On the (In)security of Stream Ciphers Based on Arrays and Modular Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIACRYPT ![In: Advances in Cryptology - ASIACRYPT 2006, 12th International Conference on the Theory and Application of Cryptology and Information Security, Shanghai, China, December 3-7, 2006, Proceedings, pp. 69-83, 2006, Springer, 3-540-49475-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Weiwei Ma, M. E. Kaye, D. M. Luke, R. Doraiswami |
An FPGA-Based Singular Value Decomposition Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1047-1050, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | S. T. Smith |
Statistical resolution limits and the complexified Cramér-Rao bound. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 53(5), pp. 1597-1609, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Manuel M. T. Chakravarty, Gabriele Keller |
An Approach to Fast Arrays in Haskell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Advanced Functional Programming ![In: Advanced Functional Programming, 4th International School, AFP 2002, Oxford, UK, August 19-24, 2002, Revised Lectures, pp. 27-58, 2002, Springer, 3-540-40132-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Mustafa Uysal, Guillermo A. Alvarez, Arif Merchant |
A Modular, Analytical Throughput Model for Modern Disk Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 9th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2001), 15-18 August 2001, Cincinnati, OH, USA, pp. 183-192, 2001, IEEE Computer Society, 0-7695-1315-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Tadayoshi Horita, Itsuo Takanami |
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(6), pp. 542-552, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
The 1$frac{1}{2}$-track switch model, reconfiguration, yield enhancement, wafer scale integration, mesh-connected processor arrays |
22 | W. Shi, K. Kumar, Fabrizio Lombardi |
On the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 125-134, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Nobuo Tsuda, Tatsuyuki Shimizu |
Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct Replacement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 5th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2000), 7-10 December 2000, Dallas / Richardson, TX, USA, pp. 24-29, 2000, IEEE Computer Society, 0-7695-0936-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Vishwani D. Agrawal, Srimat T. Chakradhar |
Combinational ATPG theorems for identifying untestable faults in sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9), pp. 1155-1160, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Dennis Holmes, John E. Howland |
APROL: a Hybrid Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Proceedings of the International Conference on APL 1993, Toronto, Ontario, Canada, August 15-19, 1993., pp. 112-123, 1993, ACM, 0-89791-612-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
APL, LISP, SCHEME |
22 | Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath |
New algorithms for reconfiguring VLSI/WSI arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(4), pp. 329-344, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
22 | Xiaoxiong Zhong, Sanjay V. Rajopadhye |
Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (1) ![In: PARLE '91: Parallel Architectures and Languages Europe, Volume I: Parallel Architectures and Algorithms, Eindhoven, The Netherlands, June 10-13, 1991, Proceedings, pp. 219-236, 1991, Springer, 3-540-54151-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
22 | F. Evans, Jan Jantzen |
A Structured Approach to Analysis and Design of Complex Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Conference Proceedings on APL 90: For the Future, APL 1990, Copenhagen, Denmark, August 13-17, 1990., pp. 104, 1990, ACM, 0-89791-371-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
APL |
22 | Adrian Vrouwenvelder, Keith R. Allen, Roy P. Pargas |
Translating systolic arrays into instruction systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the Sixteenth ACM Annual Conference on Computer Science, Atlanta, Georgia, USA, February 23-25, 1988, pp. 357-365, 1988, ACM, 0-89791-260-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
SAGE |
22 | P. Geoffrey Lowney |
Carrier Arrays: An Idiom-Preserving Extension to APL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Conference Record of the Eighth Annual ACM Symposium on Principles of Programming Languages, Williamsburg, Virginia, USA, January 1981, pp. 1-13, 1981, ACM Press, 0-89791-029-X. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
|
22 | Junli Liang, Ding Liu, Junying Zhang |
Joint frequency, 2-D DOA, and polarization estimation using parallel factor analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 52(10), pp. 1891-1904, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
parallel factor analysis, polarization sensitive array, array signal processing, cumulant |
22 | Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005 |
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 449-462, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array |
22 | Jean Paul Stromboni |
Partitioning regular computational graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 431-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
regular computational graph partitioning, massive applications, computational graph, array processing operations, strong regularity, dependence vectors, loop parameters, periodic dependence constraints, small example regular graph, parallel processing, program analysis, signal processing, parallel machine, nested loops, application program, array signal processing, application designer, loop nests |
22 | John M. Silkaitis, Hua Lee |
Spectral segmentation and multiple frequency-band tomographic backward propagation technique for high-resolution sonar imaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP ![In: Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995, pp. 457-460, 1995, IEEE Computer Society, 0-8186-7310-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
sonar imaging, acoustic tomography, acoustic holography, acoustic wave propagation, spectral segmentation, multiple frequency band, tomographic backward propagation, high resolution sonar imaging, received array time data, plane waves superposition, wavelengths, received plane waves, holographic reconstructions, phase shift beamforming algorithm, performance, image segmentation, image reconstruction, bandwidth, spectral analysis, image resolution, array signal processing, image space, tomographic image reconstruction |
22 | Man-Fai Yu, Wayne Wei-Ming Dai |
Single-layer fanout routing and routability analysis for Ball Grid Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 581-586, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
package routing, ball grid array, pin grid array, planar routing, even wiring, fanout routing, routability |
22 | Oscar H. Ibarra, Stephen M. Sohn |
On Mapping Systolic Algorithms onto the Hypercube. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(1), pp. 48-63, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
parallel to parallel mappings, time-space graph, one way linear systolic array, systolic array algorithms, fixed-size hypercube architecture, two-dimensional systolic arrays, 64-node NCUBE/7 MIMD hypercube machine, shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, Boolean transitive closure, performance evaluation, parallel algorithms, computational complexity, parallel computers, parallel architectures, hypercube, matrix multiplication, interprocessor communication, cellular arrays, systolic algorithms, local computation |
21 | Esa Ollila, Visa Koivunen |
Influence Function and Asymptotic Efficiency of Scatter Matrix Based Array Processors: Case MVDR Beamformer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 57(1), pp. 247-259, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Enno Ohlebusch, Simon Gog |
A Compressed Enhanced Suffix Array Supporting Fast String Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIRE ![In: String Processing and Information Retrieval, 16th International Symposium, SPIRE 2009, Saariselkä, Finland, August 25-27, 2009, Proceedings, pp. 51-62, 2009, Springer, 978-3-642-03783-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Hasan Saeed Mir |
A Generalized Transfer-Function Based Array Calibration Technique for Direction Finding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(2), pp. 851-855, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Keigo Hirakawa, Patrick J. Wolfe |
Spatio-Spectral Color Filter Array Design for Optimal Image Recovery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Image Process. ![In: IEEE Trans. Image Process. 17(10), pp. 1876-1890, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Supawat Supakwong, Athanassios Manikas, Anthony G. Constantinides |
Analysis of three-parameter diversely polarized array manifold. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PIMRC ![In: Proceedings of the IEEE 19th International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2008, 15-18 September 2008, Cannes, French Riviera, France, pp. 1-5, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Etan Fisher, Boaz Rafaely |
The nearfield spherical microphone array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 5272-5275, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Scott Miller, Mihai Sima, Michael McGuire |
VLSI implementation of a shift-enabled reconfigurable array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1360-1363, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Bahram Kouhi-Jelehkaran, Farbod Razzazi, Hamidreza Bakhshi |
Maximum-Likelihood Phone-Based Filter Parameter Optimization for Microphone Array Speech Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (1) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 1: Artificial Intelligence, December 12-14, 2008, Wuhan, China, pp. 842-845, 2008, IEEE Computer Society, 978-0-7695-3336-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | D. Dhanasekaran, K. Boopathy Bagan |
Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 77-83, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Virtual Reconfigurable circuit, element validation, Evolvable hardware |
21 | Sungbok Kim, Sanghyup Lee |
Optical Mouse Array Position Calibration for Mobile Robot Velocity Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAM ![In: 2008 IEEE Conference on Robotics, Automation and Mechatronics, RAM 2008, 21-24 September 2008, Chengdu, China, pp. 1167-1172, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Mika Takata, Yasuo Matsuyama |
Protein Folding Classification by Committee SVM Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (2) ![In: Advances in Neuro-Information Processing, 15th International Conference, ICONIP 2008, Auckland, New Zealand, November 25-28, 2008, Revised Selected Papers, Part II, pp. 369-377, 2008, Springer, 978-3-642-03039-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Sebastiaan van der Tol, Brian D. Jeffs, Alle-Jan van der Veen |
Self-Calibration for the LOFAR Radio Astronomical Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 55(9), pp. 4497-4510, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Hari Krishna Maganti, Daniel Gatica-Perez, Iain McCowan |
Speech Enhancement and Recognition in Meetings With an Audio-Visual Sensor Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Speech Audio Process. ![In: IEEE Trans. Speech Audio Process. 15(8), pp. 2257-2269, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Christophe Alias, Fabrice Baray, Alain Darte |
Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 73-82, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
program analysis, lattices, source-to-source transformations, memory reduction |
21 | Ezequiel Herruzo, Emilio L. Zapata, Oscar G. Plata |
Maximum and Sorted Cache Occupation Using Array Padding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007, pp. 178-185, 2007, IEEE, 1-4244-1058-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Milan Narandzic, Martin Käske, Christian Schneider 0003, Marko Milojevic, Markus H. Landmann, Gerd Sommerkorn, Reiner S. Thomä |
3D-Antenna Array Model for IST-WINNER Channel Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 319-323, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Mackale Joyner, Zoran Budimlic, Vivek Sarkar |
Optimizing Array Accesses in High Productivity Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: High Performance Computing and Communications, Third International Conference, HPCC 2007, Houston, USA, September 26-28, 2007, Proceedings, pp. 432-445, 2007, Springer, 978-3-540-75443-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Yongsheng Yin, Li Li 0003, Minglun Gao, Gaoming Du, Yu-Kun Song |
On the Implementation of Virtual Array Using Configuration Plane. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 7th International Symposium, APPT 2007, Guangzhou, China, November 22-23, 2007, Proceedings, pp. 199-208, 2007, Springer, 978-3-540-76836-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Clyde Clarke, Carl White, Ralph Etienne-Cummings |
Design and Optimization of a Capacitive Micromachined Ultrasonic Transducer Micro-Array for Near Field Sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 81-84, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu |
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 21-26, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Olgica Milenkovic, Navin Kashyap, David Leyba |
Shortened Array Codes of Large Girth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 52(8), pp. 3707-3722, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Kai Trojahner, Clemens Grelck, Sven-Bodo Scholz |
On Optimising Shape-Generic Array Programs Using Symbolic Structural Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFL ![In: Implementation and Application of Functional Languages, 18th International Symp osium, IFL 2006, Budapest, Hungary, September 4-6, 2006, Revised Selected Papers, pp. 1-18, 2006, Springer, 978-3-540-74129-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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