Search results for "full-adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis	A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Ali Abbasian, S. H. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani	No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi 0001	Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis.	ISMVL	2002	DBLP DOI BibTeX RDF	genetic algorithms, evolutionary computation, multiple-valued logic, arithmetic circuits
11	Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac, Alejandro Díaz-Sánchez	A new technique for noise-tolerant pipelined dynamic digital circuits.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
11	Turgay Temel, Avni Morgül	Multi-valued logic function implementation with novel current-mode logic gates.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
11	Seung Hoon Choi, Kaushik Roy 0001	Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Crosstalk, Inductance, Capacitance, Noise Analysis, Noise Margin, High Speed Circuit
11	Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy 0001	Dynamic Noise Analysis with Capacitive and Inductive Coupling.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	capacitiance, dynamic noise margin, crosstalk, inductance, noise analysis, deep submicron, noise model
11	Massimo Alioto, Gaetano Palumbo	Power estimation in adiabatic circuits: a simple and accurate model.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
11	Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy 0001	Design Verification and Robust Design Technique for Cross-Talk Faults.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
11	Eric Keller	Building Asynchronous Circuits with JBits.	FPL	2001	DBLP DOI BibTeX RDF
11	A. B. M. Harun-ur Rashid, Mazuhidul Karim, Syed Mahfuzul Aziz	Testing complementary pass-transistor logic circuits.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
11	Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul	Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic.	VLSI Design	2001	DBLP DOI BibTeX RDF
11	Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder	Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.	ISMVL	2000	DBLP DOI BibTeX RDF	signed-digit adder, negative differential-resistance devices, NDR devices, multiple-valued logic, resonant-tunneling diodes, redundant number systems, RTDs
11	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.	ISMVL	2000	DBLP DOI BibTeX RDF	dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder
11	Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama	Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic.	ISMVL	2000	DBLP DOI BibTeX RDF
11	Chih-Yuang Su, Shih-Am Hwang, Po-Song Chen, Cheng-Wen Wu	An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
11	Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds	High performance low power array multiplier using temporal tiling.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
11	Alexandre F. Tenca, Milos D. Ercegovac	On the Design of High-Radix On-Line Division for Long Precision.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
11	Amr M. Fahim, Mohamed I. Elmasry	A Low-Voltage High-Performance Differential Static Logic (LVDSL) family.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
11	Lei Wang 0003, Naresh R. Shanbhag	Noise-tolerant dynamic circuit design.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
11	Gianluca Cena, Paolo Montuschi, Luigi Ciminiera, Andrea Sanna	A Q-Coder Algorithm with Carry Free Addition.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	image compression, arithmetic coding
11	S. Ramanathan, V. Visvanathan	A systolic architecture for LMS adaptive filtering with minimal adaptation delay.	VLSI Design	1996	DBLP DOI BibTeX RDF	LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
11	Anastasios Vergis	On the multiple-fault testability of generalized counters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Shen-Chuan Tai, M. W. Du, Richard C. T. Lee	A transformational approach to synthesizing combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Graham A. Jullien, P. D. Bird, J. T. Carr, Majid Taheri, William C. Miller	An efficient bit-level systolic cell design for finite ring digital signal processing applications.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF
11	André Vandermeulebroecke, Etienne Vanzieleghem, Tony Denayer, Paul G. A. Jespers	A Single Chip 1024 Bits RSA Processor.	EUROCRYPT	1989	DBLP DOI BibTeX RDF
11	Bhabani P. Sinha, Pradip K. Srimani	A new parallel multiplication algorithm and its VLSI implementation.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF
11	Yasushi Ogawa, Hidekazu Terai, Tokinori Kozawa	Automatic Layout Procedures for Serial Routing Devices.	DAC	1988	DBLP BibTeX RDF