Search results for "repeater"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Tokuhiro Kitami, Haruo Yamaguchi, Takashi Hoshino 0001, Takeo Murata	An Experimental 800 Mbit/s Four-Level Repeater Compatible with the 60 MHz Analog System.	IEEE Trans. Commun.	1980	DBLP DOI BibTeX RDF
18	Humphrey W. Cheung, Victor J. Stalick, Jay A. Thomas	Key Aspects in the Development of a 48-Channel Duobinary PCM Repeater.	IEEE Trans. Commun.	1979	DBLP DOI BibTeX RDF
18	Brian Gibson	Equalization Design for a 600 MBd Quantized Feedback PCM Repeater.	IEEE Trans. Commun.	1979	DBLP DOI BibTeX RDF
18	Paul C. Davis, James F. Graczyk, William A. Griffin	Design of an Integrated Circuit for the T1C Low-Power Line Repeater.	IEEE Trans. Commun.	1979	DBLP DOI BibTeX RDF
18	Aaron Weinberg	The Effects of Repeater Hard-Limiting, Filter Distortion, and Noise on a Pseudo-Noise, Time-Of-Arrival Estimation System.	IEEE Trans. Commun.	1979	DBLP DOI BibTeX RDF
18	Frederick L. Riffle, Thomas E. Clark, San Chen, Carl G. Gilbert	A Monolithic Low Power PCM Repeater Circuit.	IEEE Trans. Commun.	1979	DBLP DOI BibTeX RDF
18	Yoshitaka Takasaki	Repeater Powering Plans for Fiber Optic Communication Systems.	IEEE Trans. Commun.	1978	DBLP DOI BibTeX RDF
18	Howard L. Weinberger	Satellite Repeater Capacity for Two Carrier Level SCPC Operation.	IEEE Trans. Commun.	1978	DBLP DOI BibTeX RDF
18	Masao Kawashima, Isao Fudemoto, Yukou Mochida, Takao Uyehara	400 Mbit/s Digital Repeater Circuitry Provided by a New Design Method and Beam Lead GHz Transistors.	IEEE Trans. Commun.	1977	DBLP DOI BibTeX RDF
18	Aaron Weinberg	Effects of a Hard Limiting Repeater on the Performance of a DPSK Data Transmission System.	IEEE Trans. Commun.	1977	DBLP DOI BibTeX RDF
18	Engel Roza, Peter W. Millenaar	An Experimental 560 Mbits/s Repeater with Integrated Circuits.	IEEE Trans. Commun.	1977	DBLP DOI BibTeX RDF
18	Gianfranco L. Cariolaro, Franco Todero	A General Spectral Analysis of Time Jitter Produced in a Regenerative Repeater.	IEEE Trans. Commun.	1977	DBLP DOI BibTeX RDF
18	Peter K. Runge	An Experimental 50 Mb/s Fiber Optic PCM Repeater.	IEEE Trans. Commun.	1976	DBLP DOI BibTeX RDF
18	Ikutaro Kobayashi, Yasuo Taki	On Optimal Analog Repeater Systems.	IEEE Trans. Commun.	1976	DBLP DOI BibTeX RDF
18	Terry Walzman	Relationship of Repeater Error Objective to System Error Objective.	IEEE Trans. Commun.	1976	DBLP DOI BibTeX RDF
18	Philip Balaban	Statistical evaluation of the error rate of the fiberguide repeater using importance sampling.	Bell Syst. Tech. J.	1976	DBLP DOI BibTeX RDF
18	Staffan A. Fredricsson	Optimum Receiver Filters in Digital Quadrature Phase-Shift-Keyed Systems with a Nonlinear Repeater.	IEEE Trans. Commun.	1975	DBLP DOI BibTeX RDF
18	Virgil I. Johannes, G. J. Stiles	Determining Repeater Margin with a Stub and Attenuator.	IEEE Trans. Commun.	1975	DBLP DOI BibTeX RDF
18	Robert G. Lyons	Combined Effects of Up- and Down-Link Fading Through a Power-Limiting Satellite Repeater.	IEEE Trans. Commun.	1974	DBLP DOI BibTeX RDF
18	Alan Stewart	A New Type of VF Repeater for Two-Wire Transmission Loops.	IEEE Trans. Commun.	1974	DBLP DOI BibTeX RDF
18	F. D. Waldhauer	Quantized Feedback in an Experimental 280-Mb/s Digital Repeater for Coaxial Transmission.	IEEE Trans. Commun.	1974	DBLP DOI BibTeX RDF
18	R. G. Buus, J. J. Kassig, Paul A. Yeisley	SF system: Repeater and equalizer design.	Bell Syst. Tech. J.	1970	DBLP DOI BibTeX RDF
18	H. T. Friis	Microwave repeater research.	Bell Syst. Tech. J.	1948	DBLP DOI BibTeX RDF
12	Marshnil Vipin Dave, Rajkumar Satkuri, Mahavir Jain, Maryam Shojaei Baghini, Dinesh Kumar Sharma	Low-power current-mode transceiver for on-chip bidirectional buses.	ISLPED	2010	DBLP DOI BibTeX RDF	current-mode signaling, driver pre-emphasis, interconnects
12	Hai Hu, Furong Wang, Fan Zhang, Weijia Jia 0001, Ge Tang	Automatic Mobile Vehicle for Adaptive Real-Time Communication Relay.	ICDCS Workshops	2009	DBLP DOI BibTeX RDF
12	Miriam J. Akl, Magdy A. Bayoumi	Transition Skew Coding for Global On-Chip Interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
12	Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross, Isaac L. Chuang, Frederic T. Chong	High-level interconnect model for the quantum logic array architecture.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	QLA, Quantum computer architecture design, teleportation, fault tolerance, large scale, quantum
12	Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi	Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect
12	Wenyi Zhang 0006, Urbashi Mitra	Channel-adaptive frequency-domain relay processing in multicarrier multihop transmission.	ICASSP	2008	DBLP DOI BibTeX RDF
12	J. M. Mouatcho Moualeu, Hongjun Xu 0001, Fambirai Takawira	Double Repeat-Punctured Turbo Coded Cooperative Diversity Scheme.	WCNC	2008	DBLP DOI BibTeX RDF
12	Ronald Raulefs, Armin Dammann	Repeating or Relaying in Wireless Systems.	WCNC	2008	DBLP DOI BibTeX RDF
12	Yulei Zhang 0002, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng	On-chip high performance signaling using passive compensation.	ICCD	2008	DBLP DOI BibTeX RDF
12	Yehea I. Ismail	Interconnect design and limitations in nanoscale technologies.	ISCAS	2008	DBLP DOI BibTeX RDF
12	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Optimization technique for flip-flop inserted global interconnect.	ISCAS	2008	DBLP DOI BibTeX RDF
12	David Dickin, Lesley Shannon	Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms.	ASAP	2008	DBLP DOI BibTeX RDF
12	Charbel J. Akl, Magdy A. Bayoumi	Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling.	VLSI Design	2008	DBLP DOI BibTeX RDF
12	Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano	Three-Dimensional Layout of On-Chip Tree-Based Networks.	ISPAN	2008	DBLP DOI BibTeX RDF	Fat H-Tree, Network-on-Chip, Fat Tree, 3-D IC
12	Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis	Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
12	Ja Chun Ku, Yehea I. Ismail	On the Scaling of Temperature-Dependent Effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
12	Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das	Hierarchical partitioning of VLSI floorplans by staircases.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	balanced bipartitioning, NP-completeness, Floorplanning, network flow, global routing
12	Michele Luglio, Fotini-Niovi Pavlidou, Cesare Roseti, Georgios Theodoridis	CAC-TCP Cross-Layer Interaction in a HAPS-Satellite Integrated Scenario.	VTC Spring	2007	DBLP DOI BibTeX RDF
12	Jakub Borkowski, Panu Lähdekorpi, Tero Isotalo, Jukka Lempiäinen	Optimization Aspects for Cellular Service Performance and Mobile Positioning in WCDMA Radio Networks.	VTC Spring	2007	DBLP DOI BibTeX RDF
12	Yasuo Tsuchimoto, Mohammad Abdul Awal, Poompat Saengudomlert, Teerapat Sanguankotchakorn, Kanchana Kanchanasut	Bandwidth Adjustable DVTS on the Heterogeneous Internet Environments for Distance Learning.	SAINT Workshops	2007	DBLP DOI BibTeX RDF
12	Byungsub Kim, Vladimir Stojanovic	Equalized interconnects for on-chip networks: modeling and optimization framework.	ICCAD	2007	DBLP DOI BibTeX RDF
12	Abinash Roy, Masud H. Chowdhury	Global Interconnect Optimization in the Presence of On-chip Inductance.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Jonathan Rosenfeld, Eby G. Friedman	Quasi-Resonant Interconnects: A Low Power Design Methodology.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	bit transitions, bus-encoding scheme, high impedance state, simultaneous switching noise (SSN), spatial and temporal redundancy, low power, delay, encoder, decoder, crosstalk noise, inductive coupling
12	Kenichi Shinkai, Masanori Hashimoto, Takao Onoye	Future Prediction of Self-Heating in Short Intra-Block Wires.	ISQED	2007	DBLP DOI BibTeX RDF
12	Michael N. Skoufis, Haibo Wang 0005, Themistoklis Haniotakis, Spyros Tragoudas	Glitch Control with Dynamic Receiver Threshold Adjustment.	ISQED	2007	DBLP DOI BibTeX RDF
12	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Delay-Balanced Smart Repeaters for On-Chip Global Signaling.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Tanya Deller, Rochelle Black, Francess Uzowulu, Vernell Mitchell, William Seffens	Internet APRS Data Utilization for Biosurveillance Applications.	BioSurveillance	2007	DBLP DOI BibTeX RDF
12	Guoqing Chen, Eby G. Friedman	Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny	Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann	Memory performance prediction for high-performance microprocessors at deep submicrometer technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
12	Alkan Cengiz, Tom W. Chen	Routing-Tree Construction with Concurrent Performance, Power and Congestion Optimization.	ISVLSI	2006	DBLP DOI BibTeX RDF
12	Yeonsu Kang, Do-Seob Ahn, Ho-Jin Lee	OFDM channel estimation with timing offset for satellite plus terrestrial multipath channels.	VTC Spring	2006	DBLP DOI BibTeX RDF
12	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	ISLPED	2006	DBLP DOI BibTeX RDF	intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
12	Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim	A low power SoC bus with low-leakage and low-swing technique.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Hyung Joon Jeon, Inn-yeal Oh	Algorithm and Structure to Cancel Signal Distortion in ATSC Digital TV System.	ICCSA (2)	2006	DBLP DOI BibTeX RDF
12	Alkan Cengiz, Tom W. Chen	A Progressive Two-Stage Global Routing for Macro-Cell Based Designs.	VLSI Design	2006	DBLP DOI BibTeX RDF
12	Daniel H. Ho, Shahrokh Valaee	Information Raining and Optimal Link-Layer Design for Mobile Hotspots.	IEEE Trans. Mob. Comput.	2005	DBLP DOI BibTeX RDF	mobile hotspots, graph theory, linear programming, wireless communication, medium access control, network protocols, constrained optimization, Emerging technologies, mobile environments, combinatorial algorithms, mobile communication systems, graphs and networks, network architecture and design
12	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for system-on-chip networks: a unified framework.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
12	Krishnan Sundaresan, Nihar R. Mahapatra	Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.	HPCA	2005	DBLP DOI BibTeX RDF
12	Seongmoo Heo, Krste Asanovic	Replacing global wires with an on-chip network: a power analysis.	ISLPED	2005	DBLP DOI BibTeX RDF	on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture
12	Guoqing Chen, Eby G. Friedman	Low power repeaters driving RLC interconnects with delay and bandwidth constraints.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
12	Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias	A distributed FIFO scheme for on chip communication.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
12	Ye Yan, Kwangsoo Kim, DongSun Park	A Flexible Mobile Communication Infrastructure Mechanism.	AICT/SAPIR/ELETE	2005	DBLP DOI BibTeX RDF
12	Zhai Mingyue, Liu Chunying, Bi Haiying	Study of Channel Characteristics of Power Line Communications Networks.	PDCAT	2005	DBLP DOI BibTeX RDF
12	Atul Maheshwari, Wayne P. Burleson	Differential current-sensing for on-chip interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
12	Mathilde Gay, Laurent Bramerie, G. Girault, Vincent Roncin, Jean-Claude Simon	Experimental Study of Reshaping Retiming Gates for 3R Regeneration.	OpNeTec	2004	DBLP DOI BibTeX RDF
12	André K. Nieuwland, Atul Katoch, Maurice Meijer	Reducing Cross-Talk Induced Power Consumption and Delay.	PATMOS	2004	DBLP DOI BibTeX RDF
12	V. Seth, Min Zhao 0001, Jiang Hu	Exploiting level sensitive latches in wire pipelining.	ICCAD	2004	DBLP DOI BibTeX RDF
12	Puneet Gupta 0001, Andrew B. Kahng	Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling.	VLSI Design	2004	DBLP DOI BibTeX RDF
12	Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III	Current-mode signaling in deep submicrometer global interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
12	Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer	Buffer delay change in the presence of power and ground noise.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
12	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	A Dynamically Tunable Memory Hierarchy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
12	Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham	Buffer insertion with adaptive blockage avoidance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
12	E. Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi	Power Comparison of Throughput Optimized IC Busses.	ISVLSI	2003	DBLP DOI BibTeX RDF
12	Ruibing Lu, Cheng-Kok Koh	Interconnect Planning with Local Area Constrained Retiming.	DATE	2003	DBLP DOI BibTeX RDF
12	Eli Chiprout	Early electrical wire projections and implications.	SLIP	2003	DBLP DOI BibTeX RDF
12	Nataraj Akkiraju, Mosur Mohan	Spec Based Flip-Flop And Buffer Insertion.	ICCD	2003	DBLP DOI BibTeX RDF
12	Rajesh Kumar 0006	Interconnect and noise immunity design for the Pentium 4 processor.	DAC	2003	DBLP DOI BibTeX RDF
12	Gregorio Cappuccino, Giuseppe Cocorullo	Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.	PATMOS	2002	DBLP DOI BibTeX RDF
12	Tao Lin, Lawrence T. Pileggi	Throughput-driven IC communication fabric synthesis.	ICCAD	2002	DBLP DOI BibTeX RDF
12	Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Optimising bandwidth over deep sub-micron interconnect.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
12	Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer	Coping with buffer delay change due to power and ground noise.	DAC	2002	DBLP DOI BibTeX RDF	common mode noise, differential mode noise, incremental delay change, power and ground noise
12	Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour	A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi	Energy efficient signaling in DSM CMOS technology.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
12	Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair	Performance Considerations in Embedded DSP based System-On-a-Chip Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
12	Kei Hirose, Hiroto Yasuura	A Bus Delay Reduction Technique Considering Crosstalk.	DATE	2000	DBLP DOI BibTeX RDF
12	Giovanni Chiola, Giuseppe Ciaccio	Fast Barrier Synchronization on Shared Fast Ethernet.	CANPC	1998	DBLP DOI BibTeX RDF
12	Hans J. Briegel, J. Ignacio Cirac, Wolfgang Dür, Steven J. van Enk, H. Jeff Kimble, Hideo Mabuchi, Peter Zoller 0001	Physical Implementations for Quantum Communication in Quantum Networks.	QCQC	1998	DBLP DOI BibTeX RDF
12	Janusz Rajski, Jerzy Tyszer	Modular logic built-in self-test for IP cores.	ITC	1998	DBLP DOI BibTeX RDF
12	David H. Albonesi	Dynamic IPC/Clock Rate Optimization.	ISCA	1998	DBLP DOI BibTeX RDF
12	D. Scott Alexander, Marianne Shaw, Scott Nettles, Jonathan M. Smith	Active Bridging.	SIGCOMM	1997	DBLP DOI BibTeX RDF
12	Daniel Audet, Yvon Savaria, N. Arel	Pipelining communications in large VLSI/ULSI systems.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
12	Biswanath Mukherjee	Performance of a Dual-Bus Unidirectional Broadcast Network Operating Under a Probabilistic Scheduling Strategy.	SIGMETRICS	1989	DBLP DOI BibTeX RDF