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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2021 occurrences of 633 keywords
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Results
Found 1539 publication records. Showing 1539 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Wei-Ting Liu, Ji-Jan Chen |
Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 10, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Joshua Ferry, Jozef Scesnak, Shoeib Shaikh |
A strategy for board level in-system programmable built-in assisted test and built-in self test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 10, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Gert Jervan |
Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2005 |
RDF |
|
14 | Jay J. Nejedlo |
IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 784, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | G. O. D. Acevedo, Jaime Ramírez-Angulo |
Built-in self-test scheme for on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 149-152, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni |
New test pattern generation units for NPSF oriented memory built-in self test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 749-752, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Gladys Omayra Ducoudray Acevedo, Jaime Ramírez-Angulo |
Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 2nd Latin American Test Workshop, LATW 2001, Cancun, Mexico, February 11-14, 2001., pp. 131-134, 2001, IEEE. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
14 | Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang |
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, pp. 93-96, 2001, ACM, 1-58113-351-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Vlado Vorisek |
Test Pattern Generators for Distributed and Embedded Built-in Self-Test at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 253-254, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth 0001, Michael R. Nelms, Jeffrey Leach, George M. Belansek |
Embedded DRAM built in self test and methodology for test insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 975-984, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | A. Chrisanthopoulos, George Kamoulakos, Y. Tsiatouhas, Angela Arapoyanni |
A test pattern generation unit for memory NPSF built-in self test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2000 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, December 17-20, 2000, pp. 425-428, 2000, IEEE, 0-7803-6542-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Ulf Pillkahn |
Structural test in a board self test environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000, pp. 1005-1012, 2000, IEEE Computer Society, 0-7803-6546-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Ramesh Karri |
Built in self test: a complete test solution for telecommunication systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Commun. Mag. ![In: IEEE Commun. Mag. 37(6), pp. 72-78, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Dhiraj K. Pradhan, Mitrajit Chatterjee |
GLFSR-a new test pattern generator for built-in-self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2), pp. 238-247, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe |
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996, pp. 319-324, 1996, IEEE Computer Society, 0-7803-3541-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
14 | Albrecht P. Stroele |
A Self-Test Approach Using Accumulators as Test Pattern Generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 2120-2123, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
14 | Dhiraj K. Pradhan, Mitrajit Chatterjee |
GLFSR - A New Test Pattern Generator for Built-In Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1994, TEST: The Next 25 Years, Washington, DC, USA, October 2-6, 1994, pp. 481-490, 1994, IEEE Computer Society, 0-7803-2103-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
14 | Arno Kunzmann |
FPL Based Self-Test with Deterministic Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31 - September 2, 1992, Selected Papers, pp. 174-182, 1992, Springer, 3-540-57091-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
14 | Chien-In Henry Chen, Joel T. Yuen |
Concurrent Test Scheduling in Built-In Self-Test Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 256-259, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
14 | Albrecht P. Stroele |
Self-Test Scheduling with Bounded Test Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 130-139, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
14 | Prawat Nagvajara, Mark G. Karpovsky, Lev B. Levitin |
Efficient test generation for built-in self-test boundary-scan template. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 9th IEEE VLSI Test Symposium (VTS'91), 15-17 Apr 1991, Atlantic City, NJ, USA, pp. 277-284, 1991, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
14 | Yasuyuki Nozuyama |
Realization of an efficient design verification test used on a microinstruction controlled self test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990, pp. 327-336, 1990, IEEE Computer Society, 0-8186-9064-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
14 | Sheldon B. Akers, Winston Jansz |
Test Set Embedding in a Built-In Self-Test Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1989, Washington, D.C., USA, August 1989, pp. 257-263, 1989, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
14 | A. C. Erdal, Pierre A. Uszynski |
A global chip test implementation including built-in self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 446-449, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
14 | Fardad Siavoshi |
WTPGA : A Novel Weighted Test Pattern Generation Approach for VLSI Built-In Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988, pp. 256-262, 1988, IEEE Computer Society, 0-8186-0870-6. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
14 | Andrzej Hlawiczka, Dariusz Badura |
Universal Test Controller Chip for Board Self Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fehlertolerierende Rechensysteme ![In: Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, 3. Internationale GI/ITG/GMA-Fachtagung, Bremerhaven, Deutschland, 9.-11. September 1987, Proceedings, pp. 165-175, 1987, Springer, 3-540-18294-2. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
14 | Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo Chacón, Diego Gomez Vela |
FPGA-Based Boundary-Scan Bist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | R. P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg |
Designing and Implementing an Architecture with Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 7(1), pp. 9-19, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
14 | Daniel Mange, André Stauffer, Gianluca Tempesti |
Embryonics: A Microscopic View of the Molecular Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, Second International Conference, ICES 98, Lausanne, Switzerland, September 23-25, 1998, Proceedings, pp. 185-195, 1998, Springer, 3-540-64954-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | A. Tchegho, Heinz Mattes, Sebastian Sattler |
Optimal High-Resolution Spectral Analyzer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 62-67, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Daniela De Venuto, Leonardo Reyneri |
PWM-Based Test Stimuli Generation for BIST of High Resolution ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 284-287, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Daniela De Venuto, Leonardo Reyneri |
Fast PWM-Based Test for High Resolution SigmaDelta ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(6), pp. 539-548, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Test of high resolution ADC, Sigma-Delta ADC, PWM test signal |
13 | Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng |
A framework for system reliability analysis considering both system error tolerance and component test quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1581-1586, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Daniela De Venuto, Leonardo Reyneri |
Fully Digital Optimized Testing and Calibration Technique for Sigma Delta ADC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 519-526, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Built-in sequential fault self-testing of array multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3), pp. 449-460, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu |
On Test and Diagnostics of Flash Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 260-265, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Christoph Hoffmann |
A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 197-204, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya |
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 303-309, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
13 | Rajiv Gupta 0002, Rajagopalan Srinivasan, Melvin A. Breuer |
Reorganizing Circuits to Aid Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 8(3), pp. 49-57, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
13 | Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal |
Serial Interfacing for Embedded-Memory Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 7(2), pp. 52-63, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
13 | Uthman Alsaiari, Resve A. Saleh |
Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 798-803, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Partitioning, Redundancy, Yield, Flip-Flop |
13 | Peter Leijdekkers, Valérie Gay |
A Self-Test to Detect a Heart Attack Using a Mobile Phone and Wearable Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CBMS ![In: Proceedings of the Twenty-First IEEE International Symposium on Computer-Based Medical Systems, June 17-19, 2008, Jyväskylä, Finland, pp. 93-98, 2008, IEEE Computer Society, 978-0-7695-3165-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
heart attack selft-test, mobile health monitoring, mobile health application, wearable sensors |
13 | H. J. Kadim |
Analytical Modelling of Power Attenuation under Parameter Fluctuations with Applications to Self-Test and Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 309-312, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Shibaji Banerjee, Dipanwita Roy Chowdhury |
Built-In Self-Test for Flash Memory Embedded in SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 379-384, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Abdil Rashid Mohamed, Zebo Peng, Petru Eles |
A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(2), pp. 216-223, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
BIST insertion, wiring area, simulated annealing, test synthesis |
13 | Mimi Yiu, Chris Winstead, Vincent C. Gaudet, Christian Schlegel |
Digital built-in self-test of CMOS analog iterative decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2204-2207, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | João Goes, Nuno Paulino 0002, Guiomar Evans |
On-chip built-in self-test of video-rate ADCs using Gaussian noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 796-799, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Ismet Bayraktaroglu, Olivier Caty, Yickkei Wong |
Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 21-26, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Sunil Rafeeque, Vinita Vasudevan |
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(6), pp. 623-638, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
digital to analog converters, nonlinearity test, analog testing, mixed-signal BIST |
13 | Shyue-Kung Lu, Shih-Chang Huang |
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 60-64, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Nilmoni Deb, R. D. (Shawn) Blanton |
Multi-Modal Built-In Self-Test for Symmetric Microsystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 139-147, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone |
A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 148-153, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Abdil Rashid Mohamed, Zebo Peng, Petru Eles |
A Wiring-Aware Approach to Minimizing Built-in Self-Test Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 413-415, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Sunil Rafeeque, Vinita Vasudevan |
A Built-in-Self-Test Scheme for Digital to Analog Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 1027-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Sanghoon Choi, William R. Eisenstadt, Robert M. Fox |
Design of programmable embedded IF source for design self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 241-244, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Louis Y. Ungar, Tony Ambler |
Economics of Built-in Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 18(5), pp. 70-79, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | A. Hodge, Robert Newcomb 0001, A. Hefner |
Use of the oscillation based built-in self-test method for smart sensor devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 281-284, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi |
DC Built-In Self-Test for Linear Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 13(2), pp. 26-33, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
13 | Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja |
A Tutorial on Built-In Self-Test, Part 2: Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(2), pp. 69-77, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
12 | Hayoung Lee, Jihye Kim, Jongho Park, Sungho Kang 0001 |
STRAIT: Self-Test and Self-Recovery for AI Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9), pp. 3092-3104, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Yu-Chih Tsai, Wen-Chien Ting, Chia-Chun Wang, Chia-Cheng Chang, Ren-Shuo Liu |
Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, pp. 1-6, 2023, IEEE, 978-3-9819263-7-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Zhiyuan Sun, Miao Wang |
Self-Test and Self-Calibration of Digital Closed-Loop Accelerometers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(24), pp. 9933, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | |
A saboteur and mutant based built-in self-test and counting threshold-based built-in self repairing mechanism for memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Ambient Intell. Humaniz. Comput. ![In: J. Ambient Intell. Humaniz. Comput. 12(6), pp. 6651-6663, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
12 | Yanqiang Yang, Jian Liang, Longjie Tian, Tongyao Yue, Hao Zhang 0039 |
Dead Band Self-Test Method of Three-Self FOG INS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 70, pp. 1-7, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
12 | Debatrayee Roychowdhury, Soroush Moallemi, Sule Ozev, Jennifer Kitchen |
Self-Interference Signal Path Characterization in Full-Duplex Transceivers Using Built-in Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RWS ![In: 2020 IEEE Radio and Wireless Symposium, RWS 2020, San Antonio, TX, USA, January 26-29, 2020, pp. 16-19, 2020, IEEE, 978-1-7281-1120-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
12 | Shahriar Shahramian, Michael J. Holyoak, Amit Singh, Yves Baeyens |
A Fully Integrated 384-Element, 16-Tile, $W$ -Band Phased Array With Self-Alignment and Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(9), pp. 2419-2434, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
12 | Tao Chen 0006, Degang Chen 0001 |
Built-in self-test and self-calibration for analog and mixed signal circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2019, Washington, DC, USA, November 9-15, 2019, pp. 1-8, 2019, IEEE, 978-1-7281-4823-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
12 | Scott Davidson 0001 |
Self-Test and Self-Aware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 35(5), pp. 80, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Michael A. Kochte, Hans-Joachim Wunderlich |
Self-Test and Diagnosis for Self-Aware Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 35(5), pp. 7-18, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Shahriar Shahramian, Mike Holyoak, Amit Singh, Bahar Jalali Farahani, Yves Baeyens |
A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 74-76, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Mario Schölzel, Tobias Koal, Sebastian Müller 0005, Stefan Scharoba, Stephanie Roder, Heinrich Theodor Vierhaus |
A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 17th Latin-American Test Symposium, LATS 2016, Foz do Iguacu, Brazil, April 6-8, 2016, pp. 33-38, 2016, IEEE, 978-1-5090-1331-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
12 | Myat Thu Linn Aung, Tony T. Kim |
Self-contained built-in-self-test/repair transceivers for interconnects in 3DICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016, pp. 640-641, 2016, IEEE, 978-1-5090-1570-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
12 | Afsaneh Nassery, Srinath Byregowda, Sule Ozev, Marian Verhelst, Mustapha Slamani |
Built-In Self-Test of Transmitter I/Q Mismatch and Nonlinearity Using Self-Mixing Envelope Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(2), pp. 331-341, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Palanichamy Manikandan, Mohammad Areef, Bjørn B. Larsen, Vladimir Hahanov |
Selective Algorithms for Built-In Self-Test and Self-Diagnosis in Embedded SRAMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 11(4), pp. 541-551, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Jae Woong Jeong, Jennifer Kitchen, Sule Ozev |
A self-compensating built-in self-test solution for RF phased array mismatch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2015 IEEE International Test Conference, ITC 2015, Anaheim, CA, USA, October 6-8, 2015, pp. 1-9, 2015, IEEE, 978-1-4673-6578-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Sleiman Bou-Sleiman, Mohammed Ismail 0001 |
Built-in-Self-Test and Digital Self-Calibration for RF SoCs ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2012 |
DOI RDF |
|
12 | Mouna Karmani, Chiraz Khedhiri, Ka Lok Man, Tomas Krilavicius, Belgacem Hamdi, Amir-Mohammad Rahmani |
A self-test and self-repair approach for analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BCFIC ![In: 2nd Baltic Congress on Future Internet Communications, BCFIC 2012, Vilnius, Lithuania, April 25-27, 2012, pp. 117-120, 2012, IEEE, 978-1-4673-1672-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
12 | Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee, Duane C. Howard, John D. Cressler |
A self-testable SiGe LNA and Built-in-Self-Test methodology for multiple performance specifications of RF amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012, pp. 7-12, 2012, IEEE, 978-1-4673-1034-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
12 | Afsaneh Nassery, Srinath Byregowda, Sule Ozev, Marian Verhelst, Mustapha Slamani |
Built-in-Self Test of transmitter I/Q mismatch using self-mixing envelope detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 56-61, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
12 | André Stauffer, Joël Rossier |
Bio-inspired bit slice processors with self-test and self-repair mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: 2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010, Anaheim, California, USA, June 15-18, 2010, pp. 44-51, 2010, IEEE Computer Society, 978-1-4244-5887-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
12 | Shu-Yen Lin, Chan-Cheng Hsu, An-Yeu Wu |
A Scalable Built-in Self-test/Self-diagnosis Architecture for 2D-Mesh based Chip Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 2317-2320, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Voicu Groza, Rami S. Abielmona, Mansour H. Assaf, Mohammed Elbadri, Mohammad El-Kadri, Arkan Khalaf |
A Self-Reconfigurable Platform for Built-In Self-Test Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 56(4), pp. 1307-1315, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Daryl W. Bradley, Andrew M. Tyrrell |
Immunotronics - novel finite-state-machine architectures with built-in self-test using self-nonself differentiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 6(3), pp. 227-238, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Janet A. Taylor |
Self Test: a flexible self assessment package for distance and other learners. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Educ. ![In: Comput. Educ. 31(3), pp. 319-328, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
12 | William S. Blackley, Mervyn A. Jack, James R. Jordan |
A Digital Polarity Correlator with Built-in Self Test and Self Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 1(2), pp. 42-49, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
12 | William S. Blackley, Mervyn A. Jack, James R. Jordan |
A Digital Polarity Correlator Featuring Built-In Self Test and Self Repair Mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1983, Philadelphia, PA, USA, October 1983, pp. 289-294, 1983, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
12 | Dong Xiang, Yang Zhao 0001, Krishnendu Chakrabarty, Hideo Fujiwara |
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6), pp. 999-1012, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Sunghoon Chun, Taejin Kim, Sungho Kang |
A new low energy BIST using a statistical code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 647-652, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Masood ul-Hasan, Yichuang Sun, Xi Zhu 0001, James Moritz |
Oscillation-based DFT for second-order OTA-C filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 720-723, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Adam B. Kinsman, Nicola Nicolici |
Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 832-837, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
design-for-testability, test data compression |
12 | Seongmoon Wang |
A BIST TPG for Low Power Dissipation and High Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(7), pp. 777-789, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 |
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2934-2943, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus |
Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 433-438, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Dhiraj K. Pradhan, Chunsheng Liu |
EBIST: a novel test generator with built-in fault detection capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1457-1466, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos |
Multiphase BIST: a new reseeding technique for high test-data compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10), pp. 1429-1446, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Jerzy J. Dabrowski, Javier Gonzalez Bayon |
Mixed Loopback BiST for RF Digital Transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 220-228, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius 0001, Rosa Rodríguez-Montañés, Joan Figueras |
BIST Technique by Equally Spaced Test Vector Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 206-216, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski |
Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 893-902, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Hailong Cui, Sharad C. Seth, Shashank K. Mehta |
Modeling Fault Coverage of Random Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 271-284, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fault-coverage prediction, cost-benefit analysis of fault simulation, variance of fault coverage, BIST, probabilistic model |
12 | Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi, Farzin Karimi |
Hybrid Multisite Testing at Manufacturing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 927-936, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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