Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Mile K. Stojcev |
Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 45(7-8), pp. 1272, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Tun Li, Yang Guo 0003, GongJie Liu, Sikun Li |
Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 17-25, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Peter Jamieson, Jonathan Rose |
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 305-310, 2005, IEEE, 0-7803-9362-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao 0001, Hamid R. Arabnia |
Verilog Coding Style for Efficient Synthesis In FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005, pp. 85-90, 2005, CSREA Press, 1-932415-54-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
18 | S. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski |
Behavioral test benches for digital clock and data recovery circuits using Verilog-A. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005, pp. 297-300, 2005, IEEE, 0-7803-9023-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Arash Saifhashemi, Peter A. Beerel |
High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CPA ![In: The 28th Communicating Process Architectures Conference, CPA 2005, organised under the auspices of WoTUG, Philips and the Technische Universiteit Eindhoven, Eindhoven, The Netherlands, 18-21 September 2005, pp. 275-288, 2005, IOS Press, 978-1-58603-561-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
18 | Janick Bergeron |
Modeling Usable and Reusable Transactors in System Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 36-, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Romeo Urbieta Parrazales, Enrique Guzmán-Ramírez |
Diseño de Control Difuso Usando Promedio de Pesos e Implementado con Lenguaje Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Polibits ![In: Polibits 30, pp. 23-27, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Yuan-Bin Sha, Mu-Shun Matt Lee, Chien-Nan Jimmy Liu |
On code coverage measurement for Verilog-A. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Ninth IEEE International High-Level Design Validation and Test Workshop 2004, Sonoma Valley, CA, USA, November 10-12, 2004, pp. 115-120, 2004, IEEE Computer Society, 0-7803-8714-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Meinrad Fiedler |
Ein Ubersetzungsverfahren von Verilog-Kausalspezifikationen in Signalflankengraph-basierte Spezifikationen zum Entwurf asynchroner Schaltwerke. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004, pp. 194-203, 2004, Shaker. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
18 | Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu |
A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 293-296, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
18 | Lubomir Ivanov |
Automatic Extraction of Non-Iterated System Behavior from Verilog Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA/VLSI ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA, pp. 399-406, 2004, CSREA Press, 1-932415-41-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
18 | Naohiko Shimizu |
Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12), pp. 3225-3229, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
18 | Jay Lawrence |
Orthogonality of Verilog Data Types and Object Kinds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(5), pp. 94-96, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
18 | Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada |
Comparative Study On Verilog-Based And C-Based Hardware Design Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 41-42, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Junjun Li, Sopan Joshi, Elyse Rosenbaum |
A Verilog-A compact model for ESD protection NMOSTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 253-256, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi |
Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Embedded Systems and Applications ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '03, June 23 - 26, 2003, Las Vegas, Nevada, USA, pp. 139-143, 2003, CSREA Press. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
18 | Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai |
A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2), pp. 395-398, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
18 | |
Verilog and Other Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(1), pp. 84-85, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
18 | Jordan Dimitriov |
Developing semantics of Verilog HDL in formal compositional design of mixed hardware/software systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2002 |
RDF |
|
18 | Daryl Stewart |
A uniform semantics for verilog and VHDL suitable for both simulation and verification ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2002 |
RDF |
|
18 | Lionel Bening, Harry Foster |
Principles of verifiable RTL design - a functional coding style supporting verification processes in Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2001 |
RDF |
|
18 | Jifeng He 0001, Huibiao Zhu |
Formalising VERILOG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2000 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, December 17-20, 2000, pp. 412-415, 2000, IEEE, 0-7803-6542-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Erik Lauwers, Georges G. E. Gielen, Koen Lampaert, Paolo Miliozzi |
High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMAS ![In: 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, BMAS 2000, Orlando, Florida, USA, 18-20 October 2000, pp. 16-21, 2000, IEEE Computer Society, 0-7695-0893-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Peter Frey, Donald O'Riordan |
Verilog-AMS: Mixed-Signal Simulation and Cross Domain Connect Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMAS ![In: 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, BMAS 2000, Orlando, Florida, USA, 18-20 October 2000, pp. 103-108, 2000, IEEE Computer Society, 0-7695-0893-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Zainalabedin Navabi |
Hardware Description in Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
The VLSI Handbook ![In: The VLSI Handbook., 1999, CRC Press, 978-0-8493-8593-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | John Howard Eli Fiskio-Lasseter, Amr Sabry |
Putting Operational Techniques to the Test: A Syntactic Theory for Behavioral Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOOTS ![In: Third Workshop on Higher-Order Operational Techniques in Semantics, HOOTS 1999, Paris, France, September 30 - October 1, 1999, pp. 34-51, 1999, Elsevier. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Françoise Martinolle, Charles Dawson 0002, Debra Corlette, Mike Floyd |
Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 788-789, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Hisashi Sasaki |
A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 353-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 326-332, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Peter Wohl, John A. Waicukauski |
Using Verilog simulation libraries for ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999, pp. 1011-1020, 1999, IEEE Computer Society, 0-7803-5753-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Daniel C. Hyde |
Using verilog HDL to teach computer architecture concepts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@ISCA ![In: Proceedings of the 1998 workshop on Computer architecture education, WCAE@ISCA 1998, Barcelona, Spain, June 1998, pp. 10, 1998, ACM, 978-1-4503-4736-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Gordon G. Pace |
Hardware design based on Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1998 |
RDF |
|
18 | James M. Lee |
Verilog quickstart. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1997 |
RDF |
|
18 | Dominique Borrione, F. Vestman, H. Bouamama |
An approach to Verilog-VHDL interoperability for synchronous designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Advances in Hardware Design and Verification, IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods, 16-18 October 1997, Montréal, Québec, Canada, pp. 65-87, 1997, Chapman & Hall, 0-412-81330-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP BibTeX RDF |
|
18 | Ulrich Golze |
VLSI chip design with the hardware description language VERILOG - an introduction based on a large RISC processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1996 |
RDF |
|
18 | Donald E. Thomas, Philip Moorby |
The Verilog hardware description language (3. ed.). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1996 |
RDF |
|
18 | Ulrich Golze |
VLSI-Entwurf eines RISC-Prozessors - eine Einführung in das Design großer Chips und die Hardware-Beschreibungssprache VERILOG HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1995 |
RDF |
|
18 | Donald E. Thomas, Philip Moorby |
The Verilog hardware description language (2. ed.). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1995 |
RDF |
|
18 | Michael J. C. Gordon |
The Semantic Challenge of Verilog HDL ![Search on Bibsonomy](Pics/bibsonomy.png) |
LICS ![In: Proceedings, 10th Annual IEEE Symposium on Logic in Computer Science, San Diego, California, USA, June 26-29, 1995, pp. 136-145, 1995, IEEE Computer Society, 0-8186-7050-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | David J. Greaves |
The CSYN Verilog Compiler and Other Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 5th International Workshop, FPL '95, Oxford, UK, August 29 - September 1, 1995, Proceedings, pp. 198-207, 1995, Springer, 3-540-60294-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Raymond P. Voith |
The PowerPC 603 C++ Verilog Interface Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPCON ![In: Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28 - March 4, 1994, pp. 337-340, 1994, IEEE Computer Society, 0-8186-5380-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Felice Balarin, Gary York |
Verilog HDL Modeling Styles for Formal Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHDL ![In: Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993, pp. 453-465, 1993, North-Holland, 0-444-81641-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
18 | Serge Maginot |
Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I & M. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992, pp. 746-751, 1992, IEEE Computer Society Press, 0-8186-2780-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
10 | Marc Schlickling, Markus Pister 0002 |
Semi-automatic derivation of timing models for WCET analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, LCTES 2010, Stockholm, Sweden, April 13-15, 2010, pp. 67-76, 2010, ACM, 978-1-60558-953-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
vhdl, worst-case execution time, hard real-time |
10 | Shiuh-Jer Huang, Shian-Shin Wu |
Vision-Based Robotic Motion Control for Non-autonomous Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 54(5), pp. 733-754, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Self-organizing fuzzy control, FPGA chip, Visual servo, Robotic system |
10 | Miloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko |
Experience in Virtual Testing of RSD cyclic A/D converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 178-181, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Warren A. Hunt Jr., Sol Swords |
Centaur Technology Media Unit Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 353-367, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner |
Fpga-based face detection system using Haar classifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 103-112, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost |
10 | Jinsil Kim, Wonyoung Chung, Junghee Lee, Yongsurk Lee |
An implementation of the CQS supporting multimedia traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHIT ![In: Proceedings of the 2009 International Conference on Hybrid Information Technology, ICHIT 2009, Daejeon, Korea, August 27-29, 2009, pp. 163-170, 2009, ACM, 978-1-60558-662-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CQS, dequeue, enqueue, scheduler |
10 | Rishiyur S. Nikhil |
Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design). ![Search on Bibsonomy](Pics/bibsonomy.png) |
GPCE ![In: Generative Programming and Component Engineering, 8th International Conference, GPCE 2009, Denver, Colorado, USA, October 4-5, 2009, Proceedings, pp. 1-2, 2009, ACM, 978-1-60558-494-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing |
10 | Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik |
Supporting RTL flow compatibility in a microarchitecture-level design framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 343-352, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
microarchitecture level, transactions, formal models, hierarchical design, hardware resources |
10 | Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro |
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 181-192, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED |
10 | Jamie Cullen |
Evolutionary meta programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GEC Summit ![In: Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation, GEC Summit 2009, Shanghai, China, June 12-14, 2009, pp. 81-88, 2009, ACM, 978-1-60558-326-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
evolutionary meta compilation, evolutionary meta programming, genetic programming, evolutionary computation, grammatical evolution |
10 | Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David T. Blaauw |
Low power circuit design based on heterojunction tunneling transistors (HETTs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 219-224, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SRAM design, low power applications, tunneling transistor |
10 | Syed Zafar Shazli, Mehdi Baradaran Tahoori |
Soft error rate computation in early design stages using boolean satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 101-104, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
soft error, hardware description language, reliability modeling |
10 | Adithya V. Kodati, Koneswara S. Vemuri, Lili He 0001, Morris Jones |
Implementation of power managed hyper transport system for transmission of HD video. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 517-521, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Jesse D. Bingham, John Erickson, Gaurav Singh, Flemming Andersen |
Industrial strength refinement checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 180-183, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Zurab Khasidashvili, Gavriel Gavrielov, Tom Melham |
Assume-guarantee validation for STE properties within an SVA environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 108-115, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham |
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 77-82, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Hong Lu, A. Forin |
Automatic Processor Customization for Zero-Overhead Online Software Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(10), pp. 1346-1357, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Hiren D. Patel, Sandeep K. Shukla |
On Cosimulating Multiple Abstraction-Level System-Level Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 394-398, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Reza M. Rad, Mohammad Tehranipoor |
SCT: A novel approach for testing and configuring nanoscale devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(3), pp. 14:1-14:24, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Configuration and testing, reconfigurable nanoscale devices, fault tolerance, crossbar, nanowire |
10 | Chun-Lung Hsu, Yu-Sheng Huang |
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 211-229, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter |
10 | Grant Martin |
Learning to assert yourself [review of Creating Assertion-Based IP (H.D. Foster and A.C. Krolnik; 2008)]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(3), pp. 284-285, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Santiago De Pablo, Santiago Cáceres, Jesús A. Cebrián, Manuel Berrocal, F. Sanz |
ASM++ diagrams used on teaching electronic design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education ![In: Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education, Proceedings of the 2007 International Conference on Engineering Education, Instructional Technology, Assessment, and E-learning (EIAE 2007), part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 2007), Bridgeport, CT, USA, December 3-12, 2007, pp. 473-478, 2008, Springer, 978-1-4020-8738-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina |
xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pp. 141-148, 2008, IEEE Computer Society, 978-0-7695-3089-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques |
10 | Jamie Cullen |
Evolving Digital Circuits in an Industry Standard Hardware Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEAL ![In: Simulated Evolution and Learning, 7th International Conference, SEAL 2008, Melbourne, Australia, December 7-10, 2008. Proceedings, pp. 514-523, 2008, Springer, 978-3-540-89693-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew D. Brown |
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 152-157, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi |
Fault Effects in FlexRay-Based Networks with Hybrid Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Third International Conference on Availability, Reliability and Security, ARES 2008, March 4-7, 2008, Technical University of Catalonia, Barcelona , Spain, pp. 491-496, 2008, IEEE Computer Society, 978-0-7695-3102-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FlexRay Protocol, Fault Injection, Error Propagation, Distributed Embedded Systems, Dependability Evaluation |
10 | Ansuman Banerjee, Kausik Datta, Pallab Dasgupta |
CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis, 6th International Symposium, ATVA 2008, Seoul, Korea, October 20-23, 2008. Proceedings, pp. 228-233, 2008, Springer, 978-3-540-88386-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes |
BenCGen: a digital circuit generation tool for benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 164-169, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
benchmarks, sat solvers, combinational equivalence checking |
10 | Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Lei Zhang 0014, Yulu Yang, Enyue Lu, Xiao-chun Yun |
Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 259-264, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
PRDT, router, NoC |
10 | Naoki Iwasaki, Katsumi Wasaki |
A Meta Hardware Description Language Melasy for Model-Checking Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 273-278, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hardware/Software co-design and co-verification, Model Checking, Haskell, Design-for-test, Hardware Compilers |
10 | Ruchika Verma, Ali Akoglu |
A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Jamie Cullen |
Evolutionary Meta Compilation: Evolving Programs Using Real World Engineering Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, pp. 414-419, 2008, Springer, 978-3-540-85856-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | David J. Greaves, Satnam Singh |
Kiwi: Synthesis of FPGA Circuits from Parallel Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 3-12, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Satnam Singh, David J. Greaves |
Synthesizing FPGA Circuits from Parallel Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, pp. 1, 2008, Springer, 978-3-540-78609-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Wolfram Büttner |
Complex Hardware Modules Can Now be Made Free of Functional Errors without Sacrificing Productivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ABZ ![In: Abstract State Machines, B and Z, First International Conference, ABZ 2008, London, UK, September 16-18, 2008. Proceedings, pp. 1-3, 2008, Springer, 978-3-540-87602-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Formal Verification, Design Process, Abstract State Machine |
10 | Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi |
An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Public Key Cryptography ![In: Public Key Cryptography - PKC 2008, 11th International Workshop on Practice and Theory in Public-Key Cryptography, Barcelona, Spain, March 9-12, 2008. Proceedings, pp. 214-228, 2008, Springer, 978-3-540-78439-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication |
10 | Michal Karczmarek, Arvind |
Synthesis from multi-cycle atomic actions as a solution to the timing closure problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 24-31, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King Liu, Vladimir Stojanovic, Elad Alon |
Integrated circuit design with NEM relays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 750-757, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee |
De-synchronization of a point-of-sales digital-logic controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3402-3405, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Balaji V. Iyer, Thomas M. Conte |
A Power Model for Register-Sharing Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DIPES ![In: Distributed Embedded Systems: Design, Middleware and Resources, IFIP 20th World Computer Congress, TC10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2008), September 7-10, 2008, Milano, Italy, pp. 131-142, 2008, Springer, 978-0-387-09660-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito |
A Tiny Processing System for Education and Small Embedded Systems on the FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC (2) ![In: 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 17-20, 2008, Volume II: Workshops, pp. 472-479, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Drew C. Ness, David J. Lilja |
Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 297-302, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
fault distribution, reliability analysis, SEU, SER |
10 | Nathaniel J. August |
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 423-428, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
pre-silicon, validation, mixed-signal |
10 | Jalaj Jain |
A Scalable and Reconfigurable Coprocessor for Image Composition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 97-102, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Yogesh Singh Chauhan, Dimitrios Tsamados, Nicolas Abelé, Christoph Eggimann, Michel J. Declercq, Adrian M. Ionescu |
Compact Modeling of Suspended Gate FET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 119-124, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Shahid Rizwan |
Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 53-58, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Kyller Costa Gorgônio, Jordi Cortadella |
Hardware Synthesis for Asynchronous Communications Mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCCC ![In: XXVII International Conference of the Chilean Computer Science Society (SCCC 2008), 10-14 November 2008, Punta Arenas, Chile, pp. 135-143, 2008, IEEE Computer Society, 978-0-7695-3403-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang 0009, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips |
A MIPS R2000 implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 102-107, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
RISC, MIPS |
10 | Xiang Xiao, Jaehwan John Lee |
A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 6(2), pp. 41-44, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Chen Shoushun, Amine Bermak |
Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 346-357, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee |
An Overview of a Compiler for Mapping Software Binaries to Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1177-1190, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Edmund M. Clarke, Himanshu Jain, Daniel Kroening |
Verification of SpecC using predicate abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 30(1), pp. 5-28, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Verification, System level design, Predicate abstraction |
10 | Aggelos Ioannou, Manolis Katevenis |
Pipelined heap (priority queue) management for advanced scheduling in high-speed networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 15(2), pp. 450-461, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high-speed network scheduling, pipelined hard-ware heap, synthesizable core, weighted fair queueing, priority queue, weighted round robin |
10 | Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham |
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(10), pp. 1401-1414, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Register Transfer Level implementation, Verification, Hardware Description Languages, arithmetic logic unit |
10 | Felice Balarin, Roberto Passerone |
Specification, Synthesis, and Simulation of Transactor Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1749-1762, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Maria Stepanova, Feng Lin 0002, Valerie C.-L. Lin |
A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 48(3), pp. 239-254, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DNA motifs, sequence structure identification, hopfield classifier, field-programmable gate arrays, recurrent neural network |