Search results for "SoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Axel G. Braun, Djones Lettnin, Joachim Gerlach, Wolfgang Rosenstiel	Automated Conversion of SystemC Fixed-Point Data Types.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Antonio Carlos Schneider Beck, Luigi Carro	Low Power Java Processor for Embedded Applications.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Giuseppe Bonfini, Andrea S. Brogna, Roberto Saletti, Cristian Garbossa, Luca Colombini, Maurizio Bacci, Stefania Chicca, Franco Bigongiari	A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Cristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis 0001	A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel	Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Jürgen Becker 0001, Michael Hübner 0001, Michael Ullmann	Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	José Augusto Miranda Nacif, Claudionor Nunes Coelho, Harry Foster, Flávio Miana de Paula, Edjard Mota, Márcia Roberta Falcão Mota, Antônio Otávio Fernandes	On-Chip Property Verification Using Assertion Processors.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Thomas Hollstein, Ralf Ludewig, Heiko Zimmer, Christoph Mager, Simon Hohenstern, Manfred Glesner	Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	João M. S. Silva, Luís Miguel Silveira	Dynamic Models for Substrate Coupling in Mixed-Mode Systems.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis	Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Eduardo A. C. da Costa, José C. Monteiro 0001, Sergio Bampi	Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Nicole Drechsler, Rolf Drechsler	Exploration of Sequential Depth by Evolutionary Algorithms.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani	Validation of Asynchronous Circuit Specifications Using IF/CADP.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Valentina Ciriani, Anna Bernasconi 0001, Rolf Drechsler	Stuck-At-Fault Testability of SPP Three-Level Logic Forms.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes (eds.)	SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France	VLSI-SOC	2002	DBLP BibTeX RDF
26	Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre	Functional Test Generation using Constraint Logic Programming.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, Si Mahmoud Karabernou	Reconfigurable Architecture Using High Speed FPGA.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Braulio Adriano de Mello, Flávio Rech Wagner	A Standardized Co-simulation Backbone.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Stephen M. Pisuk, Peter Hsin-Yu Wu	Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy	Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell	On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Eric Senn, Eric Martin 0001	A Vision System on Chip for Industrial Control.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Morgan Hirosuke Miki, Motoki Kimura, Takao Onoye, Isao Shirakawa	High Performance Java Hardware Engine and Software Kernel for Embedded Systems.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Amaury Nève, Denis Flandre	Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Philippe Maurine, Nadine Azémard, Daniel Auvergne	Gate Sizing for Low Power Design.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Didier Demigny, Lounis Kessal, J. Pons	Fast Recursive Implementation of the Gaussian Filter.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre	Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Bruno Casadei, Jean-Piere Le Normand, Yann Hu, Bernard Cunin	Design of a Fast CMOS APS Imager for High Speed Laser Detections.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Jean-Max Dutertre, F. M. Roche, Guy Cathébras	Integration of Robustness in the Design of a Cell.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Takashi Komuro, Masatoshi Ishikawa	64×64 Pixels General Purpose Digital Vision Chip.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Christophe Lallement, François Pêcheux, Yannick Hervé	A VHDL-AMS Case Study: The Incremental Design of an Efficient 3rd Generation MOS Model of a Deep Sub Micron Transistor.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Samy Meftali, Ferid Gharsalli, Frédéric Rousseau 0001, Ahmed Amine Jerraya	Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys	A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Peer Johannsen, Rolf Drechsler	Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Leandro Soares Indrusiak, Jürgen Becker 0001, Manfred Glesner, Ricardo Augusto da Luz Reis	Distributed Collaborative Design over Cave2 Framework.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Nuno Roma, Leonel Sousa	A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Catherine H. Gebotys, Radu Muresan	Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet	Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing.	VLSI-SOC	2001	DBLP BibTeX RDF
26	René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Random Adjacent Sequences: An Efficient Solution for Logic BIST.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Jung Hyun Choi, Sergio Bampi	CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne	Feasible Delay Bound Definition.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Vincent Beroulle, Laurent Latorre, M. Dardalhon, Coumar Oudéa, Guy Perez, Francis Pressecq, Pascal Nouet	Impact of Technology Spreading on MEMS design Robustness.	VLSI-SOC	2001	DBLP BibTeX RDF
26	David Bernard, Christian Landrault, Pascal Nouet	Interconnect Capacitance Modelling in a VDSM CMOS Technology.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi	Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Kiyoo Itoh 0001, Hiroyuki Mizuno	Low-Voltage Embedded-RAM Technology: Present and Future.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Erik Jan Marinissen	An Industrial Approach to Core-Based System Chip Testing.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Cristiano C. de Araújo, Edna Barros	Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design.	VLSI-SOC	2001	DBLP BibTeX RDF
26	João Cláudio Soares Otero, Flávio Rech Wagner	An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Patricia Guitton-Ouhamou, Cécile Belleudy, Michel Auguin	Power Consumption Model for the DSP OAK Processor.	VLSI-SOC	2001	DBLP BibTeX RDF
26	P. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, Si Mahmoud Karabernou	Two ASIC for Low and Middle Levels of Real Time Image Processing.	VLSI-SOC	2001	DBLP BibTeX RDF
26	Raul Camposano, Don MacMillen	Design Technology for Systems-on-Chip.	VLSI-SOC	2001	DBLP BibTeX RDF
25	G. Seetharaman, B. Venkataramani	Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA
25	Diogo José Costa Alves, Edna Barros	A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns.	SBCCI	2009	DBLP DOI BibTeX RDF	LBIST, compressed test patterns, test, SoC, self-test
25	Iman Saleh 0002, Gregory Kulczycki, M. Brian Blake	A Reusable Model for Data-Centric Web Services.	ICSR	2009	DBLP DOI BibTeX RDF	Data-Centric Web Services, SOA, Formal Specification, SOC
25	Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja	DX-compactor: distributed X-compaction for SoCs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dx-compactor, hierarchical compactor, x-compactor, SoC, compaction
25	Warren Stapleton, Paul Tobin	Verification problems in reusing internal design components.	DAC	2009	DBLP DOI BibTeX RDF	verification, validation, IP, SOC
25	Santhosh Coimbatore Vaidyanathan, Amit Mangesh Brahme, Sukumar Jairam	Techniques for Early Package Closure in System-in-Packages.	ISQED	2008	DBLP DOI BibTeX RDF	spacer, landing, SoC, SIP, CSP, MCM, POP
25	Vicente Galiano Ibarra, Héctor Migallón Gomis, David Pérez-Caparrós, Juan Alejandro Palomino Benito, Marcos Martínez	Speeding Up in Distributed SystemC Simulations.	DCAI	2008	DBLP DOI BibTeX RDF	MPI, SoC, Distributed Simulation, SystemC, RTL
25	Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Access Regulation to Hot-Modules in Wormhole NoCs.	NOCS	2007	DBLP DOI BibTeX RDF	SoC, resource management, Network on-Chip, hotspot, wormhole
25	Antoine Perrin, Frank Ghenassia	Bridging gap between simulation and spreadsheet study.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	performance, verification, SoC, SystemC
25	Tobias Bjerregaard, Shankar Mahadevan	A survey of research and practices of Network-on-chip.	ACM Comput. Surv.	2006	DBLP DOI BibTeX RDF	Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions
25	Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami	REDEFIS: a system with a redefinable instruction set processor.	SBCCI	2006	DBLP DOI BibTeX RDF	ISA customization, dynamically reconfigurable processor, low power, SoC, high performance
25	Christoph Kutter	Design challenges for mobile communication devices.	ISLPED	2006	DBLP DOI BibTeX RDF	design for low power, SoC, leakage
25	Stephen E. Krufka, Phillip Christie	Terminal optimization analysis for functional block re-use.	SLIP	2002	DBLP DOI BibTeX RDF	optimization, SoC, interconnect, Rent's rule
25	Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama	Trends in Low Power Digital System-on-Chip Designs (invited).	ISQED	2002	DBLP DOI BibTeX RDF	Low-Power CMOS, Design, SoC, Digital
25	Bilge Saglam Akgul, Jaehwan Lee 0002, Vincent John Mooney III	A system-on-a-chip lock cache with task preemption support.	CASES	2001	DBLP DOI BibTeX RDF	lock synchronization, multi-processor synchronization, SoC, shared memory, RTOS, preemption
25	Ruofan Xu, Michael S. Hsiao	Embedded core testing using genetic algorithms.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	gate level implementation, user defined logic, random inputs, high level benchmarks, wrapper size, genetic algorithms, genetic algorithms, fault diagnosis, logic testing, controllability, controllability, high level synthesis, automatic test pattern generation, observability, observability, application specific integrated circuits, fault coverage, SOC, test application time, test patterns, embedded core testing, internal state
24	Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara	Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF	TAM design, thermal-aware test, wrapper design, test scheduling, SOC test
24	Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	oscillation ring (OR) test scheme, open faults, crosstalk glitches, IEEE P1500, wrapper cell design, stuck-at faults, delay faults, SOC testing, interconnect test
24	D. Barros Júnior, Marcial Jesús Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas 0001, João Paulo Teixeira 0001	Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	intermittent faults modeling and simulation, digital SoC, EMI/EMC standard compliance, delay fault simulation, power supply voltage transients, fault tolerance
24	Resve A. Saleh	An approach that will NoC your SoCs off!	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	networks on chips, SoC design, Moore's law, interconnect delay, IP blocks
24	Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan, Srimat T. Chakradhar	SECA: security-enhanced communication architecture.	CASES	2005	DBLP DOI BibTeX RDF	AMBA Bus, security-aware design, small embedded systems, security, communication, access control, architecture, intrusion detection, system-on-chip (SoC), attacks, bus, digital rights management (DRM)
24	Lei Li 0036, Krishnendu Chakrabarty	On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	compression codes, SOC testing, embedded core testing, test data volume
24	Sandeep Kumar Goel, Erik Jan Marinissen	A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	TAM and wrapper design, test scheduling, SOC-test
24	Lei Li 0036, Krishnendu Chakrabarty, Nur A. Touba	Test data compression using dictionaries with selective entries and fixed-length indices.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	reduced pin-count testing, SoC testing, test application time, Embedded core testing, test data volume
24	Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty	Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.	DAC	2003	DBLP DOI BibTeX RDF	bandwidth matching, automatic test equipment (ATE), test access mechanism (TAM), scan chains, system-on-chip (SOC)
24	Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki	CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	SoC test control, TAPed cores, P1500 wrappers, test access mechanism, I/O bandwidth
24	Zahra Sadat Ebadi, André Ivanov	Design of an Optimal Test Access Architecture Using a Genetic Algorithm.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	Optimal testing time, test data width, Genetic Algorithm, Test Access Mechanism (TAM), SOC testing, Embedded core testing
24	Liang-Hao Wang, Dongxiao Li, Ming Zhang 0001	SoC Design of VLD in Multi-standard Video Decoder for Wearable Multimedia Players.	APWCS	2010	DBLP DOI BibTeX RDF	multi-standard, video, SoC, wearable system
24	Wei Liu	A SOC Design for AVS Video Decoding.	PACIIA (1)	2008	DBLP DOI BibTeX RDF	C model, SOC, AVS, IP core
24	Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne H. Wolf	Roundtable: Envisioning the Future for Multiprocessor SoC.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	multiprocessor, SoC, multicore, MPSoC, CPU, chip
24	Peter Rickert, William Krenik	Cell Phone Integration: SiP, SoC, and PoP.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	PiP, analog integration, RF integration, memory integration, SoC, SiP, PoP
24	Jong-Yeol Lee, In-Cheol Park	Timed compiled-code simulation of embedded software for performance analysis of SOC design.	DAC	2002	DBLP DOI BibTeX RDF	timed functional simulation, compiler, SOC
23	Soraj Hongladarom	Global culture, local cultures and the internet: The Thai example.	AI Soc.	1999	DBLP DOI BibTeX RDF	Cultural homogenisation, Michael Walzer, soc.culture.thai, Thai culture, Thai language, thick, Usenet newsgroup, Internet, thin, Thailand
23	Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Hoi-Jun Yoo	A Low-Power Multimedia SoC with Fully Programmable 3D Graphics for Mobile Devices.	IEEE Computer Graphics and Applications	2009	DBLP DOI BibTeX RDF	Mobile multimedia SoC, mobile unified shader, low-power design, 3D graphics, programmable
23	Philippe Grosse, Yves Durand, Paul Feautrier	Methods for power optimization in SOC-based data flow systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	4G base-band modem, data-driven SOC, synchronous data-flow graph, Power optimization
23	Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso, Edgar E. Sánchez, Matteo Sonza Reorda	Automatic Functional Stress Pattern Generation for SoC Reliability Characterization.	ETS	2009	DBLP DOI BibTeX RDF	SoC reliability characterization
23	Zhiyuan He 0002, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi	Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Thermal-aware testing, Test scheduling, SoC testing
23	Hongkyun Jung, Xianzhe Jin, Younjin Jung, Ok Kim, Byoungyup Lee, Jungbum Heo, Kwangki Ryoo	Design of Multimedia SoC Platform with a Crossbar On-Chip Bus for Embedded Systems.	NCM (1)	2008	DBLP DOI BibTeX RDF	SoC platform, crossbar, on-chip bus
23	Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, José María Monzó, Christoph W. Lerche, Jorge Daniel Martínez, Angel Sebastiá, Fernando Mateo	SoC-Based Implementation of the Backpropagation Algorithm for MLP.	HIS	2008	DBLP DOI BibTeX RDF	system-on-chip (SoC), parallel systems, multilayer perceptron (MLP), backpropagation, timing model
23	Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley	GALS SoC interconnect bus for wireless sensor network processor platforms.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	SoC bus, application specific bus, system on chip bus, WSN, wireless sensor network, low power, GALS
23	Mahmut T. Kandemir	Reducing energy consumption of multiprocessor SoC architectures by exploiting memory bank locality.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Banked memory systems, bank locality, compiler optimization, energy consumption, multiprocessor SoC
23	Vijay K. Jain, Glenn H. Chapman	Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC.	DFT	2006	DBLP DOI BibTeX RDF	3D Heterogeneous sensor, redundancy and reconfiguration, energy economization, heterogeneous SOC, J-platform, defect tolerance
23	Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete	Fine-grain design space exploration for a cartographic SoC multiprocessor.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF	SoC Multiprocessors, performance evaluation, embedded systems, trace-driven simulation, multiprocessor architecture
23	Philippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber	Hardware Partitioning Software for Dynamically Reconfigurable SoC Design.	IWSOC	2003	DBLP DOI BibTeX RDF	FPGA Dynamic Reconfiguration RTR SOC
23	Shuichi Sakai	CMP on SoC: Architect's View.	ISSS	2002	DBLP DOI BibTeX RDF	CMP (Chip Multiprocessor), I/O centric, SoC (System on Chip), parallel processing, dependability
23	Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty	Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
23	Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith	SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	System design, hardware/software codesign
23	Dan Zhao 0001, Yi Wang 0007	MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF