Search results for "analog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Sudarshan Bahukudumbi, Krishna Bharath	A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
22	Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert	Performance space modeling for hierarchical synthesis of analog integrated circuits.	DAC	2005	DBLP DOI BibTeX RDF	hierarchical synthesis
22	B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal	A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
22	Chandrasekar Rajagopal, Adrián Núñez-Aldana	CMOS Analog Programmable Logic Array.	ISVLSI	2004	DBLP DOI BibTeX RDF
22	Sheldon X.-D. Tan, Zhenyu Qi, Hang Li	Hierarchical Modeling and Simulation of Large Analog Circuits.	DATE	2004	DBLP DOI BibTeX RDF
22	Tholom Kiely, Georges G. E. Gielen	Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines.	DATE	2004	DBLP DOI BibTeX RDF
22	Régis Leveugle, Abdelaziz Ammari	Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow.	DATE	2004	DBLP DOI BibTeX RDF
22	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi	Hierarchical extraction and verification of symmetry constraints for analog layout automation.	ASP-DAC	2004	DBLP DOI BibTeX RDF
22	Olivier Bournez, Emmanuel Hainry	An Analog Characterization of Elementarily Computable Functions over the Real Numbers.	ICALP	2004	DBLP DOI BibTeX RDF
22	Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterjee	Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
22	Donghoon Han, Abhijit Chatterjee	Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
22	Xin Li 0001, Padmini Gopalakrishnan, Yang Xu 0017, Lawrence T. Pileggi	Robust analog/RF circuit design with projection-based posynomial modeling.	ICCAD	2004	DBLP DOI BibTeX RDF
22	Hyongsuk Kim, Hongrak Son, Tamás Roska, Leon O. Chua	Very high speed Viterbi decoder with circularly connected analog CNN cell array.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
22	Radu M. Secareanu, Bill Peterson	An adaptive circuits concept to address mismatch in analog circuits.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
22	Jorge Luís Machado do Amaral, José Franco Machado do Amaral, Ricardo Tanscheit, Marco Aurélio Cavalcanti Pacheco	An Immune Inspired Fault Diagnosis System for Analog Circuits using Wavelet Signatures.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	Sina Balkir, Günhan Dündar, Güner Alpaydin	Evolution Based Synthesis of Analog Integrated Circuits and Systems.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	Pedro F. Vieira, Leonardo Bruno de Sá, João P. B. Botelho, Antonio Carneiro de Mesquita Filho	Evolutionary Synthesis of Analog Circuits Using Only MOS Transistors.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
22	Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay	Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
22	Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud Magdy, Noha Hassan, Noha Soliman, Sami Moussa	Synthesis of CMOS Analog Cells Using AMIGO.	DATE	2003	DBLP DOI BibTeX RDF
22	Alessandro Girardi, Sergio Bampi	LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks.	DATE	2003	DBLP DOI BibTeX RDF
22	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi	Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology.	SBCCI	2003	DBLP DOI BibTeX RDF
22	John A. Nestor, David A. Rich	Integrating Digital, Analog, and Mixed-Signal Design in an Undergraduate ECE Curriculum.	MSE	2003	DBLP DOI BibTeX RDF
22	Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio	An Analog Integrated Circuit Design Laboratory.	MSE	2003	DBLP DOI BibTeX RDF
22	Dean Liu, Stefanos Sidiropoulos, Mark Horowitz	A Framework for Designing Reusable Analog Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
22	David A. Gwaltney, Michael I. Ferguson	Hardware Evolution of Analog Speed Controllers for a DC Motor.	GECCO	2003	DBLP DOI BibTeX RDF
22	Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi	Automatic analog layout retargeting for new processes and device sizes.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
22	Eric E. Fabris, Luigi Carro, Sergio Bampi	An analog signal interface with constant performance for SoCs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
22	Stephen K. Sunter	Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus.	ITC	2003	DBLP DOI BibTeX RDF
22	Ramakrishna Voorakaranam, Randy Newby, Sasikumar Cherubal, Bob Cometta, Thomas Kuehl, David M. Majernik, Abhijit Chatterjee	Production Deployment of a Fast Transient Testing Methodology for Analog Circuits : Case Study and Results.	ITC	2003	DBLP DOI BibTeX RDF
22	David A. Gwaltney, Michael I. Ferguson	Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
22	Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi, P. K. Ghosh	Synthesis Of Programmable Current Mode Linear Analog Circuit.	VLSI Design	2003	DBLP DOI BibTeX RDF	Band Reject Filter, Low Pass Filter, Band Pass Filter, Operational Transconductance Amplifier, High Pass Filter
22	Daniel Micusík, Viera Stopjaková, Lubica Benusková	Application of Feed-forward Artificial Neural Networks to the Identification of Defective Analog Integrated Circuits.	Neural Comput. Appl.	2002	DBLP DOI BibTeX RDF	Circuits response investigation, Fault modelling and simulation, Resilient-backpropagation neural networks, Signal filtering, Supply current analysis
22	Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi	Efficient synthesis of OTA network for linear analog functions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
22	Carlo Guardiani, Patrick McNamara, Lidia Daldoss, Sharad Saxena, Stefano Zanella, Wei Xiang, Suli Liu	Analog IP Testing: Diagnosis and Optimization.	DATE	2002	DBLP DOI BibTeX RDF
22	Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu	On-chip Analog Response Extraction with 1-Bit ? - Modulators.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
22	Shambhu J. Upadhyaya, Jae Min Lee, Padmanabhan Nair	Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point Insertion.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
22	Maziar Tavakoli Dastjerdi, Rahul Sarpeshkar	A low-noise nonlinear feedback technique for compensating offset in analog multipliers.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
22	Andrea Xotta, Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, Melchiorre Bruccoleri, Giorgio Betti	An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
22	Janusz A. Starzyk, Dong Liu	Locating stuck faults in analog circuits.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
22	Paul D. Smith, Matt Kucic, Richard Ellis, Paul E. Hasler, David V. Anderson	Mel-frequency cepstrum encoding in analog floating-gate circuitry.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
22	Sule Ozev, Alex Orailoglu	Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis.	VTS	2002	DBLP DOI BibTeX RDF
22	José Franco Machado do Amaral, Jorge Luís Machado do Amaral, Cristina Costa Santini, Ricardo Tanscheit, Marley M. B. R. Vellasco, Marco Aurélio Cavalcanti Pacheco	Towards Evolvable Analog Fuzzy Logic Controllers.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
22	Faizal Arya Samman, Rhiza S. Sadjad	Analog MOS circuit design for reconfigurable fuzzy logic controller.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
22	Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley	Remembrance of circuits past: macromodeling by data mining in large analog design spaces.	DAC	2002	DBLP DOI BibTeX RDF
22	Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts	AMGIE-A synthesis environment for CMOS analog integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
22	Mani Soma, Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg	Hierarchical ATPG for Analog Circuits and Systems.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
22	S. Sandeep Pradhan, Kannan Ramchandran	Enhancing Analog Image Transmission Systems Using Digital Side Information: A New Wavelet-Based Image Coding Paradigm.	Data Compression Conference	2001	DBLP DOI BibTeX RDF
22	Per Löwenborg, Håkan Johansson	Quantization noise in filter bank analog-to-digital converters.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
22	Abdelhakim Khouas, Anne Derieux	FDP: fault detection probability function for analog circuits.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
22	Sangjin Hong, Wayne E. Stark	Performance effects of using analog memory in baseband signal processing systems design.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
22	Keng Hoong Wee, Toshiyuki Nozawa, Takemi Yonezawa, Yuichiro Yamashita, Tadashi Shibata, Tadahiro Ohmi	High-precision analog EEPROM with real-time write monitoring.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
22	Felix Lustenberger, Hans-Andrea Loeliger	On mismatch errors in analog-VLSI error correcting decoders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
22	Krissanapong Nandhasri, Jitkasem Ngarmnil	Designs of analog and digital comparators with FGMOS.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
22	Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin	Floating-gate CMOS differential analog inverter for ultra low-voltage applications.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
22	Cristina Costa Santini, Marco Aurélio Cavalcanti Pacheco, Marley M. B. R. Vellasco, Moisés H. Szwarcman, Ricardo Salem Zebulum	Pama - Programmable Analog Multiplexer Array.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
22	Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar	Efficient handling of operating range and manufacturing linevariations in analog cell synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
22	Mattias Duppils, Christer Svensson	Low power mixed analog-digital signal processing.	ISLPED	2000	DBLP DOI BibTeX RDF
22	Ricardo Salem Zebulum, Cristina Costa Santini, Helio Takahiro Sinohara, Marco Aurélio Cavalcanti Pacheco, Marley M. B. R. Vellasco, Moisés H. Szwarcman	A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
22	Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi	Design of OTA Based Field Programmable Analog Array.	VLSI Design	2000	DBLP DOI BibTeX RDF	Operational Transconductance Amplifier(OTA), Amplitude Modulation (AM), Frequency Modulation (FM)
22	Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke	A current driven routing and verification methodology for analog applications.	DAC	2000	DBLP DOI BibTeX RDF	multiterminal signal nets, routing, verification, design methodology, Steiner tree, electromigration, current density
22	Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums	A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC.	DAC	2000	DBLP DOI BibTeX RDF
22	Jing Xu, Raymond E. Siferd, Robert L. Ewing	High Performance CMOS Analog Arithmetic Circuits.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
22	Emmanuel Simeu, Arno W. Peters, Iyad Rayane	Automatic Design of Optimal Concurrent Fault Detector for Linear Analog Systems.	FTCS	1999	DBLP DOI BibTeX RDF	concurrent, detection, state space, residual, netlist
22	Aryan Saed, Majid Ahmadi, Graham A. Jullien	Arithmetic Circuits for Analog Digits.	ISMVL	1999	DBLP DOI BibTeX RDF
22	Jaime Velasco-Medina, Iyad Rayane, Michael Nicolaidis	On-Line BIST for Testing Analog Circuits.	ICCD	1999	DBLP DOI BibTeX RDF
22	Xuan Zeng 0001, J. Guan, Wenqing Zhao, Pushan Tang, Dian Zhou	A constraint-based placement refinement method for CMOS analog cell layout.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
22	Sudip Chakrabarti, Abhijit Chatterjee	Fault modeling and fault sampling for isolating faults in analog and mixed-signal circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	Felix Lustenberger, Markus Helfenstein, Hans-Andrea Loeliger, Felix Tarköy, George S. Moschytz	An analog VLSI decoding technique for digital codes.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	Ying Wang, Han Ngee Tan	The Development of Analog SPICE Behavioral Model Based on IBIS Model.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
22	Stephen K. Sunter, Naveena Nagi	Test Metrics for Analog Parametric Faults.	VTS	1999	DBLP DOI BibTeX RDF
22	Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen	Probabilistic fault detection and the selection of measurements for analog integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
22	Jason D. Lohn, Silvano Colombano	Automated Analog Circuit Sythesis Using a Linear Representation.	ICES	1998	DBLP DOI BibTeX RDF
22	Chieh-Yuan Chao, Hung-Jen Lin, L. Miler	Optimal testing of VLSI analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
22	Vladimír Székely, Andras Pahi, András Poppe, Márta Rencz, Alpar Csendes	SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells.	ED&TC	1997	DBLP DOI BibTeX RDF
22	C.-J. Richard Shi, Xiang-Dong Tan	Symbolic analysis of large analog circuits with determinant decision diagrams.	ICCAD	1997	DBLP DOI BibTeX RDF
22	Fabio Ancona, Giorgio Oddone, Stefano Rovetta, Gianni Uneddu, Rodolfo Zunino	VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
22	Yingquan Zhou, Mike W. T. Wong, Yinghua Min	Hardware reduction in continuous checksum-based analog checkers: Algorithm and its analysis.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	testing, diagnosis, error detection, error correction, hardware overhead
22	D. J. Klein, Mark L. Manwaring	A Differential Model Approach To Analog Design Automation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF
22	Mircea R. Stan, Wayne P. Burleson, Christopher I. Connolly, Roderic A. Grupen	Analog VLSI for robot path planning.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
22	Howard C. Card, Christian R. Schneider, Roland S. Schneider	Learning capacitive weights in analog CMOS neural networks.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
22	Eric A. Vittoz	Analog VLSI signal processing: Why, where, and how?	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
22	Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar	Synthesis of manufacturable analog circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
22	Abhijit Chatterjee	Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
22	Ji-Chien Lee, Bing J. Sheu, Rama Chellappa	A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
22	Marwan A. Jabri, Stephen Pickard, Philip H. W. Leong, Y. Xie	Algorithmic and implementation issues in analog low power learning neural network chips.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
22	Lisa G. Dron	The multiscale veto model: A two-stage analog network for edge detection and image reconstruction.	Int. J. Comput. Vis.	1993	DBLP DOI BibTeX RDF
22	Michele Favalli, Piero Olivo, Bruno Riccò	A probabilistic fault model for 'analog' faults in digital CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
22	Timothy K. Horiuchi, Wyeth Bair, Brooks Bishofberger, Andrew Moore 0002, Christof Koch, John Lazzaro	Computing motion using analog VLSI vision chips: An experimental comparison among different approaches.	Int. J. Comput. Vis.	1992	DBLP DOI BibTeX RDF
22	Francisco J. Pelayo, Begoña Pino, Alberto Prieto, Julio Ortega 0001, F. J. Fernández	CMOS Implementation of Synapse Matrices with Programmable Analog Weights.	IWANN	1991	DBLP DOI BibTeX RDF
22	Michel Verleysen, Paul G. A. Jespers	Analog VLSI Synapse Matrix with Enhanced Stochastic Computations.	IWANN	1991	DBLP DOI BibTeX RDF
22	Fathey M. El-Turky, Elizabeth E. Perry	BLADES: an artificial intelligence approach to analog circuit design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
22	Esa Korhonen, Juha Kostamovaara	Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs.	ETS	2011	DBLP DOI BibTeX RDF	didital-analog conversion, algorithms, testing, histograms, linearity, analog-digital conversion
22	B. K. Mishra 0001, Sandhya Save	Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance.	ICSAP	2010	DBLP DOI BibTeX RDF	Analog circuit designs methodologies, Analog design automation, Op-amps, AMS, Simulated Annealing, CAD, SoC, ASIC, SPICE, EDA tools
22	Byoungho Kim, Nash Khouzam, Jacob A. Abraham	Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits.	VTS	2008	DBLP DOI BibTeX RDF	Loopback Test, Aperture Jitter, Digital-to-Analog Converter, Analog-to-Digital Converter, ADC, Mixed-Signal Testing, DAC
22	Stephen C. Terry, Mohammad M. Mojarradi, Benjamin J. Blalock, Jesse A. Richmond	Adaptive gate biasing: a new solution for body-driven current mirrors.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	SOI analog, body driving, current mirrors, ultra-low-voltage analog circuit design
22	Jaijeet S. Roychowdhury	A time-domain RF steady-state method for closely spaced tones.	DAC	2002	DBLP DOI BibTeX RDF	MPDE, RF switching mixers, analog/RF simulation, artificial time scales, difference-frequency time scales, multi-time PDEs, shooting, analog, homotopy, mixed-signal, envelope, continuation methods, harmonic balance
22	Andrea Boni, Andrea Pierazzi	Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs.	DFT	1998	DBLP DOI BibTeX RDF	BiCMOS analog integrated circuits, Monte Carlo methods, Yield optimization, Analog-digital conversion
22	Sudhir Aggarwal	An Enhanced Macromodel for a CMOS Operational Amplifier for HDL Implementation.	VLSI Design	1996	DBLP DOI BibTeX RDF	VHDL-Analog, Non-linear model, Analog IC's, Operational Amplifier, Macromodel
22	C. K. Yuen	Negabinary A/D Conversion.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	negabinary analog-digital conversion, Analog-digital conversion
20	Akitoshi Kawamura	Differential recursion.	ACM Trans. Comput. Log.	2009	DBLP DOI BibTeX RDF	differentially algebraic functions, real recursive functions, transcendentally transcendental functions, initial value problems, Analog computation