Search results for "interconnects"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Frank T. Hady, Ron Minnich, Dan Burns, Kevin Smith	A memory integrated network interface.	Hot Interconnects	1994	DBLP DOI BibTeX RDF
30	Deog-Kyoon Jeong, David D. Lee, J. Duane Northcutt, Andreas von Bechtolsheim, David R. Ditzel, Amnon Fisher	Hotpads - macro-dells for gigabit I/O.	Hot Interconnects	1994	DBLP DOI BibTeX RDF
30	David A. Patterson 0001	A case for NOW (networks-of-workstations).	Hot Interconnects	1994	DBLP DOI BibTeX RDF
30	James C. Hoe, Andy Boughton	Network substrate for parallel processing on a workstation cluster.	Hot Interconnects	1994	DBLP DOI BibTeX RDF
30	Chuck Seitz	Myrinet-a gigabit-per-second local-area network.	Hot Interconnects	1994	DBLP DOI BibTeX RDF
29	Wei Huang 0003, Jiuxing Liu, Matthew J. Koop, Bülent Abali, Dhabaleswar K. Panda 0001	Nomad: migrating OS-bypass networks in virtual machines.	VEE	2007	DBLP DOI BibTeX RDF	virtual machines, migration, xen, InfiniBand, high speed interconnects
29	J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Constant impedance scaling paradigm for interconnect synthesis.	SLIP	2006	DBLP DOI BibTeX RDF	transmission lines, interconnect optimization, global interconnects
29	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
28	Cees T. A. M. de Laat, Chris Develder, Admela Jukan, Joe Mambretti	Introduction.	Euro-Par	2009	DBLP DOI BibTeX RDF
28	Yan Lin 0001, Lei He 0001	Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
28	Jun Chen 0008, Lei He 0001	Modeling and synthesis of multiport transmission line for multichannel communication.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
28	Kenichi Okada, Takumi Uezono, Kazuya Masu	Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.	PATMOS	2006	DBLP DOI BibTeX RDF
28	Allan Carroll, Carl Ebeling	Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding.	FPL	2006	DBLP DOI BibTeX RDF
28	Praveen Ghanta, Sarma B. K. Vrudhula	Variational Interconnect Delay Metrics for Statistical Timing Analysis.	ISQED	2006	DBLP DOI BibTeX RDF
28	Abhinav Vishnu, Prachi Gupta, Amith R. Mamidala, Dhabaleswar K. Panda 0001	Scalable systems software - A software based approach for providing network fault tolerance in clusters with uDAPL interface: MPI level design and performance evaluation.	SC	2006	DBLP DOI BibTeX RDF
28	Haitham S. Hamza, Jitender S. Deogun	Design and Analysis of a New Class of WDM Optical Interconnect Architectures.	BROADNETS	2006	DBLP DOI BibTeX RDF
28	Lin Zhong 0001, Niraj K. Jha	Interconnect-aware low-power high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
28	Li Chen, Xiaoliang Bai, Sujit Dey	Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	interconnect, crosstalk, processor, self-test
28	Wichian Sirisaengtaksin, Sandeep K. Gupta 0001	Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
28	Sung-Mo Kang	On-chip thermal engineering for peta-scale integration.	ISPD	2002	DBLP DOI BibTeX RDF
28	Lin Zhong 0001, Niraj K. Jha	Interconnect-aware high-level synthesis for low power.	ICCAD	2002	DBLP DOI BibTeX RDF
28	Li-Rong Zheng 0001, Hannu Tenhunen	Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits.	ARVLSI	1999	DBLP DOI BibTeX RDF	Mixed-Signal VLSI, Interconnection, Crosstalk, Noise Margin
27	Lin Liu 0004, Yuanyuan Yang 0001	Achieving 100% Throughput in Input-Buffered WDM Optical Packet Interconnects.	IEEE Trans. Parallel Distributed Syst.	2011	DBLP DOI BibTeX RDF	WDM optical packet interconnects, input buffered, 100% throughput, packet scheduling, wavelength conversion
27	Balazs Gerofi, Yutaka Ishikawa	RDMA Based Replication of Multiprocessor Virtual Machines over High-Performance Interconnects.	CLUSTER	2011	DBLP DOI BibTeX RDF	Fault-Tolerance, Virtualization, Checkpoint, Recovery, Hypervisor, RDMA, High-Performance Interconnects
27	Peter M. Kelly, Fergal Tuffy, Valeriu Beiu, Liam McDaid	Reduced Interconnects in Neural Networks Using a Time Multiplexed Architecture Based on Quantum Devices.	NanoNet	2009	DBLP DOI BibTeX RDF	Quantum device, resonant tunneling device (RTD), time multiplexed architecture (TMA), neural network (NN), interconnects
27	Bo Fu, Paul Ampadu	A Dual-Mode Hybrid ARQ Scheme for Energy Efficient On-Chip Interconnects.	NanoNet	2008	DBLP DOI BibTeX RDF	Adaptive error control, interleaving, on-chip interconnects, hybrid ARQ
27	Mohammad J. Rashti, Ahmad Afsahi	Improving Communication Progress and Overlap in MPI Rendezvous Protocol over RDMA-enabled Interconnects.	HPCS	2008	DBLP DOI BibTeX RDF	Rendezvous Protocol, Communication Progress, MPI, Overlap, RDMA, High-performance Interconnects
27	Rasit Onur Topaloglu	Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics.	ISQED	2008	DBLP DOI BibTeX RDF	foldable electronics, nanoparticle interconnects, process variations
27	Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli	Early wire characterization for predictable network-on-chip global interconnects.	SLIP	2007	DBLP DOI BibTeX RDF	early wire characterization, design methodology, NoCs, global interconnects
27	Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail	Physical limitations on the bit-rate of on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	damping factor, delay, interconnects, bit-rate
27	Bhaskar Mukherjee, Lei Wang, Andrea Pacelli	A practical approach to modeling skin effect in on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	interconnects, circuit simulation, skin effect
27	Pawan Kapur, Gaurav Chandra, Krishna Saraswat	Power estimation in global interconnects and its reduction using a novel repeater optimization methodology.	DAC	2002	DBLP DOI BibTeX RDF	repeaters, power dissipation, global interconnects
27	Andrew B. Kahng, Kei Masuko, Sudhakar Muddu	Analytical delay models for VLSI interconnects under ramp input.	ICCAD	1996	DBLP DOI BibTeX RDF	SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
26	Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty	SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Core-based system-on-chip, test scheduling, test-access mechanism (TAM), interconnect testing
26	Krishna Saraswat	Performance comparison of cu/low-k, carbon nanotube, and optics for on-chip and off-chip interconnects.	SLIP	2009	DBLP DOI BibTeX RDF	copper, energy per bit, power, latency, bandwidth, optical interconnect, carbon nanotube
26	Yariv Aridor, Tamar Domany, Oleg Goldshmidt, Yevgeny Kliteynik, Edi Shmueli, José E. Moreira	Multitoroidal Interconnects For Tightly Coupled Supercomputers.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF	parallel architectures, network topology, scheduling and task partitioning
26	Byungsub Kim, Vladimir Stojanovic	Characterization of Equalized and Repeated Interconnects for NoC Applications.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
26	Christof Teuscher, Anders A. Hansson	Non-traditional irregular interconnects for massive scale SoC.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas	A High-Performance Bus Architecture for Strongly Coupled Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	high-speed bus, crosstalk
26	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
26	Partha Kundu, Li-Shiuan Peh	Guest Editors' Introduction: On-Chip Interconnects for Multicores.	IEEE Micro	2007	DBLP DOI BibTeX RDF	embedded systems, system on chip, network on chip, multicore architectures, on-chip interconnection networks
26	Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis	Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan	Lightweight Error Correction Coding for System-Level Interconnects.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Interconnections (subsystems), coding and information theory, error control codes, interconnection architectures, code design, coding tools and techniques
26	Manhee Lee, Minseon Ahn, Eun Jung Kim 0001	I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems.	PACT	2007	DBLP DOI BibTeX RDF
26	Jun Wang, Ge Zhang 0007, Weiwu Hu	An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Massimo Alioto, Gaetano Palumbo	Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Denis Deschacht	DSM interconnects: importance of inductance effects and corresponding range of length.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
26	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	Modeling and analysis of crosstalk noise in coupled RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
26	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier	Modeling of Crosstalk Fault in Defective Interconnects.	PATMOS	2006	DBLP DOI BibTeX RDF	defect-based-crosstalk fault model, signal integrity losses, aggres-sor-victim, ABCD-model, crosstalk-hazards
26	Karthikeyan Vaidyanathan, Sundeep Narravula, Dhabaleswar K. Panda 0001	DDSS: A Low-Overhead Distributed Data Sharing Substrate for Cluster-Based Data-Centers over Modern Interconnects.	HiPC	2006	DBLP DOI BibTeX RDF
26	Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava	Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems.	ASP-DAC	2006	DBLP DOI BibTeX RDF
26	Alejandro Martínez, George Apostolopoulos, Francisco José Alfaro, José L. Sánchez 0002, José Duato	QoS Support for Video Transmission in High-Speed Interconnects.	HPCC	2006	DBLP DOI BibTeX RDF	Clusters, Scheduling, QoS, Virtual Channels, Switch Design
26	Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail	Importance of volume discretization of single and coupled interconnects.	ICCAD	2006	DBLP DOI BibTeX RDF
26	Satoshi Komatsu, Masahiro Fujita	An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
26	K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas	A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
26	B. Haddadin, Min Ma, T. S. Roseanu, Roni Khazaka	Efficient Macromodel for Interconnects Excited by Incident Fields.	CCECE	2006	DBLP DOI BibTeX RDF
26	Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar	A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects.	VLSI Design	2006	DBLP DOI BibTeX RDF
26	Min Tang, Jun-Fa Mao	Optimization of Global Interconnects in High Performance VLSI Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
26	Guillermo L. Taboada, Juan Touriño, Ramon Doallo	Efficient Java Communication Protocols on High-speed Cluster Interconnects.	LCN	2006	DBLP DOI BibTeX RDF
26	Xiaomeng Shi, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do, Erping Li	Equivalent circuit model of on-wafer CMOS interconnects for RFICs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
26	Eun Jung Kim 0001, Greg M. Link, Ki Hwan Yum, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Chita R. Das	A Holistic Approach to Designing Energy-Efficient Cluster Interconnects.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Buffer design, cluster interconnect, dynamic link shutdown, link design, dynamic voltage scaling, energy optimization, switch design
26	Bing Zhong, Tao Hu, Dawei Fu, Steven L. Dvorak, John L. Prince	A study of a hybrid phase-pole macromodel for transient simulation of complex interconnects structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
26	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-independent testing of FPGA interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
26	Medha Kulkarni, Tom Chen 0001	A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
26	Valeriy Sukharev	Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
26	Hao Yu 0001, Lei He 0001	A provably passive and cost-efficient model for inductive interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
26	Wichian Sirisaengtaksin, Sandeep K. Gupta 0001	A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
26	Rod Fatoohi, Ken Kardys, Sumy Koshy, Soundarya Sivaramakrishnan, Jeffrey S. Vetter	Performance Evaluation of High-Speed Interconnects Using Dense Communication Patterns.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
26	Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla	Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
26	Youngsoo Shin, Hyung-Ock Kim	Analysis of power consumption in VLSI global interconnects.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
26	Parthasarathi Dasgupta	Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions.	VLSI Design	2005	DBLP DOI BibTeX RDF
26	Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar	A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
26	Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani	Testing SoC interconnects for signal integrity using extended JTAG architecture.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
26	Xiaoliang Bai, Sujit Dey	High-level crosstalk defect Simulation methodology for system-on-chip interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
26	Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, André Ivanov	Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
26	Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang	Realizable parasitic reduction for distributed interconnects using matrix pencil technique.	ASP-DAC	2004	DBLP DOI BibTeX RDF
26	Manhee Lee, Eun Jung Kim 0001, Cheol Won Lee	A Source Identification Scheme against DDoS Attacks in Cluster Interconnects.	ICPP Workshops	2004	DBLP DOI BibTeX RDF
26	Vishak Venkatraman, Atul Maheshwari, Wayne P. Burleson	Mitigating static power in current-sensed interconnects.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	interconnect circuits, static power, self-timed systems
26	Syed M. Alam, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel	Circuit Level Reliability Analysis of Cu Interconnects.	ISQED	2004	DBLP DOI BibTeX RDF
26	John W. Lockwood	Guest Editor's Introduction: Hot Interconnects 10--Thinking beyond the Internet.	IEEE Micro	2003	DBLP DOI BibTeX RDF
26	Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III	Current-mode signaling in deep submicrometer global interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
26	Razak Hossain, Fabrizio Viglione, Marco Cavalli	Designing fast on-chip interconnects for deep submicrometer technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
26	Pasquale Cocchini	A methodology for optimal repeater insertion in pipelined interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
26	Gregorio Cappuccino	Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects.	DSD	2003	DBLP DOI BibTeX RDF
26	Christian Kurmann, Felix Rauch, Thomas Stricker	Cost/Performance Tradeoffs in Network Interconnects for Clusters of Commodity PCs.	IPDPS	2003	DBLP DOI BibTeX RDF	Clusters of commodity PCs, switch performance, full bisection bandwidth, Ethernet, Myrinet, all-to-all communication, application performance
26	Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III	Accurate delay model and experimental verification for current/voltage mode on-chip interconnects.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
26	Yoshihiro Yamagami, Yoshifumi Nishio, Atsumi Hattori, Akio Ushida	A reduction technique of large scale RCG interconnects in complex frequency domain.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
26	Guoan Zhong, Cheng-Kok Koh	Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects.	ICCD	2002	DBLP DOI BibTeX RDF
26	Qinwei Xu, Pinaki Mazumder, Li Ding 0002	Novel macromodeling for on-chip RC/RLC interconnects.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
26	Falah R. Awwad, Mohamed Nekili	Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	parallel regeneration, VLSI, repeater, RLC interconnect
26	Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi	Incremental Diagnosis of Multiple Open-Interconnects.	ITC	2002	DBLP DOI BibTeX RDF
26	Qinwei Xu, Pinaki Mazumder	Rational ABCD Modeling of High-Speed Interconnects.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
26	P. K. Datta, S. Sanyal, D. Bhattacharya	Losses in Multilevel Crossover in VLSI Interconnects.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
26	Youxin Gao, D. F. Wong 0001	A fast and accurate delay estimation method for buffered interconnects.	ASP-DAC	2001	DBLP DOI BibTeX RDF
26	Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl	Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
26	Tong Liu 0007, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi	Test generation and scheduling for layout-based detection of bridge faults in interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
26	Arani Sinha, Sandeep K. Gupta 0001, Melvin A. Breuer	Validation and test generation for oscillatory noise in VLSI interconnects.	ICCAD	1999	DBLP DOI BibTeX RDF
26	Satrajit Gupta, Lalit M. Patnaik	Exact Output Response Computation of RC Interconnects under Polynomial Input Waveforms.	VLSI Design	1999	DBLP DOI BibTeX RDF
26	Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang	Full-wave analysis of high-speed interconnects using complex frequency hopping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
26	Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu	Optimal diagnostic methods for wiring interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF