Search results for "single-event"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Johan Karlsson, Ulf Gunneflo, Jan Torin	The Effects of Heavy-Ion Induced Single Event Upsets in the MC6809E Microprocessor.	Fehlertolerierende Rechensysteme	1989	DBLP DOI BibTeX RDF
9	Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker 0001	On Reducing Circuit Malfunctions Caused by Soft Errors.	DFT	2008	DBLP DOI BibTeX RDF
9	Luca Sterpone, Massimo Violante	Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.	ETS	2007	DBLP DOI BibTeX RDF
9	Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi	Error Tolerance of DNA Self-Healing Assemblies by Puncturing.	DFT	2007	DBLP DOI BibTeX RDF
9	Liang Wang 0024, Suge Yue, Yuanfu Zhao, Long Fan	An SEU-Tolerant Programmable Frequency Divider.	ISQED	2007	DBLP DOI BibTeX RDF
9	Sara Adams, Joël Ouaknine, James Worrell 0001	Undecidability of Universality for Timed Automata with Minimal Resources.	FORMATS	2007	DBLP DOI BibTeX RDF
9	Bernhard Fechner	Analysis of checksum-based execution schemes for pipelined processors.	IPDPS	2006	DBLP DOI BibTeX RDF
9	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis 0001	Design of a Robust 8-Bit Microprocessor to Soft Errors.	IOLTS	2006	DBLP DOI BibTeX RDF
9	Bin Zhang 0011, Wei-Shen Wang, Michael Orshansky	FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs.	ISQED	2006	DBLP DOI BibTeX RDF
9	Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil	Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
9	Nicolas Renaud	How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family.	IOLTS	2005	DBLP DOI BibTeX RDF
9	Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert	Evaluation of SET and SEU Effects at Multiple Abstraction Levels.	IOLTS	2005	DBLP DOI BibTeX RDF
9	Thara Rejimon, Sanjukta Bhanja	An Accurate Probalistic Model for Error Detection.	VLSI Design	2005	DBLP DOI BibTeX RDF
9	Michael Nicolaidis, Yervant Zorian	Scaling Deeper to Submicron: On-Line Testing to the Rescue.	DATE	1999	DBLP DOI BibTeX RDF
8	Umut A. Acar, Guy E. Blelloch, Kanat Tangwongsan, Duru Türkoglu	Robust Kinetic Convex Hulls in 3D.	ESA	2008	DBLP DOI BibTeX RDF
8	Arash Nasiri Eghbali, Hadi Sanjani, Mehdi Dehghan 0001	ODCP: An On-Demand Clustering Protocol for Directed Diffusion.	ADHOC-NOW	2007	DBLP DOI BibTeX RDF	on-demand clustering, Wireless sensor networks, energy efficiency, directed diffusion
8	Prarthana Shrestha, Mauro Barbieri, Hans Weda	Synchronization of multi-camera video recordings based on audio.	ACM Multimedia	2007	DBLP DOI BibTeX RDF	video synchronization, audio classification, audio fingerprinting
8	Peter M. Fischer 0001, Donald Kossmann	Quality of service in stateful information filters.	DMSN	2006	DBLP DOI BibTeX RDF
8	Jean-Raymond Abrial, Dominique Cansell, Dominique Méry	A Mechanically Proved and Incremental Development of IEEE 1394 Tree Identify Protocol.	Formal Aspects Comput.	2003	DBLP DOI BibTeX RDF	Proof-based development, Proof engine, Refinement, B method, Abstract model, Event-driven approach
8	Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante	Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
6	Avijit Dutta, Nur A. Touba	Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code.	VTS	2007	DBLP DOI BibTeX RDF
6	Vilas Sridharan, Hossein Asadi 0001, Mehdi Baradaran Tahoori, David R. Kaeli	Reducing Data Cache Susceptibility to Soft Errors.	IEEE Trans. Dependable Secur. Comput.	2006	DBLP DOI BibTeX RDF	refresh, refetch, Fault tolerance, reliability, cache memories, soft errors, error modeling
6	T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani	SEU Mitigation Techniques for Microprocessor Control Logic.	EDCC	2006	DBLP DOI BibTeX RDF
6	Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar	Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic.	ISQED	2006	DBLP DOI BibTeX RDF
6	Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss 0001	A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	instruction queue, reliability, error correcting codes
6	Jonny Vinter, Olof Hannius, Torbjörn Norlander, Peter Folkesson, Johan Karlsson	Experimental Dependability Evaluation of a Fail-Bounded Jet Engine Control System for Unmanned Aerial Vehicles.	DSN	2005	DBLP DOI BibTeX RDF
6	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.	IPDPS	2005	DBLP DOI BibTeX RDF
6	Nicholas J. Wang, Justin Quek, Todd M. Rafacz, Sanjay J. Patel	Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline.	DSN	2004	DBLP DOI BibTeX RDF
6	Luca Schiano, Marco Ottavi, Fabrizio Lombardi	Markov Models of Fault-Tolerant Memory Systems under SEU.	MTDT	2004	DBLP DOI BibTeX RDF
6	Daniel Mossé, Rami G. Melhem, Sunondo Ghosh	A Nonpreemptive Real-Time Scheduler with Recovery from Transient Faults and Its Implementation.	IEEE Trans. Software Eng.	2003	DBLP DOI BibTeX RDF	scheduling, Fault tolerance, real-time, operating system, transient faults
6	Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin	A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor.	MICRO	2003	DBLP DOI BibTeX RDF
6	Lucja Iwanska, Douglas E. Appelt, Damaris M. Ayuso, Kathy Dahlgren, Bonnie Glover Stalls, Ralph Grishman, George R. Krupka, Christine A. Montgomery, Ellen Riloff	Computational aspects of discourse in the context of MUC-3.	MUC	1991	DBLP DOI BibTeX RDF
5	Jonathan M. Johnson, Michael J. Wirthlin	Voter insertion algorithms for FPGA designs using triple modular redundancy.	FPGA	2010	DBLP DOI BibTeX RDF	scc, tmr, voter insertion, fpga, algorithm, reliability, synchronization
5	Xin He, Afshin Abdollahi	Cost aware fault tolerant logic synthesis in presence of soft errors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	soft error rate, reliability, linear programming
5	Manu Jose, Yu Hu 0002, Rupak Majumdar, Lei He 0001	Rewiring for robustness.	DAC	2010	DBLP DOI BibTeX RDF	SPFD, FPGA, logic synthesis, soft errors, rewiring
5	Rajesh Garg, Sunil P. Khatri	Efficient analytical determination of the SEU-induced pulse shape.	ASP-DAC	2009	DBLP DOI BibTeX RDF
5	Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi	Memory Sharing Approach for TMR Softcore Processor.	ARC	2009	DBLP DOI BibTeX RDF
5	Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi	SEU hardened clock regeneration circuits.	ISQED	2009	DBLP DOI BibTeX RDF
5	Jieh-Shan Yeh, Szu-Chen Lin	A new data structure for asynchronous periodic pattern mining.	ICUIMC	2009	DBLP DOI BibTeX RDF	asynchronous sequence, data mining, periodic pattern
5	Kuande Wang, Li Chen, Jinsheng Yang	AN ultra low power fault tolerant SRAM design in 90nm CMOS.	CCECE	2009	DBLP DOI BibTeX RDF
5	Fan Wang, Vishwani D. Agrawal	Soft Error Rates with Inertial and Logical Masking.	VLSI Design	2009	DBLP DOI BibTeX RDF
5	Sobeeh Almukhaizim, Yiorgos Makris	Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires.	IEEE Trans. Reliab.	2008	DBLP DOI BibTeX RDF
5	Saihua Lin, Huazhong Yang, Rong Luo	A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
5	Chong Zhao, Yi Zhao, Sujit Dey	Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
5	Pankaj K. Agarwal, Haim Kaplan, Micha Sharir	Kinetic and dynamic data structures for closest pair and all nearest neighbors.	ACM Trans. Algorithms	2008	DBLP DOI BibTeX RDF	computational geometry, nearest neighbors, Kinetic data structures, closest pair
5	Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh	General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
5	Egas Henes Neto, Gilson I. Wirth, Fernanda Lima Kastensmidt	Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Fault-tolerance, Reliability, Testing, Built-in tests, Error-checking
5	Kapil Kumar Gupta, Baikunth Nath, Kotagiri Ramamohanarao	User Session Modeling for Effective Application Intrusion Detection.	SEC	2008	DBLP DOI BibTeX RDF
5	Biwei Liu, Shuming Chen	Fast and Accurate Estimate SET Voltage Pulses from Transient Currents Induced by Heavy Ion.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	voltage pulse, radiation effect, SET
5	Alexander I. Fedoseyev, Marek Turowski, Ashok Raman, Michael L. Alles, Robert A. Weller	Multiscale Numerical Models for Simulation of Radiation Events in Semiconductor Devices.	ICCS (2)	2008	DBLP DOI BibTeX RDF	Nanoscale device, radiation event, nuclear reaction, 3D transient simulation, 3D adaptive mesh generation, drift-diffusion, computer-aided-design, multiscale, finite volume method, hydrodynamics
5	Kaushal R. Gandhi, Nihar R. Mahapatra	Partitioned reuse cache for energy-efficient soft-error protection of functional units.	SoCC	2008	DBLP DOI BibTeX RDF
5	Srivathsan Krishnamohan, Nihar R. Mahapatra	Slack redistribution in pipelined circuits for enhanced soft-error rate reduction.	SoCC	2008	DBLP DOI BibTeX RDF
5	Drew C. Ness, David J. Lilja	Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	fault distribution, reliability analysis, SEU, SER
5	Rui Gong, Kui Dai, Zhiying Wang 0003	A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
5	Cristiana Bolchini, Antonio Miele	Design Space Exploration for the Design of Reliable.	DFT	2008	DBLP DOI BibTeX RDF
5	Mahdi Fazeli, Seyed Ghassem Miremadi	A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET.	DFT	2008	DBLP DOI BibTeX RDF
5	Vinay Jain, Payman Zarkesh-Ha	Analytical Noise-Rejection Model Based on Short Channel MOSFET.	ISQED	2008	DBLP DOI BibTeX RDF
5	Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sarrafzadeh	Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems.	ISQED	2008	DBLP DOI BibTeX RDF
5	Rui Gong, Kui Dai, Zhiying Wang 0003	Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
5	Juan Antonio Maestro, Pedro Reviriego	Study of the effects of MBUs on the reliability of a 150 nm SRAM device.	DAC	2008	DBLP DOI BibTeX RDF	multiple bit upsets (MBUs), reliability, memory, radiation
5	Sobeeh Almukhaizim, Yiorgos Makris	Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	asynchronous burst-mode machines, error-detecting codes, Concurrent error detection, Berger code
5	Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro	Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	reliability, fault tolerant systems, SEU, SRAM-based FPGA
5	Mahdi Fazeli, Ahmad Patooghy, Seyed Ghassem Miremadi, Alireza Ejlali	Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.	DSN	2007	DBLP DOI BibTeX RDF
5	Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh	Soft Error-Aware Power Optimization Using Gate Sizing.	PATMOS	2007	DBLP DOI BibTeX RDF
5	Saihua Lin, Huazhong Yang, Rong Luo	High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit.	ISVLSI	2007	DBLP DOI BibTeX RDF
5	Bernhard Fechner, Andre Osterloh	Transient Fault Detection in State-Automata.	DepCoS-RELCOMEX	2007	DBLP DOI BibTeX RDF
5	Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel	RIC Fast Adder and its Set Tolerant Implementation in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
5	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan	Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
5	Franz X. Ruckerbauer, Georg Georgakos	Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena.	IOLTS	2007	DBLP DOI BibTeX RDF	NSER, ASER, multi-bit upset, soft errors and radiation, CMOS, SRAM, SEU
5	Michel Pignol	Methodology and Tools Developed for Validation of COTS-based Fault-Tolerant Spacecraft Supercomputers.	IOLTS	2007	DBLP DOI BibTeX RDF
5	Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio	SEU mitigation for sram-based fpgas through dynamic partial reconfiguration.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault detection, SEU, partial dynamic reconfiguration
5	Haruhiko Kaneko, Eiji Fujiwara	Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks.	DFT	2007	DBLP DOI BibTeX RDF
5	Swapnil Bahl	A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema.	DFT	2007	DBLP DOI BibTeX RDF
5	Helia Naeimi, André DeHon	Fault Secure Encoder and Decoder for Memory Applications.	DFT	2007	DBLP DOI BibTeX RDF
5	Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty	A TMR Scheme for SEU Mitigation in Scan Flip-Flops.	ISQED	2007	DBLP DOI BibTeX RDF
5	Yanxia Wu, Guochang Gu, Shaobin Huang, Jun Ni	Control Flow Checking Algorithm using Soft-based Intra-/Inter-block Assigned-Signature.	IMSCCS	2007	DBLP DOI BibTeX RDF
5	Lianlian Zeng, Paul Beckett	Soft Error Rate Estimation in Deep Sub-micron CMOS.	PRDC	2007	DBLP DOI BibTeX RDF
5	Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Reliability, redundancy, Markov random fields, noise immunity, probabilistic computing
5	Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi	Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
5	Byonghyo Shim, Naresh R. Shanbhag	Energy-efficient soft error-tolerant digital signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
5	Luca Sterpone, Massimo Violante	A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	transient fault injection, FPGA, reliability, place and route
5	Quming Zhou, Kartik Mohanram	Gate sizing to radiation harden combinational logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
5	Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das	Exploring Fault-Tolerant Network-on-Chip Architectures.	DSN	2006	DBLP DOI BibTeX RDF
5	Mohamed Abbas, Makoto Ikeda, Kunihiro Asada	On-chip 8GHz non-periodic high-swing noise detector.	DATE	2006	DBLP DOI BibTeX RDF
5	Todd M. Austin	Robust low power computing in the nanoscale era.	SBCCI	2006	DBLP DOI BibTeX RDF
5	Bernhard Fechner	A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments.	PARELEC	2006	DBLP DOI BibTeX RDF
5	Riaz Naseer, Jeff Draper	DF-DICE: a scalable solution for soft error tolerant circuit design.	ISCAS	2006	DBLP DOI BibTeX RDF
5	Michel Pignol	DMT and DT2: Two Fault-Tolerant Architectures developed by CNES for COTs-based Spacecraft Supercomputers.	IOLTS	2006	DBLP DOI BibTeX RDF
5	Maico Cassel, Fernanda Lima Kastensmidt	Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
5	Arthur Pereira Frantz, Luigi Carro, Érika F. Cota, Fernanda Lima Kastensmidt	Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers.	IOLTS	2006	DBLP DOI BibTeX RDF
5	Guillaume Hubert, Antonin Bougerol, Florent Miller, Nadine Buard, Lorena Anghel, Thierry Carrière, Frederic Wrobel, Rémi Gaillard	Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells.	IOLTS	2006	DBLP DOI BibTeX RDF
5	Marco Ottavi, Salvatore Pontarelli, A. Leandri, Adelio Salsano	Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers.	DFT	2006	DBLP DOI BibTeX RDF
5	Vivek Joshi, Rajeev R. Rao, David T. Blaauw, Dennis Sylvester	Logic SER Reduction through Flipflop Redesign.	ISQED	2006	DBLP DOI BibTeX RDF
5	Chong Zhao, Sujit Dey	Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO).	ISQED	2006	DBLP DOI BibTeX RDF
5	Navid Azizi, Farid N. Najm	A family of cells to reduce the soft-error-rate in ternary-CAM.	DAC	2006	DBLP DOI BibTeX RDF	soft-error rate, content-addressable memory
5	Anurag Tiwari, Karen A. Tomko	Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction.	IEEE Trans. Reliab.	2005	DBLP DOI BibTeX RDF
5	Ceyhun Burak Akgül, Bülent Sankur, Ata Akin	Spectral Analysis of Event-Related Hemodynamic Responses in Functional Near Infrared Spectroscopy.	J. Comput. Neurosci.	2005	DBLP DOI BibTeX RDF	cerebrovascular dynamics, time-frequency distribution, oscillary brain dynamics, near infrared spectroscopy
5	Cung Nguyen, G. Robert Redinbo	Fault Tolerance Design in JPEG 2000 Image Compression System.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	Fault-tolerant source coding, JPEG 2000 standard, hardware reliability, weighted sum parity, data compression, Discrete Wavelet Transform (DWT), Soft errors, concurrent error detection, Huffman coding, error control codes, algorithm-based fault tolerance, error-checking
5	Srivathsan Krishnamohan, Nihar R. Mahapatra	Combining Error Masking and Error Detection Plus Recovery to Combat Soft Errors in Static CMOS Circuits.	DSN	2005	DBLP DOI BibTeX RDF
5	Ghazanfar Asadi, Mehdi Baradaran Tahoori	Soft error rate estimation and mitigation for SRAM-based FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	soft error rate estimation, error recovery, SRAM-based FPGA