Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
12 | Subhomoy Chattopadhyay |
Low power design techniques for nanometer design processes: 65 nm and smaller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 5, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
65 nm, low power, embedded design |
12 | Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari |
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 67-74, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing |
12 | Zhiyu Liu, Volkan Kursun |
High Read Stability and Low Leakage Cache Memory Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2774-2777, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Bernabé Linares-Barranco, Teresa Serrano-Gotarredona |
A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1561-1564, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Jaume Abella 0001, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González 0001 |
Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 15-22, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Senthil Kumar Lakshmanan, Peter Tawdross, Andreas König 0001 |
Towards Generic On-the-Fly Reconfigurable Sensor Electronics for Embedded System- First Measurement Results of Reconfigurable Folded. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 379-384, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Subhomoy Chattopadhyay, Rakesh Patel |
Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 5, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Kiran Puttaswamy, Gabriel H. Loh |
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 622-625, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001 |
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 823-828, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Robert J. Bonneau, George O. Ramseyer, Tom Renz, Claire Thiem |
A Mathematical Architecture for Molecular Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AIPR ![In: 36th Applied Imagery Pattern Recognition Workshop, AIPR 2007, Washington, DC, USA, October 10-12, 2007, Proceedings, pp. 80-86, 2007, IEEE Computer Society, 978-0-7695-3066-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
molecular computing |
12 | Ilya Obridko, Ran Ginosar |
Minimal Energy Asynchronous Dynamic Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(9), pp. 1043-1047, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman |
Extraction error modeling and automated model debugging in high-performance custom designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(7), pp. 763-776, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Eric W. MacDonald, Nur A. Touba |
Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(6), pp. 587-595, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum |
Compact modeling of on-chip ESD protection devices using Verilog-A. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6), pp. 1047-1063, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Imad A. Ferzli, Farid N. Najm |
Analysis and verification of power grids considering process-induced leakage-current variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1), pp. 126-143, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Nian Zhang, Donald C. Wunsch II |
Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Fuzzy Syst. ![In: IEEE Trans. Fuzzy Syst. 14(6), pp. 728-737, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Dmitri B. Strukov, Konstantin K. Likharev |
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 131-140, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
integrated hybrid circuits, architecture, programmable logic, nanoelectronics, programmable interconnect |
12 | Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong |
Performance benefits of monolithically stacked 3D-FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 113-122, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
3D monolithically stacked, FPGA, performance analysis |
12 | Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang 0011, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky |
BulletProof: a defect-tolerant CMP switch architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006, pp. 5-16, 2006, IEEE Computer Society, 0-7803-9368-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Yavuz Cengiz, Hüseyin Göksu, Filiz Günes |
Design of a Broadband Microwave Amplifier Using Neural Performance Data Sheets and Very Fast Simulated Reannealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28 - June 1, 2006, Proceedings, Part III, pp. 815-820, 2006, Springer, 3-540-34482-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Elias Kougianos, Saraju P. Mohanty |
Effective tunneling capacitance: a new metric to quantify transient gate leakage current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Erhan Ozalevli, Paul E. Hasler |
A tunable floating gate CMOS resistor for low-power and low-voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho |
A high speed and energy efficient full adder design using complementary & level restoring carry logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Alexandre J. Aragão, João Navarro Jr., Wilhelmus A. M. Van Noije |
Mismatch effect analyses in CMOS tapered buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | David G. Haigh |
Analytic approach to or transformations for FET circuit synthesis. Part I. Nullator-norator tree transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Zheng Yang 0004, Viktor Gruev, Jan Van der Spiegel |
A CMOS linear voltage/current dual-mode imager. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Magdy S. Abadir |
Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 81, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Zhiyu Liu, Volkan Kursun |
Leakage current starved domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 428-433, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage |
12 | Victor Moroz, Lee Smith, Xi-Wei Lin, Dipu Pramanik, Greg Rollins |
Stress-Aware Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 807-812, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Chung-Kuan Tsai, Malgorzata Marek-Sadowska |
Analysis of Process Variation's Effect on SRAM's Read Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 603-610, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Hayssam El-Razouk, Zine Abid |
Area and Power Efficient Array and Tree Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 713-716, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Yunfeng Peng, Derui Kong, Feng Zhou |
A Low-Voltage Sampling Switch with Improved Linearity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1706-1709, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Fang Liu 0029, Plamen K. Nikolov, Sule Ozev |
Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 272-277, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Reddy Kotha, Kunul Gottimukkula, M. B. Srinivas |
Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 414-417, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Masanori Hariyama, Michitaka Kameyama |
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1803-1806, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Kwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen |
Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1476-1479, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Saurabh Singh, K. Radhakrishna Rao |
Low Voltage Analogue Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1772-1775, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh |
Timing driven power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 121-124, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
leakage current, power gating, IR drop |
12 | Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar |
Gate oxide leakage and delay tradeoffs for dual-Tox circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(12), pp. 1362-1375, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Shrirang K. Karandikar, Sachin S. Sapatnekar |
Fast comparisons of circuit implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(12), pp. 1329-1339, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy 0001 |
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1286-1295, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang |
A review of 0.18-μm full adder performances for tree structured arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 686-695, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001 |
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3), pp. 363-381, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 446-455, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 436-445, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Minoru Watanabe, Fuminori Kobayashi |
An Improved Dynamic Optically Reconfigurable Gate Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 136-141, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy 0001 |
Statistical Timing Analysis using Levelized Covariance Propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 764-769, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa |
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 646-647, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
Low-power domino circuits using NMOS pull-up on off-critical paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 533-538, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie 0001 |
Low-leakage robust SRAM cell design for sub-100nm technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 539-544, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Leonardo Barboni, Rafaella Fiorelli |
Design and power optimization of CMOS RF blocks operating in the moderate inversion region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 127-132, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
amplifier design, radio frequency integrated circuits, CMOS integrated circuits, power optimization |
12 | Paul L. Jespers |
A design methodology for analogue CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 2, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Youngmoon Choi, Earl E. Swartzlander Jr. |
Parallel Prefix Adder Design with Matrix Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 90-98, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Dennis Buss |
Technology and design challenges for mobile communication and computing products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 1, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King 0001, Borivoje Nikolic |
FinFET-based SRAM design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 2-7, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
double gate transistors, low power, memory, SRAM |
12 | Stephan Henzler, Thomas Nirschl, Matthias Eireiner, Ettore Amirante, Doris Schmitt-Landsiedel |
Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 414-420, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
adiabatic logic, adiabatic mode logic, cross coupled domino, dynamic power reduction, low-power design styles |
12 | Antti Heiskanen, Timo Rahkonen |
Comparison of two class E amplifiers for EER transmitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 704-707, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler |
Indirect programming of floating-gate transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2172-2175, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Gerard Villar, Eduard Alarcón, Jordi Madrenas, Francesc Guinjoan, Alberto Poveda |
Energy optimization of tapered buffers for CMOS on-chip switching power converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4453-4456, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Vadim Ivanov, Igor M. Filanovsky |
A 110 dB CMRR/PSRR/gain CMOS operational amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1561-1564, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Cristiano Santos, Daniel Lima Ferrão, Ricardo Reis 0001, José Luís Güntzel |
Incremental timing optimization for automatic layout generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3567-3570, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Daniel Fernández, Gerard Villar, Eva Vidal, Eduard Alarcón, Jordi Cosp, Jordi Madrenas |
Mismatch-tolerant CMOS oscillator and excitatory synapse for bioinspired image segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4114-4117, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Martin Omaña 0001, O. Losco, Cecilia Metra, Andrea Pagni |
On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 163-168, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Amir Fijany, Farrokh Vatan, Mohammad M. Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil |
The G4-FET: a universal and programmable logic gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 349-352, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
G4-FET, programmable gate, universal logic gate, full adder |
12 | Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi |
A high speed and leakage-tolerant domino logic for high fan-in gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 478-481, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high speed, noise immunity, deep submicron, fan-in, domino |
12 | Cory Jung, Mohammad Hadi Izadi, Michelle L. La Haye |
Noise Analysis of Fault Tolerant Active Pixel Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 140-148, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Yuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk |
Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 476-481, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally |
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, November 12-18, 2005, Seattle, WA, USA, CD-Rom, pp. 29, 2005, IEEE Computer Society, 1-59593-061-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Ramaprasath Vilangudipitchai, Poras T. Balsara |
Power Switch Network Design for MTCMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 836-839, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Sergei P. Skorobogatov |
Data Remanence in Flash Memory Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 339-353, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Hiran Tennakoon, Carl Sechen |
Efficient and accurate gate sizing with piecewise convex delay models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 807-812, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
piecewise convex, optimization, Lagrangian relaxation, gate sizing, delay modeling |
12 | Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato |
A leakage-energy-reduction technique for highly-associative caches in embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 32(3), pp. 50-54, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cache memories, embedded processors, leakage current |
12 | Saul Rosen |
Recollections of the Philco Transac S-2000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Ann. Hist. Comput. ![In: IEEE Ann. Hist. Comput. 26(2), pp. 34-47, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Arifur Rahman, Vijay Polavarapuv |
Evaluation of low-leakage design techniques for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 23-30, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, leakage power, multiplexer |
12 | Hidenori Sato, Toshinori Sato |
A static and dynamic energy reduction technique for I-cache and BTB in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 830-833, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Binu K. Mathew, Al Davis |
A loop accelerator for low power embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 6-11, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
embedded systems, low power design, VLIW |
12 | Kalle Ruttik |
BER for CMOS Analog Decoder with Different Working Points. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICT ![In: Telecommunications and Networking - ICT 2004, 11th International Conference on Telecommunications, Fortaleza, Brazil, August 1-6, 2004, Proceedings, pp. 885-890, 2004, Springer, 3-540-22571-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Alexandre Schmid, Yusuf Leblebici |
Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 685-688, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Seiichiro Fujii, Toshinori Sato |
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings, pp. 217-226, 2004, Springer, 3-540-22906-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Amir Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz |
Leakage current reduction by new technique in standby mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 158-161, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
subthreshold current, low power, leakage current, digital integrated circuits, static power |
12 | Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek |
Low energy FPGA interconnect design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 393-396, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, low power, interconnect, encoding |
12 | Jörg Langeheine, Karlheinz Meier, Johannes Schemmel, Martin Trefzer |
Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 24-26 June 2004, Seattle, WA, USA, pp. 18-25, 2004, IEEE Computer Society, 0-7695-2145-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Rohini Krishnan, José Pineda de Gyvez |
Low Energy Switch Block For FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 209-214, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Modeling and Estimation of Leakage in Sub-90nm Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 65-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Volkan Kursun, Eby G. Friedman |
Domino logic with variable threshold voltage keeper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 1080-1093, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Li Ding 0002, Pinaki Mazumder |
Simultaneous switching noise analysis using application specific device modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 1146-1152, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins, Vivek De |
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(5), pp. 863-870, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
Hierarchical whitespace allocation in top-down placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11), pp. 1550-1556, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Stephen H. Unger |
Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(6), pp. 18-24, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Akihito Sakanaka, Toshinori Sato |
Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 530-539, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra |
Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 62-69, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Alessandro Girardi, Sergio Bampi |
LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11106-11107, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi |
Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 311-316, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Stanislav Sedukhin, Mostafa I. Soliman |
Trident: Technology-Scalable Architecture for Data Parallel Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 264, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scalar/vector/matrix processing, data parallel applications, scalable architecture, BLAS |
12 | Snorre Aunet, Morten Hartmann |
Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 5th International Conference, ICES 2003, Trondheim, Norway, March 17-20, 2003, Proceedings, pp. 365-376, 2003, Springer, 3-540-00730-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Ricardo Salem Zebulum, Adrian Stoica, Didier Keymeulen, Michael I. Ferguson, Vu Duong, Xin Guo 0002, Vatche Vorperian |
Automatic Evolution of Signal Separators Using Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 5th International Conference, ICES 2003, Trondheim, Norway, March 17-20, 2003, Proceedings, pp. 286-295, 2003, Springer, 3-540-00730-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Patricia Giacomelli, Márcio C. Schneider, Carlos Galup-Montoro |
MOSVIEW: A Graphical Tool for MOS Analog Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 43-44, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Mohan G. Kabadi, Ranjani Parthasarathi |
Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 337-351, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Abhishek Singh 0001, Jitin Tharian, Jim Plusquellic |
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 748-753, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Lei Yang 0019, C.-J. Richard Shi |
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 741-747, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|