Search results for "transistor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Subhomoy Chattopadhyay	Low power design techniques for nanometer design processes: 65 nm and smaller.	SBCCI	2007	DBLP DOI BibTeX RDF	65 nm, low power, embedded design
12	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
12	Zhiyu Liu, Volkan Kursun	High Read Stability and Low Leakage Cache Memory Cell.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Bernabé Linares-Barranco, Teresa Serrano-Gotarredona	A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Jaume Abella 0001, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González 0001	Fuse: A Technique to Anticipate Failures due to Degradation in ALUs.	IOLTS	2007	DBLP DOI BibTeX RDF
12	Senthil Kumar Lakshmanan, Peter Tawdross, Andreas König 0001	Towards Generic On-the-Fly Reconfigurable Sensor Electronics for Embedded System- First Measurement Results of Reconfigurable Folded.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Subhomoy Chattopadhyay, Rakesh Patel	Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Kiran Puttaswamy, Gabriel H. Loh	Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors.	DAC	2007	DBLP DOI BibTeX RDF
12	Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001	Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.	DAC	2007	DBLP DOI BibTeX RDF
12	Robert J. Bonneau, George O. Ramseyer, Tom Renz, Claire Thiem	A Mathematical Architecture for Molecular Computing.	AIPR	2007	DBLP DOI BibTeX RDF	molecular computing
12	Ilya Obridko, Ran Ginosar	Minimal Energy Asynchronous Dynamic Adders.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman	Extraction error modeling and automated model debugging in high-performance custom designs.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Eric W. MacDonald, Nur A. Touba	Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum	Compact modeling of on-chip ESD protection devices using Verilog-A.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
12	Imad A. Ferzli, Farid N. Najm	Analysis and verification of power grids considering process-induced leakage-current variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
12	Nian Zhang, Donald C. Wunsch II	Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach.	IEEE Trans. Fuzzy Syst.	2006	DBLP DOI BibTeX RDF
12	Dmitri B. Strukov, Konstantin K. Likharev	A reconfigurable architecture for hybrid CMOS/Nanodevice circuits.	FPGA	2006	DBLP DOI BibTeX RDF	integrated hybrid circuits, architecture, programmable logic, nanoelectronics, programmable interconnect
12	Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong	Performance benefits of monolithically stacked 3D-FPGA.	FPGA	2006	DBLP DOI BibTeX RDF	3D monolithically stacked, FPGA, performance analysis
12	Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang 0011, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky	BulletProof: a defect-tolerant CMP switch architecture.	HPCA	2006	DBLP DOI BibTeX RDF
12	Yavuz Cengiz, Hüseyin Göksu, Filiz Günes	Design of a Broadband Microwave Amplifier Using Neural Performance Data Sheets and Very Fast Simulated Reannealing.	ISNN (2)	2006	DBLP DOI BibTeX RDF
12	Elias Kougianos, Saraju P. Mohanty	Effective tunneling capacitance: a new metric to quantify transient gate leakage current.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Erhan Ozalevli, Paul E. Hasler	A tunable floating gate CMOS resistor for low-power and low-voltage applications.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho	A high speed and energy efficient full adder design using complementary & level restoring carry logic.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Alexandre J. Aragão, João Navarro Jr., Wilhelmus A. M. Van Noije	Mismatch effect analyses in CMOS tapered buffers.	ISCAS	2006	DBLP DOI BibTeX RDF
12	David G. Haigh	Analytic approach to or transformations for FET circuit synthesis. Part I. Nullator-norator tree transformations.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Zheng Yang 0004, Viktor Gruev, Jan Van der Spiegel	A CMOS linear voltage/current dual-mode imager.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Magdy S. Abadir	Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs.	IOLTS	2006	DBLP DOI BibTeX RDF
12	Zhiyu Liu, Volkan Kursun	Leakage current starved domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage
12	Victor Moroz, Lee Smith, Xi-Wei Lin, Dipu Pramanik, Greg Rollins	Stress-Aware Design Methodology.	ISQED	2006	DBLP DOI BibTeX RDF
12	Chung-Kuan Tsai, Malgorzata Marek-Sadowska	Analysis of Process Variation's Effect on SRAM's Read Stability.	ISQED	2006	DBLP DOI BibTeX RDF
12	Hayssam El-Razouk, Zine Abid	Area and Power Efficient Array and Tree Multipliers.	CCECE	2006	DBLP DOI BibTeX RDF
12	Yunfeng Peng, Derui Kong, Feng Zhou	A Low-Voltage Sampling Switch with Improved Linearity.	CCECE	2006	DBLP DOI BibTeX RDF
12	Fang Liu 0029, Plamen K. Nikolov, Sule Ozev	Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework.	VTS	2006	DBLP DOI BibTeX RDF
12	Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Reddy Kotha, Kunul Gottimukkula, M. B. Srinivas	Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.	DELTA	2006	DBLP DOI BibTeX RDF
12	Masanori Hariyama, Michitaka Kameyama	A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment.	APCCAS	2006	DBLP DOI BibTeX RDF
12	Kwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen	Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process.	APCCAS	2006	DBLP DOI BibTeX RDF
12	Saurabh Singh, K. Radhakrishna Rao	Low Voltage Analogue Multiplier.	APCCAS	2006	DBLP DOI BibTeX RDF
12	De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh	Timing driven power gating.	DAC	2006	DBLP DOI BibTeX RDF	leakage current, power gating, IR drop
12	Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar	Gate oxide leakage and delay tradeoffs for dual-Tox circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
12	Shrirang K. Karandikar, Sachin S. Sapatnekar	Fast comparisons of circuit implementations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
12	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy 0001	Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
12	Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang	A review of 0.18-μm full adder performances for tree structured arithmetic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
12	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001	Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
12	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
12	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Design of Variable Input Delay Gates for Low Dynamic Power Circuits.	PATMOS	2005	DBLP DOI BibTeX RDF
12	Minoru Watanabe, Fuminori Kobayashi	An Improved Dynamic Optically Reconfigurable Gate Array.	ISVLSI	2005	DBLP DOI BibTeX RDF
12	Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy 0001	Statistical Timing Analysis using Levelized Covariance Propagation.	DATE	2005	DBLP DOI BibTeX RDF
12	Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa	Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction.	DATE	2005	DBLP DOI BibTeX RDF
12	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Low-power domino circuits using NMOS pull-up on off-critical paths.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie 0001	Low-leakage robust SRAM cell design for sub-100nm technologies.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Leonardo Barboni, Rafaella Fiorelli	Design and power optimization of CMOS RF blocks operating in the moderate inversion region.	SBCCI	2005	DBLP DOI BibTeX RDF	amplifier design, radio frequency integrated circuits, CMOS integrated circuits, power optimization
12	Paul L. Jespers	A design methodology for analogue CMOS circuits.	SBCCI	2005	DBLP DOI BibTeX RDF
12	Youngmoon Choi, Earl E. Swartzlander Jr.	Parallel Prefix Adder Design with Matrix Representation.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
12	Dennis Buss	Technology and design challenges for mobile communication and computing products.	ISLPED	2005	DBLP DOI BibTeX RDF
12	Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King 0001, Borivoje Nikolic	FinFET-based SRAM design.	ISLPED	2005	DBLP DOI BibTeX RDF	double gate transistors, low power, memory, SRAM
12	Stephan Henzler, Thomas Nirschl, Matthias Eireiner, Ettore Amirante, Doris Schmitt-Landsiedel	Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	adiabatic logic, adiabatic mode logic, cross coupled domino, dynamic power reduction, low-power design styles
12	Antti Heiskanen, Timo Rahkonen	Comparison of two class E amplifiers for EER transmitter.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
12	David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler	Indirect programming of floating-gate transistors.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
12	Gerard Villar, Eduard Alarcón, Jordi Madrenas, Francesc Guinjoan, Alberto Poveda	Energy optimization of tapered buffers for CMOS on-chip switching power converters.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
12	Vadim Ivanov, Igor M. Filanovsky	A 110 dB CMRR/PSRR/gain CMOS operational amplifier.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
12	Cristiano Santos, Daniel Lima Ferrão, Ricardo Reis 0001, José Luís Güntzel	Incremental timing optimization for automatic layout generation.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
12	Daniel Fernández, Gerard Villar, Eva Vidal, Eduard Alarcón, Jordi Cosp, Jordi Madrenas	Mismatch-tolerant CMOS oscillator and excitatory synapse for bioinspired image segmentation.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
12	Martin Omaña 0001, O. Losco, Cecilia Metra, Andrea Pagni	On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization.	IOLTS	2005	DBLP DOI BibTeX RDF
12	Amir Fijany, Farrokh Vatan, Mohammad M. Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil	The G4-FET: a universal and programmable logic gate.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	G4-FET, programmable gate, universal logic gate, full adder
12	Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi	A high speed and leakage-tolerant domino logic for high fan-in gates.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high speed, noise immunity, deep submicron, fan-in, domino
12	Cory Jung, Mohammad Hadi Izadi, Michelle L. La Haye	Noise Analysis of Fault Tolerant Active Pixel Sensors.	DFT	2005	DBLP DOI BibTeX RDF
12	Yuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk	Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models.	ISQED	2005	DBLP DOI BibTeX RDF
12	Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally	Fault Tolerance Techniques for the Merrimac Streaming Supercomputer.	SC	2005	DBLP DOI BibTeX RDF
12	Ramaprasath Vilangudipitchai, Poras T. Balsara	Power Switch Network Design for MTCMOS.	VLSI Design	2005	DBLP DOI BibTeX RDF
12	Sergei P. Skorobogatov	Data Remanence in Flash Memory Devices.	CHES	2005	DBLP DOI BibTeX RDF
12	Hiran Tennakoon, Carl Sechen	Efficient and accurate gate sizing with piecewise convex delay models.	DAC	2005	DBLP DOI BibTeX RDF	piecewise convex, optimization, Lagrangian relaxation, gate sizing, delay modeling
12	Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato	A leakage-energy-reduction technique for highly-associative caches in embedded systems.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF	cache memories, embedded processors, leakage current
12	Saul Rosen	Recollections of the Philco Transac S-2000.	IEEE Ann. Hist. Comput.	2004	DBLP DOI BibTeX RDF
12	Arifur Rahman, Vijay Polavarapuv	Evaluation of low-leakage design techniques for field programmable gate arrays.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, leakage power, multiplexer
12	Hidenori Sato, Toshinori Sato	A static and dynamic energy reduction technique for I-cache and BTB in embedded processors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
12	Binu K. Mathew, Al Davis	A loop accelerator for low power embedded VLIW processors.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	embedded systems, low power design, VLIW
12	Kalle Ruttik	BER for CMOS Analog Decoder with Different Working Points.	ICT	2004	DBLP DOI BibTeX RDF
12	Alexandre Schmid, Yusuf Leblebici	Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
12	Seiichiro Fujii, Toshinori Sato	Non-uniform Set-Associative Caches for Power-Aware Embedded Processors.	EUC	2004	DBLP DOI BibTeX RDF
12	Amir Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz	Leakage current reduction by new technique in standby mode.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	subthreshold current, low power, leakage current, digital integrated circuits, static power
12	Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek	Low energy FPGA interconnect design.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	FPGA, low power, interconnect, encoding
12	Jörg Langeheine, Karlheinz Meier, Johannes Schemmel, Martin Trefzer	Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
12	Rohini Krishnan, José Pineda de Gyvez	Low Energy Switch Block For FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
12	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001	Modeling and Estimation of Leakage in Sub-90nm Devices.	VLSI Design	2004	DBLP DOI BibTeX RDF
12	Volkan Kursun, Eby G. Friedman	Domino logic with variable threshold voltage keeper.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
12	Li Ding 0002, Pinaki Mazumder	Simultaneous switching noise analysis using application specific device modeling.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
12	Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins, Vivek De	Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
12	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov	Hierarchical whitespace allocation in top-down placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
12	Stephen H. Unger	Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
12	Akihito Sakanaka, Toshinori Sato	Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction.	PATMOS	2003	DBLP DOI BibTeX RDF
12	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design.	ISVLSI	2003	DBLP DOI BibTeX RDF
12	Alessandro Girardi, Sergio Bampi	LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks.	DATE	2003	DBLP DOI BibTeX RDF
12	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi	Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology.	SBCCI	2003	DBLP DOI BibTeX RDF
12	Stanislav Sedukhin, Mostafa I. Soliman	Trident: Technology-Scalable Architecture for Data Parallel Application.	IPDPS	2003	DBLP DOI BibTeX RDF	scalar/vector/matrix processing, data parallel applications, scalable architecture, BLAS
12	Snorre Aunet, Morten Hartmann	Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware.	ICES	2003	DBLP DOI BibTeX RDF
12	Ricardo Salem Zebulum, Adrian Stoica, Didier Keymeulen, Michael I. Ferguson, Vu Duong, Xin Guo 0002, Vatche Vorperian	Automatic Evolution of Signal Separators Using Reconfigurable Hardware.	ICES	2003	DBLP DOI BibTeX RDF
12	Patricia Giacomelli, Márcio C. Schneider, Carlos Galup-Montoro	MOSVIEW: A Graphical Tool for MOS Analog Design.	MSE	2003	DBLP DOI BibTeX RDF
12	Mohan G. Kabadi, Ranjani Parthasarathi	Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
12	Abhishek Singh 0001, Jitin Tharian, Jim Plusquellic	Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF
12	Lei Yang 0019, C.-J. Richard Shi	FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF