Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Bing Li 0005, Ning Chen 0006, Ulf Schlichtmann |
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010, pp. 524-531, 2010, IEEE, 978-1-4244-8192-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Shohreh Sharif Mansouri, Elena Dubrova |
Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 28th International Conference on Computer Design, ICCD 2010, 3-6 October 2010, Amsterdam, The Netherlands, Proceedings, pp. 253-259, 2010, IEEE Computer Society, 978-1-4244-8936-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Eduardo Luis Rhod, Luca Sterpone, Luigi Carro |
A New Soft-Error Resilient Voltage-Mode Quaternary Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 200-208, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Kazuteru Namba, Masatoshi Sakata, Hideo Ito |
Single Event Induced Double Node Upset Tolerant Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 280-288, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Kun Young Chung, Sandeep K. Gupta 0001 |
Design and test of latch-based circuits to maximize performance, yield, and delay test quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, pp. 94-103, 2010, IEEE Computer Society, 978-1-4244-7206-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Fan Yang 0060, Sreejit Chakravarty |
Testing of latch based embedded arrays using scan tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, pp. 104-113, 2010, IEEE Computer Society, 978-1-4244-7206-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Keisuke Inoue, Mineo Kaneko |
Optimal register assignment with minimum-delay compensation for latch-based design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 887-890, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Khosrov Dabbagh-Sadeghipour |
A new offset cancelled latch comparator for high-speed, low-power ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 13-16, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee |
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 1203-1206, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Massimo Pozzoni, Simone Erba, Paolo Viola, Matteo Pisati, Emanuele Depaoli, Davide Sanzogni, Riccardo Brama, Daniele Baldi, Matteo Repossi, Francesco Svelto |
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 44(4), pp. 1306-1315, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Tetsuo Endoh, Masashi Kamiyanagi |
Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML Type Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 92-C(5), pp. 603-607, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mahdi Fazeli, Seyed Ghassem Miremadi, Alireza Ejlali, Ahmad Patooghy |
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 3(3), pp. 289-303, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Chen-Hsuan Lin, Chun-Yao Wang, Yung-Chih Chen |
Dependent-Latch Identification in Reachable State Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8), pp. 1113-1126, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Evan Mills, Kevin Truong |
Cascading signaling pathways improve the fidelity of a stochastically and deterministically simulated molecular RS latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMC Syst. Biol. ![In: BMC Syst. Biol. 3, pp. 72, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Su-Jin Park, Yonggu Kang, Joung-Yeal Kim, Tae Hee Han, Young-Hyun Jun, Chil-Gee Lee, Bai-Sun Kong |
CMOS cross-coupled charge pump with improved latch-up immunity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 6(11), pp. 736-742, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Hossein Karimiyan Alidash, Vojin G. Oklobdzija |
Low-Power Soft Error Hardened Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers, pp. 256-265, 2009, Springer, 978-3-642-11801-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Seungwhun Paik, Insup Shin, Youngsoo Shin |
HLS-l: High-level synthesis of high performance latch-based circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 1112-1117, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Seonggwan Lee, Seungwhun Paik, Youngsoo Shin |
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009, pp. 375-380, 2009, ACM, 978-1-60558-800-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Bernhard Goll, Horst Zimmermann |
A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, pp. 328-329, 2009, IEEE, 978-1-4244-3458-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra |
Novel High Speed Robust Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 65-73, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Kun Young Chung, Sandeep K. Gupta 0001 |
Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 103-110, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Visvesh S. Sathe 0001, Jerry C. Kao, Marios C. Papaefthymiou |
Resonant-Clock Latch-Based Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 43(4), pp. 864-873, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein |
Heterogeneous Latch-Based Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 14th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2008, Newcastle upon Tyne, UK, April 7-10, 2008, pp. 83-92, 2008, IEEE Computer Society, 978-0-7695-3107-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Graham M. Birtwistle, Kenneth S. Stevens |
The Family of 4-phase Latch Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 14th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2008, Newcastle upon Tyne, UK, April 7-10, 2008, pp. 71-82, 2008, IEEE Computer Society, 978-0-7695-3107-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Yngvar Berg, Omid Mirmotahari, Snorre Aunet |
High speed and ultra low voltage CMOS latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 153-156, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Zhengfeng Huang, Huaguo Liang |
A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece, pp. 175-176, 2008, IEEE Computer Society, 978-0-7695-3264-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Yuichi Nakamura 0002 |
A design method for skew tolerant latch design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 356-359, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang, Yeh-Ning Jou, Geeng-Lih Lin |
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 61-64, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Kyung Tae Do, Young Hwan Kim, Haeng Seon Son |
Timing modeling of latch-controlled sub-systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 40(2), pp. 62-73, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Inhwa Jung, Moo-young Kim, Chulwoo Kim |
Sptpl: a New Pulsed Latch Type Flip-Flop in High-Performance System-on-a-Chip (SOC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 16(2), pp. 169-179, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Venkatesh Acharya, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan |
CMOS Latch Using Quad for High-Speed Comparators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 54-II(5), pp. 407-411, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Anatol Ursu |
Latch Inference for Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007, pp. 127-131, 2007, Univ. Montpellier II, 2-9517461-3-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
16 | Tamer Mohamed, Graham A. Jullien, Wael M. Badawy |
Crossbar latch-based combinational and sequential logic for nano FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2007, San Jose, CA, USA, October 21-22, 2007, pp. 117-122, 2007, IEEE Computer Society, 978-1-4244-1790-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta |
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007, pp. 314-605, 2007, IEEE, 1-4244-0853-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | K. T. Gardiner, Alexandre Yakovlev, Alexandre V. Bystrov |
A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 223-230, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Takashi Ikeda, Kazuteru Namba, Hideo Ito |
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 282-290, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Shinzo Koyama, Yoshihisa Kato, Takayoshi Yamada, Yasuhiro Shimada |
Fast Pulse Driving of Ferroelectric SBT Capacitors in a Nonvolatile Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 89-C(9), pp. 1368-1372, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Yoshihide Komatsu, Yukio Arima, Koichiro Ishibashi |
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 89-C(3), pp. 384-391, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Michael Heer, Viktor Dubec, Sergey Bychikhin, Dionyz Pogany, Erich Gornik, M. Frank, A. Konrad, J. Schulz |
Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 46(9-11), pp. 1591-1596, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Detlef Bonfert, Horst A. Gieser, Heinrich Wolf, M. Frank, A. Konrad, J. Schulz |
Transient-induced latch-up test setup for wafer-level and package-level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 46(9-11), pp. 1629-1633, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Krzysztof Domanski, B. Póltorak, S. Bargstädt-Franke, Wolfgang Stadler, Waclaw Bala |
Physical fundamentals of external transient latch-up and corrective actions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 46(5-6), pp. 689-701, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Amin Nikoozadeh, Boris Murmann |
An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 53-II(12), pp. 1398-1402, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Man Chung Hon |
Spec-based flip-flop and latch repeater planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 326-331, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Shunsuke Okura, Tetsuro Okura, Kenji Taniguchi 0001, Hajime Shibata |
Frequency Response Analysis of Latch Utilized in High-Speed Comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 1077-1080, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Fernando Paixão Cortes, Alessandro Girardi, Sergio Bampi |
Track-and-Latch Comparator Design Using Associations of MOS Transistors and Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 1164-1167, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Wei-Li Su, Herming Chiueh |
A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 553-556, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Jingye Xu, Masud H. Chowdhury |
Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 1061-1064, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito |
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 327-335, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | David E. Lackey |
Efficient Latch and Clock Structures for System-on-Chip Test Flexibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-7, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Yasushi Amamiya, Zin Yamazaki, Yasuyuki Suzuki, Masayuki Mamada, Hikaru Hida |
Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(10), pp. 2111-2117, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi |
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(4), pp. 862-869, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Massimo Alioto, Gaetano Palumbo |
Power-delay optimization of D-latch/MUX source coupled logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 33(1), pp. 65-86, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Ravi K. Kummamuru, Mo Liu 0005, Alexei O. Orlov, Craig S. Lent, Gary H. Bernstein, Gregory L. Snider |
Temperature dependence of the locked mode in a single-electron latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 36(3-6), pp. 304-307, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | S. Bargstädt-Franke, Wolfgang Stadler, Kai Esmark, Martin Streibl, Krzysztof Domanski, Horst A. Gieser, Heinrich Wolf, Waclaw Bala |
Transient latch-up: experimental analysis and device simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 45(2), pp. 297-304, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Gianluca Boselli, Charvaka Duvvury |
Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 45(9-11), pp. 1406-1414, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Himyanshu Anand, Jayanta Bhadra, Alper Sen 0001, Magdy S. Abadir, Kenneth G. Davis |
Establishing latch correspondence for embedded circuits of PowerPC microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30 - December 2, 2005, pp. 37-44, 2005, IEEE Computer Society, 0-7803-9571-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Chuan Lin 0002, Hai Zhou 0001 |
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2005 International Conference on Computer-Aided Design, ICCAD 2005, San Jose, CA, USA, November 6-10, 2005, pp. 329-334, 2005, IEEE Computer Society, 0-7803-9254-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Moo-young Kim, Inhwa Jung, Young-Ho Kwak, Sunghoon Ahn, Chulwoo Kim |
Differential Pass Transistor Pulsed Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Proceedings 2005 IEEE International SOC Conference, September 25-28, 2005, Washington Dulles Airport, Herndon, VA, USA, pp. 295-300, 2005, IEEE, 0-7803-9264-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Bernhard Wicht, Thomas Nirschl, Doris Schmitt-Landsiedel |
Yield and speed optimization of a latch-type voltage sense amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(7), pp. 1148-1158, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | David Trémouilles, Marise Bafleur, Géraldine Bertrand, Nicolas Nolhier, Nicolas Mauran, Lionel Lescouzères |
Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(10), pp. 1778-1782, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar |
Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(9), pp. 1536-1543, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi |
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004, pp. 329-332, 2004, IEEE, 0-7803-8495-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001 |
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 269-274, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Massimo Alioto, Rosario Mita, Gaetano Palumbo |
Performance evaluation of the low-voltage CML D-latch topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 36(4), pp. 191-209, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Amit M. Sheth, Jacob Savir |
Single-clock, single-latch, scan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 52(5), pp. 1455-1457, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Vladislav A. Vashchenko, Ann Concannon, Marcel ter Beek, P. Hopper |
LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 43(1), pp. 61-69, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Markus P. J. Mergens, Christian C. Russ, Koen G. Verhaege, John Armer, Phillip Jozwiak, Russ Mohn |
High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 43(7), pp. 993-1000, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Bernhard Wicht, Thomas Nirschl, Doris Schmitt-Landsiedel |
A yield-optimized latch-type SRAM sense amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003, pp. 409-412, 2003, IEEE, 0-7803-7995-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar |
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 617-620, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Mun-Kyu Choi, Byung-Gil Jeon, Nakwon Jang, Byung-Jun Min, Yoon-Jong Song, Sung-Yung Lee, Hyun-Ho Kim, Dong-Jin Jung, Heung-Jin Joo, Kinam Kim |
A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(11), pp. 1472-1478, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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16 | Mamidala Jagadesh Kumar, Vikram Verma |
Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 51(3), pp. 367-370, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Robert C. Chang, L.-C. Hsu, M.-C. Sun |
A Low-Power and High-Speed D Flip-Flop Using a Single Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 11(1), pp. 51-56, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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16 | Bradley J. Rhodes, Daniel Bullock |
A Scalable Model of Cerebellar Adaptive Timing and Sequencing: The Recurrent Slide and Latch (RSL) Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 17(1), pp. 35-48, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Massimo Alioto, Rosario Mita, Gaetano Palumbo |
Analysis and comparison of low-voltage CML D-latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, pp. 737-740, 2002, IEEE, 0-7803-7596-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Ey Goo Kang, Seung Hyun Moon, Man Young Sung |
A small sized lateral trench electrode IGBT having improved latch-up and breakdown characteristics for power IC system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 385-388, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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16 | Troy A. Johnson, Ivan S. Kourtev |
A single latch, high speed double-edge triggered flip-flop (DETFF). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 189-192, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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16 | Amit Singh 0001, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska |
Latency and Latch Count Minimization in Wave Steered Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 383-388, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Sally Myles, Mario di Bernardo |
Preventing Multiple switchings in Power Electronic Circuits: Effects of the Latch on the nonlinear Dynamics of the DC-DC buck converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Bifurc. Chaos ![In: Int. J. Bifurc. Chaos 10(2), pp. 431-442, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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16 | Nikola Nedovic, Vojin G. Oklobdzija |
Hybrid latch Flip-Flop with Improved Power Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2000, Manaus, Brazil, September 18-24, 2000, pp. 211-215, 2000, IEEE Computer Society, 0-7695-0843-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
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16 | Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan |
Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 653-656, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Hongyan Yan, Manish Biyani, Kenneth K. O |
A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2) latch and its application in a dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(10), pp. 1400-1404, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Janett Mohnke, Paul Molitor, Sharad Malik |
Establishing latch correspondence for sequential circuits using distinguishing signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 27(1), pp. 33-46, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Saeid Nooshabadi, Juan A. Montiel-Nelson, Kamran Eshraghian |
A novel latch design technique for high speed GaAs circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, pp. 331-334, 1999, IEEE, 0-7803-5682-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Jari Pasanen, Bengt Oelmann |
Locally clocked AFSMs with dynamic latch implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, pp. 1643-1646, 1999, IEEE, 0-7803-5682-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | George S. Taylor, Gerard M. Blair |
Reduced complexity two-phase micropipeline latch controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 33(10), pp. 1590-1593, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Jerry R. Burch, Vigyan Singhal |
Robust latch mapping for combinational equivalence checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 563-569, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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16 | Young-Hee Kim, Jae-Yoon Sim, Hong June Park, Jae-Ik Doh, Kun-Woo Park, Hyun-Woong Chung, Jong-Hoon Oh, Choon-Sik Oh, Seung-Han Ahn |
Analysis and prevention of DRAM latch-up during power-on. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(1), pp. 79-85, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Wei Hwang, Rajiv V. Joshi, Walter H. Henkels |
A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997, pp. 712-717, 1997, IEEE Computer Society, 0-8186-8206-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Jacob Savir |
Scan Latch Design for Delay Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1997, Washington, DC, USA, November 3-5, 1997, pp. 446-453, 1997, IEEE Computer Society, 0-7803-4209-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Ellen Sentovich, Horia Toma, Gérard Berry |
Efficient Latch Optimization Using Exclusive Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 8-11, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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16 | Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome |
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 30(4), pp. 487-490, April 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Hungse Cha, Janak H. Patel |
Latch Design for Transient Pulse Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 385-388, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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16 | P. Zhou, J. C. Czilli, Graham A. Jullien, William C. Miller |
Current Input TSPC Latch for High Speed, Complex Switching Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 335-338, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta 0001, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro |
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 2019-2022, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
16 | Michael M. Y. Hui, Benoit Nadeau-Dostie |
Scan testing of latch arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 10th IEEE VLSI Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic City, NJ, USA, pp. 31-36, 1992, IEEE Computer Society, 0-7803-0623-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Susheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce |
ATPG Based on a Novel Grid-Addressable Latch Element. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991., pp. 282-286, 1991, ACM, 0-89791395-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Enrico Sangiorgi |
Latch-up in CMOS circuits: A review. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Eur. Trans. Telecommun. ![In: Eur. Trans. Telecommun. 1(3), pp. 337-349, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda |
Multi-Level Logic Minimization Across Latch Boundaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 406-409, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | K. Wayne Current |
A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: Proceedings of the 20th International Symposium on Multiple-Valued Logic, ISMVL 1990, Charlotte, NC, USA, May 23-25, 1990, pp. 168-173, 1990, IEEE Computer Society, 0-8186-2046-3. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Roberto Menozzi, Massimo Lanzoni, Luca Selmi, Bruno Riccò |
An improved procedure to test CMOS ICs for latch-up. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990, pp. 1028-1034, 1990, IEEE Computer Society, 0-8186-9064-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|