Search results for "D-latch"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Bing Li 0005, Ning Chen 0006, Ulf Schlichtmann	Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods.	ICCAD	2010	DBLP DOI BibTeX RDF
16	Shohreh Sharif Mansouri, Elena Dubrova	Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms.	ICCD	2010	DBLP DOI BibTeX RDF
16	Eduardo Luis Rhod, Luca Sterpone, Luigi Carro	A New Soft-Error Resilient Voltage-Mode Quaternary Latch.	DFT	2010	DBLP DOI BibTeX RDF
16	Kazuteru Namba, Masatoshi Sakata, Hideo Ito	Single Event Induced Double Node Upset Tolerant Latch.	DFT	2010	DBLP DOI BibTeX RDF
16	Kun Young Chung, Sandeep K. Gupta 0001	Design and test of latch-based circuits to maximize performance, yield, and delay test quality.	ITC	2010	DBLP DOI BibTeX RDF
16	Fan Yang 0060, Sreejit Chakravarty	Testing of latch based embedded arrays using scan tests.	ITC	2010	DBLP DOI BibTeX RDF
16	Keisuke Inoue, Mineo Kaneko	Optimal register assignment with minimum-delay compensation for latch-based design.	APCCAS	2010	DBLP DOI BibTeX RDF
16	Khosrov Dabbagh-Sadeghipour	A new offset cancelled latch comparator for high-speed, low-power ADCs.	APCCAS	2010	DBLP DOI BibTeX RDF
16	Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee	A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique.	APCCAS	2010	DBLP DOI BibTeX RDF
16	Massimo Pozzoni, Simone Erba, Paolo Viola, Matteo Pisati, Emanuele Depaoli, Davide Sanzogni, Riccardo Brama, Daniele Baldi, Matteo Repossi, Francesco Svelto	A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
16	Tetsuo Endoh, Masashi Kamiyanagi	Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML Type Latch.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
16	Mahdi Fazeli, Seyed Ghassem Miremadi, Alireza Ejlali, Ahmad Patooghy	Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies.	IET Comput. Digit. Tech.	2009	DBLP DOI BibTeX RDF
16	Chen-Hsuan Lin, Chun-Yao Wang, Yung-Chih Chen	Dependent-Latch Identification in Reachable State Space.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
16	Evan Mills, Kevin Truong	Cascading signaling pathways improve the fidelity of a stochastically and deterministically simulated molecular RS latch.	BMC Syst. Biol.	2009	DBLP DOI BibTeX RDF
16	Su-Jin Park, Yonggu Kang, Joung-Yeal Kim, Tae Hee Han, Young-Hyun Jun, Chil-Gee Lee, Bai-Sun Kong	CMOS cross-coupled charge pump with improved latch-up immunity.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
16	Hossein Karimiyan Alidash, Vojin G. Oklobdzija	Low-Power Soft Error Hardened Latch.	PATMOS	2009	DBLP DOI BibTeX RDF
16	Seungwhun Paik, Insup Shin, Youngsoo Shin	HLS-l: High-level synthesis of high performance latch-based circuits.	DATE	2009	DBLP DOI BibTeX RDF
16	Seonggwan Lee, Seungwhun Paik, Youngsoo Shin	Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits.	ICCAD	2009	DBLP DOI BibTeX RDF
16	Bernhard Goll, Horst Zimmermann	A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V.	ISSCC	2009	DBLP DOI BibTeX RDF
16	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Novel High Speed Robust Latch.	DFT	2009	DBLP DOI BibTeX RDF
16	Kun Young Chung, Sandeep K. Gupta 0001	Efficient Scheduling of Path Delay Tests for Latch-Based Circuits.	VTS	2009	DBLP DOI BibTeX RDF
16	Visvesh S. Sathe 0001, Jerry C. Kao, Marios C. Papaefthymiou	Resonant-Clock Latch-Based Design.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
16	Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein	Heterogeneous Latch-Based Asynchronous Pipelines.	ASYNC	2008	DBLP DOI BibTeX RDF
16	Graham M. Birtwistle, Kenneth S. Stevens	The Family of 4-phase Latch Protocols.	ASYNC	2008	DBLP DOI BibTeX RDF
16	Yngvar Berg, Omid Mirmotahari, Snorre Aunet	High speed and ultra low voltage CMOS latch.	ICECS	2008	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Huaguo Liang	A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies.	IOLTS	2008	DBLP DOI BibTeX RDF
16	Yuichi Nakamura 0002	A design method for skew tolerant latch design.	APCCAS	2008	DBLP DOI BibTeX RDF
16	Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang, Yeh-Ning Jou, Geeng-Lih Lin	Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration.	APCCAS	2008	DBLP DOI BibTeX RDF
16	Kyung Tae Do, Young Hwan Kim, Haeng Seon Son	Timing modeling of latch-controlled sub-systems.	Integr.	2007	DBLP DOI BibTeX RDF
16	Inhwa Jung, Moo-young Kim, Chulwoo Kim	Sptpl: a New Pulsed Latch Type Flip-Flop in High-Performance System-on-a-Chip (SOC).	J. Circuits Syst. Comput.	2007	DBLP DOI BibTeX RDF
16	Venkatesh Acharya, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan	CMOS Latch Using Quad for High-Speed Comparators.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
16	Anatol Ursu	Latch Inference for Equivalence Checking.	ReCoSoC	2007	DBLP BibTeX RDF
16	Tamer Mohamed, Graham A. Jullien, Wael M. Badawy	Crossbar latch-based combinational and sequential logic for nano FPGA.	NANOARCH	2007	DBLP DOI BibTeX RDF
16	Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta	A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time.	ISSCC	2007	DBLP DOI BibTeX RDF
16	K. T. Gardiner, Alexandre Yakovlev, Alexandre V. Bystrov	A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits.	IOLTS	2007	DBLP DOI BibTeX RDF
16	Takashi Ikeda, Kazuteru Namba, Hideo Ito	Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.	DFT	2007	DBLP DOI BibTeX RDF
16	Shinzo Koyama, Yoshihisa Kato, Takayoshi Yamada, Yasuhiro Shimada	Fast Pulse Driving of Ferroelectric SBT Capacitors in a Nonvolatile Latch.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
16	Yoshihide Komatsu, Yukio Arima, Koichiro Ishibashi	Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
16	Michael Heer, Viktor Dubec, Sergey Bychikhin, Dionyz Pogany, Erich Gornik, M. Frank, A. Konrad, J. Schulz	Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
16	Detlef Bonfert, Horst A. Gieser, Heinrich Wolf, M. Frank, A. Konrad, J. Schulz	Transient-induced latch-up test setup for wafer-level and package-level.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
16	Krzysztof Domanski, B. Póltorak, S. Bargstädt-Franke, Wolfgang Stadler, Waclaw Bala	Physical fundamentals of external transient latch-up and corrective actions.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
16	Amin Nikoozadeh, Boris Murmann	An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
16	Man Chung Hon	Spec-based flip-flop and latch repeater planning.	ASP-DAC	2006	DBLP DOI BibTeX RDF
16	Shunsuke Okura, Tetsuro Okura, Kenji Taniguchi 0001, Hajime Shibata	Frequency Response Analysis of Latch Utilized in High-Speed Comparator.	ICECS	2006	DBLP DOI BibTeX RDF
16	Fernando Paixão Cortes, Alessandro Girardi, Sergio Bampi	Track-and-Latch Comparator Design Using Associations of MOS Transistors and Characterization.	ICECS	2006	DBLP DOI BibTeX RDF
16	Wei-Li Su, Herming Chiueh	A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder.	ICECS	2006	DBLP DOI BibTeX RDF
16	Jingye Xu, Masud H. Chowdhury	Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining.	ICECS	2006	DBLP DOI BibTeX RDF
16	Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito	Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.	DFT	2006	DBLP DOI BibTeX RDF
16	David E. Lackey	Efficient Latch and Clock Structures for System-on-Chip Test Flexibility.	ITC	2006	DBLP DOI BibTeX RDF
16	Yasushi Amamiya, Zin Yamazaki, Yasuyuki Suzuki, Masayuki Mamada, Hikaru Hida	Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
16	Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi	1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
16	Massimo Alioto, Gaetano Palumbo	Power-delay optimization of D-latch/MUX source coupled logic gates.	Int. J. Circuit Theory Appl.	2005	DBLP DOI BibTeX RDF
16	Ravi K. Kummamuru, Mo Liu 0005, Alexei O. Orlov, Craig S. Lent, Gary H. Bernstein, Gregory L. Snider	Temperature dependence of the locked mode in a single-electron latch.	Microelectron. J.	2005	DBLP DOI BibTeX RDF
16	S. Bargstädt-Franke, Wolfgang Stadler, Kai Esmark, Martin Streibl, Krzysztof Domanski, Horst A. Gieser, Heinrich Wolf, Waclaw Bala	Transient latch-up: experimental analysis and device simulation.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
16	Gianluca Boselli, Charvaka Duvvury	Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
16	Himyanshu Anand, Jayanta Bhadra, Alper Sen 0001, Magdy S. Abadir, Kenneth G. Davis	Establishing latch correspondence for embedded circuits of PowerPC microprocessors.	HLDVT	2005	DBLP DOI BibTeX RDF
16	Chuan Lin 0002, Hai Zhou 0001	Trade-off between latch and flop for min-period sequential circuit designs with crosstalk.	ICCAD	2005	DBLP DOI BibTeX RDF
16	Moo-young Kim, Inhwa Jung, Young-Ho Kwak, Sunghoon Ahn, Chulwoo Kim	Differential Pass Transistor Pulsed Latch.	SoCC	2005	DBLP DOI BibTeX RDF
16	Bernhard Wicht, Thomas Nirschl, Doris Schmitt-Landsiedel	Yield and speed optimization of a latch-type voltage sense amplifier.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
16	David Trémouilles, Marise Bafleur, Géraldine Bertrand, Nicolas Nolhier, Nicolas Mauran, Lionel Lescouzères	Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
16	Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar	Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
16	Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi	A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond.	CICC	2004	DBLP DOI BibTeX RDF
16	Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.	ISMVL	2004	DBLP DOI BibTeX RDF
16	Massimo Alioto, Rosario Mita, Gaetano Palumbo	Performance evaluation of the low-voltage CML D-latch topology.	Integr.	2003	DBLP DOI BibTeX RDF
16	Amit M. Sheth, Jacob Savir	Single-clock, single-latch, scan design.	IEEE Trans. Instrum. Meas.	2003	DBLP DOI BibTeX RDF
16	Vladislav A. Vashchenko, Ann Concannon, Marcel ter Beek, P. Hopper	LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
16	Markus P. J. Mergens, Christian C. Russ, Koen G. Verhaege, John Armer, Phillip Jozwiak, Russ Mohn	High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
16	Bernhard Wicht, Thomas Nirschl, Doris Schmitt-Landsiedel	A yield-optimized latch-type SRAM sense amplifier.	ESSCIRC	2003	DBLP DOI BibTeX RDF
16	Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar	Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process.	CICC	2003	DBLP DOI BibTeX RDF
16	Mun-Kyu Choi, Byung-Gil Jeon, Nakwon Jang, Byung-Jun Min, Yoon-Jong Song, Sung-Yung Lee, Hyun-Ho Kim, Dong-Jin Jung, Heung-Jin Joo, Kinam Kim	A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
16	Mamidala Jagadesh Kumar, Vikram Verma	Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET.	IEEE Trans. Reliab.	2002	DBLP DOI BibTeX RDF
16	Robert C. Chang, L.-C. Hsu, M.-C. Sun	A Low-Power and High-Speed D Flip-Flop Using a Single Latch.	J. Circuits Syst. Comput.	2002	DBLP DOI BibTeX RDF
16	Bradley J. Rhodes, Daniel Bullock	A Scalable Model of Cerebellar Adaptive Timing and Sequencing: The Recurrent Slide and Latch (RSL) Model.	Appl. Intell.	2002	DBLP DOI BibTeX RDF
16	Massimo Alioto, Rosario Mita, Gaetano Palumbo	Analysis and comparison of low-voltage CML D-latch.	ICECS	2002	DBLP DOI BibTeX RDF
16	Ey Goo Kang, Seung Hyun Moon, Man Young Sung	A small sized lateral trench electrode IGBT having improved latch-up and breakdown characteristics for power IC system.	ICECS	2001	DBLP DOI BibTeX RDF
16	Troy A. Johnson, Ivan S. Kourtev	A single latch, high speed double-edge triggered flip-flop (DETFF).	ICECS	2001	DBLP DOI BibTeX RDF
16	Amit Singh 0001, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	Latency and Latch Count Minimization in Wave Steered Circuits.	DAC	2001	DBLP DOI BibTeX RDF
16	Sally Myles, Mario di Bernardo	Preventing Multiple switchings in Power Electronic Circuits: Effects of the Latch on the nonlinear Dynamics of the DC-DC buck converter.	Int. J. Bifurc. Chaos	2000	DBLP DOI BibTeX RDF
16	Nikola Nedovic, Vojin G. Oklobdzija	Hybrid latch Flip-Flop with Improved Power Efficiency.	SBCCI	2000	DBLP BibTeX RDF
16	Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan	Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input.	ISCAS	2000	DBLP DOI BibTeX RDF
16	Hongyan Yan, Manish Biyani, Kenneth K. O	A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2) latch and its application in a dual-modulus prescaler.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
16	Janett Mohnke, Paul Molitor, Sharad Malik	Establishing latch correspondence for sequential circuits using distinguishing signatures.	Integr.	1999	DBLP DOI BibTeX RDF
16	Saeid Nooshabadi, Juan A. Montiel-Nelson, Kamran Eshraghian	A novel latch design technique for high speed GaAs circuits.	ICECS	1999	DBLP DOI BibTeX RDF
16	Jari Pasanen, Bengt Oelmann	Locally clocked AFSMs with dynamic latch implementation.	ICECS	1999	DBLP DOI BibTeX RDF
16	George S. Taylor, Gerard M. Blair	Reduced complexity two-phase micropipeline latch controller.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
16	Jerry R. Burch, Vigyan Singhal	Robust latch mapping for combinational equivalence checking.	ICCAD	1998	DBLP DOI BibTeX RDF
16	Young-Hee Kim, Jae-Yoon Sim, Hong June Park, Jae-Ik Doh, Kun-Woo Park, Hyun-Woong Chung, Jong-Hoon Oh, Choon-Sik Oh, Seung-Han Ahn	Analysis and prevention of DRAM latch-up during power-on.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
16	Wei Hwang, Rajiv V. Joshi, Walter H. Henkels	A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit.	ICCD	1997	DBLP DOI BibTeX RDF
16	Jacob Savir	Scan Latch Design for Delay Test.	ITC	1997	DBLP DOI BibTeX RDF
16	Ellen Sentovich, Horia Toma, Gérard Berry	Efficient Latch Optimization Using Exclusive Sets.	DAC	1997	DBLP DOI BibTeX RDF
16	Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome	A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
16	Hungse Cha, Janak H. Patel	Latch Design for Transient Pulse Tolerance.	ICCD	1994	DBLP DOI BibTeX RDF
16	P. Zhou, J. C. Czilli, Graham A. Jullien, William C. Miller	Current Input TSPC Latch for High Speed, Complex Switching Trees.	ISCAS	1994	DBLP DOI BibTeX RDF
16	Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta 0001, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro	A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.	ISCAS	1993	DBLP BibTeX RDF
16	Michael M. Y. Hui, Benoit Nadeau-Dostie	Scan testing of latch arrays.	VTS	1992	DBLP DOI BibTeX RDF
16	Susheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce	ATPG Based on a Novel Grid-Addressable Latch Element.	DAC	1991	DBLP DOI BibTeX RDF
16	Enrico Sangiorgi	Latch-up in CMOS circuits: A review.	Eur. Trans. Telecommun.	1990	DBLP DOI BibTeX RDF
16	Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda	Multi-Level Logic Minimization Across Latch Boundaries.	ICCAD	1990	DBLP DOI BibTeX RDF
16	K. Wayne Current	A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch.	ISMVL	1990	DBLP DOI BibTeX RDF
16	Roberto Menozzi, Massimo Lanzoni, Luca Selmi, Bruno Riccò	An improved procedure to test CMOS ICs for latch-up.	ITC	1990	DBLP DOI BibTeX RDF