Search results for "FinFET"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Muyang Qin, Yabin Sun, Xiaojin Li, Yanling Shi	Analytical Parameter Extraction for Small-Signal Equivalent Circuit of 3D FinFET Into Sub-THz Range.	IEEE Access	2018	DBLP DOI BibTeX RDF
14	Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui	Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
14	Kexin Yang 0001, Taizhi Liu, Rui Zhang 0048, Linda Milor	A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
14	Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui	Design of Low-Power High-Performance FinFET Standard Cells.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
14	Vikas Mahor, Manisha Pattanaik	A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
14	M. Arulvani, M. Mohamed Ismail	Low power FinFET content addressable memory design for 5G communication networks.	Comput. Electr. Eng.	2018	DBLP DOI BibTeX RDF
14	Osama Abdelkader, Mohamed Mohie El-Din, Hassan Mostafa, Hamdy Abdelhamid, Hossam A. H. Fahmy, Yehea Ismail, Ahmed M. Soliman	Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
14	Ajay Kumar Dadoria, Kavita Khare, Tarun Kumar Gupta, R. P. Singh	New Leakage Reduction Techniques for FinFET Technology with Its Application.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
14	S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad	FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
14	Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac	Detectability Challenges of Bridge Defects in FinFET Based Logic Cells.	J. Electron. Test.	2018	DBLP DOI BibTeX RDF
14	Ye Yu 0003, Niraj K. Jha	Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment.	ACM J. Emerg. Technol. Comput. Syst.	2018	DBLP DOI BibTeX RDF
14	Lucas Prilenski, P. R. Mukund	A sub 1-volt subthreshold bandgap reference at the 14 nm FinFET node.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
14	Rajashree Das, Srimanta Baishya	Analytical model of surface potential and threshold voltage in gate-drain overlap FinFET.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
14	Rajeev Pankaj Nelapati, K. Sivasankaran	Impact of self-heating effect on the performance of hybrid FinFET.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
14	Xiaocheng Liu, Qifan Zhang, Pengcheng Qiu, Jiajie Tong, Huazi Zhang, Changyong Zhao, Jun Wang 0062	A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET.	CoRR	2018	DBLP BibTeX RDF
14	Esteve Amat, Antonio Calomarde, Ramon Canal, Antonio Rubio 0001	Optimization of FinFET-Based Gain Cells for Low Power Sub-V T Embedded DRAMs.	J. Low Power Electron.	2018	DBLP DOI BibTeX RDF
14	S. Nilamani, P. Chitra, V. N. Ramakrishnan	Topological variation on sub-20 nm double-gate inversion and Junctionless-FinFET based 6T-SRAM circuits and its SEU radiation performance.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
14	Shalu Kaundal, Ashwani K. Rana	Evaluation of statistical variability and parametric sensitivity of non-uniformly doped Junctionless FinFET.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
14	Anne Beyreuther, Norbert Herfurth, Elham Amini, Tomonori Nakamura, Ingrid De Wolf, Christian Boit	Photon emission as a characterization tool for bipolar parasitics in FinFET technology.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
14	Woojin Ahn, Sang Hoon Shin, Chunsheng Jiang, Hai Jiang, M. A. Wahab, Muhammad Ashraful Alam	Integrated modeling of Self-heating of confined geometry (FinFET, NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
14	Minjung Jin, Kangjung Kim, Yoohwan Kim, Hyewon Shim, Jinju Kim, Gunrae Kim, Sangwoo Pae	Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
14	Shaalini Chithambaram, Pik Kee Tan, Yuzhe Zhao, Binghai Liu, Yinzhe Ma, Alfred Quah, Dayanand Nagalingam, Yanlin Pan, Zhihong Mai	Failure analysis on 14 nm FinFET devices with ESD CDM failure.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
14	Roberto B. Almeida, Cleiton Magano Marques, Paulo F. Butzen, Fábio G. R. G. da Silva, Ricardo A. L. Reis, Cristina Meinhardt	Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
14	G. Cardoso Medeiros, Letícia Maria Veiras Bolzani, Mottaqiallah Taouil, Fabian Vargas 0001, Said Hamdioui	A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
14	Subhadeep Mukhopadhyay 0002, Yung-Huei Lee, Jen-Hao Lee	Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
14	ChengKuei Lee, Sen Yin, Jinyu Zhang, Yan Wang 0023, Zhiping Yu	Study on scalability of hybrid junctionless FinFET and multi-stacked nanowire FET by TCAD simulation.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
14	Alfonso Herrera-Moreno, Jose Luis Garcia-Gervacio, Héctor Villacorta-Minaya, Héctor Vázquez-Leal	TCAD analysis and modeling for NBTI mechanism in FinFET transistors.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
14	Marko Simicic, Geert Hellings, Shih-Hung Chen, Naoto Horiguchi, Dimitri Linten	ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology.	ESSDERC	2018	DBLP DOI BibTeX RDF
14	Bertrand Parvais, Geert Hellings, Marko Simicic, Pieter Weckx, Jérôme Mitard, Doyoung Jang, V. Deshpande, B. van Liempc, Anabela Veloso, A. Vandooren, Niamh Waldron, Piet Wambacq, Nadine Collaert, Diederik Verkest	Scaling CMOS beyond Si FinFET: an analog/RF perspective.	ESSDERC	2018	DBLP DOI BibTeX RDF
14	Umanath Kamath, Tao Yu, Wei Yao, Edward Cullen, John Jennings, Susan Wu, Peng Lim, Brendan Farley, Robert Bogdan Staszewski	BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET.	ESSDERC	2018	DBLP DOI BibTeX RDF
14	A. V. Korshunov, S. A. Ilin	The Technique of Fast Power Analysis for FinFET Standard Cells.	EWDTS	2018	DBLP DOI BibTeX RDF
14	Milova Paul, Boeila Sampath Kumar, Harald Gossner, Mayank Shrivastava	Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability.	IRPS	2018	DBLP DOI BibTeX RDF
14	H. Zhang, H. Jiang, M. R. Eaker, Kurt J. Lezon, Balaji Narasimham, Nihaar N. Mahatme, Lloyd W. Massengill, Bharat L. Bhuva	Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology.	IRPS	2018	DBLP DOI BibTeX RDF
14	Chen-Yi Su, M. Armstrong, Lei Jiang, S. A. Kumar, C. D. Landon, S. Liu, Inanc Meric, K. W. Park, Leif Paulson, K. Phoa, Bernhard Sell, Jihan Standfest, Ketul B. Sutaria, J. Wan, D. Young, Stephen Ramey	Transistor reliability characterization and modeling of the 22FFL FinFET technology.	IRPS	2018	DBLP DOI BibTeX RDF
14	Taiki Uemura, Soonyoung Lee, Dahye Min, Ihlhwa Moon, Jungman Lim, Seungbae Lee, Hyun-Chul Sagong, Sangwoo Pae	Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit.	IRPS	2018	DBLP DOI BibTeX RDF
14	D. S. Huang, J. H. Lee, Y. S. Tsai, Y. F. Wang, Y. S. Huang, C. K. Lin, Ryan Lu, Jun He	Comprehensive device and product level reliability studies on advanced CMOS technologies featuring 7nm high-k metal gate FinFET transistors.	IRPS	2018	DBLP DOI BibTeX RDF
14	Pengpeng Ren, Changze Liu, Sanping Wan, Jiayang Zhang, Zhuoqing Yu, Nie Liu, Yongsheng Sun, Runsheng Wang, Canhui Zhan, Zhenghao Gan, Waisum Wong, Yu Xia, Ru Huang	New insights into the HCI degradation of pass-gate transistor in advanced FinFET technology.	IRPS	2018	DBLP DOI BibTeX RDF
14	Balaji Narasimham, Saket Gupta, Daniel S. Reed, J. K. Wang, Nick Hendrickson, Hasan Taufique	Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs.	IRPS	2018	DBLP DOI BibTeX RDF
14	Antoine Laurent, Xavier Garros, Sylvain Barraud, J. Pelloux-Prayer, Mikaël Cassé, Fred Gaillard, X. Federspiel, David Roy 0001, E. Vincent, Gérard Ghibaudo	Performance & reliability of 3D architectures (πfet, Finfet, Ωfet).	IRPS	2018	DBLP DOI BibTeX RDF
14	Miaomiao Wang 0006, Richard G. Southwick, Kangguo Cheng, James H. Stathis	Lateral profiling of HCI induced damage in ultra-scaled FinFET devices with Id-Vd characteristics.	IRPS	2018	DBLP DOI BibTeX RDF
14	Kaustubh Joshi, Shu-Wen Chang, D. S. Huang, P. J. Liao, Yung-Huei Lee	Study of dynamic TDDB in scaled FinFET technologies.	IRPS	2018	DBLP DOI BibTeX RDF
14	Hyun-Chul Sagong, Hyunjin Kim, Seungjin Choo, Sungyoung Yoon, Hyewon Shim, Sangsu Ha, Tae-Young Jeong, Minhyeok Choe, Junekyun Park, Sangchul Shin, Sangwoo Pae	Effects of Far-BEOL anneal on the WLR and product reliability characterization of FinFET process technology.	IRPS	2018	DBLP DOI BibTeX RDF
14	Wen Liu, Andreas Kerber, Fernando Guarin, Claude Ortolland	Cap layer and multi-work-function tuning impact on TDDB/BTI in SOI FinFET devices.	IRPS	2018	DBLP DOI BibTeX RDF
14	Yi-Pin Fang, Anthony S. Oates	Soft errors in 7nm FinFET SRAMs with integrated fan-out packaging.	IRPS	2018	DBLP DOI BibTeX RDF
14	Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani, Koji Nii	Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET.	IRPS	2018	DBLP DOI BibTeX RDF
14	Peter C. Paliwoda, Zakariae Chbili, A. Kerber, D. Singh, Durga Misra	Ambient temperature and layout impact on self-heating characterization in FinFET devices.	IRPS	2018	DBLP DOI BibTeX RDF
14	Hyunjin Kim, Minjung Jin, Hyun-Chul Sagong, Jinju Kim, Ukjin Jung, Minhyuck Choi, Junekyun Park, Sangchul Shin, Sangwoo Pae	A systematic study of gate dielectric TDDB in FinFET technology.	IRPS	2018	DBLP DOI BibTeX RDF
14	Krzysztof Domanski	Latch-up in FinFET technologies.	IRPS	2018	DBLP DOI BibTeX RDF
14	Anisur Rahman, Javier Dacuña, Pinakpani Nayak, Gerald S. Leatherman, Stephen Ramey	Reliability studies of a 10nm high-performance and low-power CMOS technology featuring 3rd generation FinFET and 5th generation HK/MG.	IRPS	2018	DBLP DOI BibTeX RDF
14	Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor	Degradation analysis of high performance 14nm FinFET SRAM.	DATE	2018	DBLP DOI BibTeX RDF
14	Meng-Chi Chen, Tsung-Hsuan Wu, Cheng-Wen Wu	A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit.	ATS	2018	DBLP DOI BibTeX RDF
14	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001	Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells.	ICECS	2018	DBLP DOI BibTeX RDF
14	Amir Shalom, Robert Giterman, Adam Teman	High Density GC-eDRAM Design in 16nm FinFET.	ICECS	2018	DBLP DOI BibTeX RDF
14	Fabio G. Rossato G. da Silva, Cristina Meinhardt, Ricardo Reis 0001	Impact of Near-Threshold and Variability on 7nm FinFET XOR Circuits.	ICECS	2018	DBLP DOI BibTeX RDF
14	Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic	A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.	ESSCIRC	2018	DBLP DOI BibTeX RDF
14	Umanath Kamath, Edward Cullen, John Jennings, Ionut Cical, Darragh Walsh, Peng Lim, Brendan Farley, Robert Bogdan Staszewski	A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from -45°C to 125°C.	ESSCIRC	2018	DBLP DOI BibTeX RDF
14	Sae Kyu Lee, Paul N. Whatmough, Niamh Mulholland, Patrick Hansen, David Brooks 0001, Gu-Yeon Wei	A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET.	ESSCIRC	2018	DBLP DOI BibTeX RDF
14	Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong	A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS.	BCICTS	2018	DBLP DOI BibTeX RDF
14	Steven Callender, Woorim Shin, Hyung-Jin Lee, Stefano Pellerano, Christopher D. Hull	FinFET for mm Wave - Technology and Circuit Design Challenges.	BCICTS	2018	DBLP DOI BibTeX RDF
14	Min Soo Bae, Chuntaek Park, Ilgu Yun	Compact Drain Current Model of Nanoscale FinFET Considering Short Channel Effect in Ballistic Transport Regime.	SMACD	2018	DBLP DOI BibTeX RDF
14	Rafaella Fiorelli, Juan Núñez 0002, Fernando Silveira	All-inversion region gm/ID methodology for RF circuits in FinFET technologies.	NEWCAS	2018	DBLP DOI BibTeX RDF
14	Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl	A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski	A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Bichoy Bahr, Yanbo He, Zoran Krivokapic, Srinivasa Banna, Dana Weinstein	32GHz resonant-fin transistors in 14nm FinFET technology.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao 0010, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang	A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Taejoong Song, Jonghoon Jung, Woojin Rim, Hoonki Kim, Yongho Kim, Changnam Park, Jeongho Do, Sunghyun Park 0003, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, Jaeseung Choi 0001, Jong Shik Yoon	A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone	A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang 0002, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang	A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl	A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Cho-Ying Lu, Surej Ravikumar, Amruta D. Sali, Matthias Eberlein, Hyung-Jin Lee	An 8b subthreshold hybrid thermal sensor with ±1.07°C inaccuracy and single-element remote-sensing technique in 22nm FinFET.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr	A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Qing Liu, Dae Hyun Kwon, Quang-Diep Bui, Jeong-Hyun Choi, Jaehun Lee, Sanghyun Baek, Seungchan Heo, Thomas Byunghak Cho	A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOS.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Thomas Morf, Daniel M. Kuchta, Lukas Kull, Marcel A. Kossel, Danny Luu, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl	A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Stanley Chen, Lei Zhou, Ian Zhuang, Jay Im, Didem Turkur Melek, Jinyung Namkoong, Mayank Raj, Jaewook Shin, Yohan Frans, Ken Chang	A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Marc Erett, Declan Carey, James Hudner, Ronan Casey, Kevin Geary, Pedro Neto 0001, Mayank Raj, Scott McLeod, Hongtao Zhang 0002, Arianne Roldan, Hongyuan Zhao, Ping-Chuan Chiang, Haibing Zhao, Kee Hian Tan, Yohan Frans, Ken Chang	A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Arijit Banerjee 0002, Sumanth Kamineni, Benton H. Calhoun	Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications.	ISLPED	2018	DBLP DOI BibTeX RDF
14	Bruno Vaz, Bob Verbruggen, Christophe Erdmann, Diarmuid Collins, John McGrath, Ali Boumaalif, Edward Cullen, Darragh Walsh, Alonso Morgado, Conrado Mesadri, Brian Long, Rajitha Pathepuram, Ronnie De La Torre, Alvin Manlapat, Georgios Karyotis, Dimitris Tsaliagos, Patrick Lynch, Peng Lim, Daire Breathnach, Brendan Farley	A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata	14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Amy Whitcombe, Borivoje Nikolic, Farhana Sheikh, Erkan Alpman, Ashoke Ravi	A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski	A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang	A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Ting-Kuei Kuan, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen 0001	A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang 0002, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang	A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang 0003, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang	A 112-GB/S PAM4 Transmitter in 16NM FinFET.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Jay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, David Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang	A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy	A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Xiaocheng Liu, Qifan Zhang, Pengcheng Qiu, Jiajie Tong, Huazi Zhang, Changyong Zhao, Jun Wang 0062	A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET.	ISWCS	2018	DBLP DOI BibTeX RDF
14	Youngmin Kim, Pilsung Jang, Joongseok Lim, Won Ko, Seungchan Heo, Jongwoo Lee, Thomas Byunghak Cho	A Ka-band Phase Shifting Low Noise Amplifier with Gain Error Compensation for 5G RF beam forming array using 14nm FinFET CMOS.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Motoi Ichihashi, Youngtag Woo, Muhammed Ahosan Ul Karim, Vivek Joshi, David Burnett	10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application.	SoCC	2018	DBLP DOI BibTeX RDF
14	G. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen	Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs.	LATS	2018	DBLP DOI BibTeX RDF
14	Vishal Gupta 0002, Saurabh Khandelwal, Jimson Mathew, Marco Ottavi	45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control.	DFT	2018	DBLP DOI BibTeX RDF
14	Hassan Afzali-Kusha, Alireza Shafaei, Massoud Pedram	A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell.	ISQED	2018	DBLP DOI BibTeX RDF
14	Archana Pandey, Pitul Garg, Shobhit Tyagi, Rajeev Ranjan, Anand Bulusu	A modified method of logical effort for FinFET circuits considering impact of fin-extension effects.	ISQED	2018	DBLP DOI BibTeX RDF
14	Vivek Nautiyal, Nishant Nukala, Fakhruddin Ali Bohra, Sagar Dwivedi, Jitendra Dasani, Satinderjit Singh, Gaurav Singla, Martin Kinkade	Logic-based row redundancy technique designed in 7nm FinFET technology for embedded SRAMs.	ISQED	2018	DBLP DOI BibTeX RDF
14	Shreyash Patel, YoungBae Kim, Ken Choi	Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory.	ISOCC	2018	DBLP DOI BibTeX RDF
14	H. Girish, D. R. Shashikumar	SOPA: Search Optimization Based Predictive Approach for Design Optimization in FinFET/SRAM.	CSOS (2)	2018	DBLP DOI BibTeX RDF
14	Ali Razavieh, Y. Deng, Peter Zeitzoff, M. R. Na, J. Frougier, Gauri Karve, D. E. Brown, T. Yamashita, Edward J. Nowak	Effective Drive Current in Scaled FinFET and NSFET CMOS Inverters.	DRC	2018	DBLP DOI BibTeX RDF
14	Kexin Yang 0001, Taizhi Liu, Rui Zhang 0048, Linda Milor	Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology.	VTS	2018	DBLP DOI BibTeX RDF
14	Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian, Anteneh Gebregiorgis, Mohammad Saber Golanbari, Rajendra Bishnoi, Mehdi Baradaran Tahoori	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications.	ITC	2018	DBLP DOI BibTeX RDF
14	Will Howell, Friedrich Hapke, Edward Brazil, Srikanth Venkataraman, R. Datta, Andreas Glowatz, Wilfried Redemund, J. Schmerberg, Anja Fast, Janusz Rajski	DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies.	ITC	2018	DBLP DOI BibTeX RDF