Search results for "Verilog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Luke Demoracski, Dimiter R. Avresky	An Approach for Functional Decomposition Applied to State-Based Designs.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
10	Hua Li, Jianzhou Li	A High Performance Sub-Pipelined Architecture for AES.	ICCD	2005	DBLP DOI BibTeX RDF	sub-pipelined architecture, FPGA, cryptography, AES
10	Chun Luo, Jun Yang 0006, Gugang Gao, Longxing Shi	Domain fault model and coverage metric for SoC verification.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
10	Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch	Design of superscalar processor with multi-bank register file.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
10	Dayu Yang, Foster F. Dai, Charles E. Stroud	Built-in self-test for automatic analog frequency response measurement.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe	Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
10	Chengjun Zhang, Chunyan Wang 0004, M. Omair Ahmad	A VLSI architecture for a high-speed computation of the 1D discrete wavelet transform.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
10	Yasuhiro Takahashi, Michio Yokoyama	New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
10	Ming-Ta Hsieh, Gerald E. Sobelman	Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
10	Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu	An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
10	Anat Dahan, Daniel Geist, Leonid Gluhovsky, Dmitry Pidan, Gil Shapir, Yaron Wolfsthal, Lyes Benalycherif, Romain Kamdem, Younes Lahbib	Combining System Level Modeling with Assertion Based Verification.	ISQED	2005	DBLP DOI BibTeX RDF
10	Chun Luo, Jun Yang 0006, Longxing Shi, Xufan Wu, Yu Zhang	Domain Strategy and Coverage Metric for Validation.	ISQED	2005	DBLP DOI BibTeX RDF
10	Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo	Automatic Partitioner for Behavior Level Distributed Logic Simulation.	FORTE	2005	DBLP DOI BibTeX RDF	RTL level partitioner, behavior level partitioner, distributed simulation, parallel simulation
10	R. Gopalakrishnan, Rajat Moona	Variable Resizing for Area Improvement in Behavioral Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
10	Ping Dong, Xiangdong Shi, Jiehui Yang	Design of a New Kind of Encryption Kernel Based on RSA Algorithm.	CIS (2)	2005	DBLP DOI BibTeX RDF
10	Ethan Schuchman, T. N. Vijaykumar	Rescue: A Microarchitecture for Testability and Defect Tolerance.	ISCA	2005	DBLP DOI BibTeX RDF
10	Arash Reyhani-Masoleh, M. Anwar Hasan	Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2^{m}).	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
10	Byung Cheol Song, Kang Wook Chun	Multi-resolution block matching algorithm and its VLSI architecture for fast motion estimation in an MPEG-2 video encoder.	IEEE Trans. Circuits Syst. Video Technol.	2004	DBLP DOI BibTeX RDF
10	Bin Sheng, Wen Gao 0001, Di Wu 0022	An implemented architecture of deblocking filter for H.264/AVC.	ICIP	2004	DBLP DOI BibTeX RDF
10	Himanshu Jain, Daniel Kroening, Edmund M. Clarke	Verification of SpecC using predicate abstraction.	MEMOCODE	2004	DBLP DOI BibTeX RDF
10	Suryaprasad Jayadevappa, Ravi Shankar 0002, Imad Mahgoub	A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study.	ISVLSI	2004	DBLP DOI BibTeX RDF
10	Shu-Shin Chin, Sangjin Hong, Suhwan Kim	Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units.	ISVLSI	2004	DBLP DOI BibTeX RDF
10	John F. Keane, Christopher Bradley, Carl Ebeling	A compiled accelerator for biological cell signaling simulations.	FPGA	2004	DBLP DOI BibTeX RDF	simulation, reconfigurable hardware, cell, biology, reactions
10	Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Mohamed, Sofiène Tahar	On the Design and Verification Methodology of the Look-Aside Interface.	DATE	2004	DBLP DOI BibTeX RDF
10	José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira 0001	A Probabilistic Method for the Computation of Testability of RTL Constructs.	DATE	2004	DBLP DOI BibTeX RDF
10	J. D. Kranthi Kumar, Shri K. V. Srinivasan	A Novel VLSI Architecture to Implement Region Merging Algorithm for Image Segmentation.	DSD	2004	DBLP DOI BibTeX RDF
10	Maâmar El-Amine Hamri, Norbert Giambiasi, Claudia S. Frydman	Simulation Semantics for Min-Max DEVS Models.	AIS	2004	DBLP DOI BibTeX RDF
10	Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer 0001, Kurt Keutzer	Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	automatic control generation, instruction set extraction, cycle-accurate simulation
10	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
10	Kees A. Vissers	Programming models and architectures for FPGA platforms.	CASES	2004	DBLP DOI BibTeX RDF
10	Daniel Barros Jr., Fabian Vargas 0001, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Modeling and Simulation of Time Domain Faults in Digital Systems.	IOLTS	2004	DBLP DOI BibTeX RDF
10	Christian Stangier, Thomas Sidle	Invariant Checking Combining Forward and Backward Traversal.	FMCAD	2004	DBLP DOI BibTeX RDF
10	Foster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi	Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer.	ITC	2004	DBLP DOI BibTeX RDF
10	Bill Eklow, Anoosh Hosseini, Chi Khuong, Shyam Pullela, Toai Vo, Hien Chau	Simulation Based System Level Fault Insertion Using Co-verification Tools.	ITC	2004	DBLP DOI BibTeX RDF
10	Paolo Ienne, Ajay Kumar Verma	Arithmetic Transformations to Maximise the Use of Compressor Trees.	DELTA	2004	DBLP DOI BibTeX RDF
10	Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen	Efficient timing closure without timing driven placement and routing.	DAC	2004	DBLP DOI BibTeX RDF	digital design flow, gate sizing, placement and routing, timing closure
10	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	Automatic translation of software binaries onto FPGAs.	DAC	2004	DBLP DOI BibTeX RDF	compiler, reconfigurable computing, binary translation, hardware-software co-design, decompilation
10	Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul	A test evaluation technique for VLSI circuits using register-transfer level fault modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
10	Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri	A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	hierarchical test generation, constraint slicing, incremental slicing, program slicing, data-flow analysis
10	Arun Raghupathy, Nitin Chandrachoodan, K. J. Ray Liu	Algorithm and VLSI architecture for high performance adaptive video scaling.	IEEE Trans. Multim.	2003	DBLP DOI BibTeX RDF
10	Jen-Shiun Chiang, Min-Shiou Tsai	A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system
10	Jae Sung Lee, Myung Hoon Sunwoo	Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	application specific digital signal processor, DMT, fast Fourier transform, OFDM
10	Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi	A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation.	DSN	2003	DBLP DOI BibTeX RDF
10	Arvind	Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk.	MEMOCODE	2003	DBLP DOI BibTeX RDF
10	Hong Peng, Sofiène Tahar, Yassine Mokhtari	Compositional Verification of a Switch Fabric from Nortel Networks.	ICFEM	2003	DBLP DOI BibTeX RDF
10	Alex K. Jones, Prithviraj Banerjee	An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
10	Khaled Benkrid, Samir Belkacemi, Danny Crookes	A logic based approach to hardware abstraction.	FPGA	2003	DBLP DOI BibTeX RDF
10	Matjaz Verderber, Andrej Zemva, Damjan Lampret	HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder.	DATE	2003	DBLP DOI BibTeX RDF
10	Seetharaman Ramachandran, S. Srinivasan 0001	Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization.	DSD	2003	DBLP DOI BibTeX RDF
10	Maria-Cristina V. Marinescu, Martin C. Rinard	A Formal Framework for Modular Synchronous System Design.	FME	2003	DBLP DOI BibTeX RDF	modular, system design, asynchronous, formal
10	Amir K. Daneshbeh, M. Anwarul Hasan	A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2m).	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
10	Matjaz Verderber, Andrej Zemva, Andrej Trost	HW/SW Codesign of the MPEG-2 Video Decoder.	IPDPS	2003	DBLP DOI BibTeX RDF
10	Eric W. Johnson	Extensive Introduction to VHDL and PLDs in the Sophomore Year.	MSE	2003	DBLP DOI BibTeX RDF
10	Won Jay Song, Won Hee Kim, Bo Gwan Kim, Byung-Ha Ahn, Mun Kee Choi, Minho Kang	Smart Card Terminal Systems Using ISO/IEC 7816-3 Interface and 8051 Microprocessor Based on the System-on-Chip.	ISCIS	2003	DBLP DOI BibTeX RDF
10	Won Jay Song, Won Hee Kim, Bo Gwan Kim, Byung-Ha Ahn, Mun Kee Choi, Minho Kang	Conditional Access Module Systems for Digital Contents Protection Based on Hybrid/Fiber/Coax CATV Networks.	ISCIS	2003	DBLP DOI BibTeX RDF
10	Abhijit S. Pandya, Ankur Agarwal, Pyeoung Kee Kim	Low Power Design of the Neuroprocessor.	KES	2003	DBLP DOI BibTeX RDF
10	Fabrice Baray, Philippe Codognet, Daniel Diaz 0001, Henri Michel	Code-Based Test Generation for Validation of Functional Processor Descriptions.	TACAS	2003	DBLP DOI BibTeX RDF	Code-based test generation, functional hardware verification, constraint solving techniques
10	Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou	Parameterized and low power DSP core for embedded systems.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Johnny Bjørnsen, Trond Ytterdal	Behavioral modeling and simulation of high-speed analog-to-digital converters using SystemC.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
10	Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi	54x54-bit radix-4 multiplier based on modified booth algorithm.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	compressor, adder, multiplier, booth encoder, wallace tree
10	Robert Thomson 0003, Tughrul Arslan	The Evolutionary Design and Synthesis of Non-Linear Digital VLSI Systems.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
10	Souvik Basu, Rajat Moona	High Level Synthesis from Sim-nML Processor Models.	VLSI Design	2003	DBLP DOI BibTeX RDF
10	Arash Reyhani-Masoleh, M. Anwarul Hasan	On Low Complexity Bit Parallel Polynomial Basis Multipliers.	CHES	2003	DBLP DOI BibTeX RDF	Finite or Galois field, Mastrovito multiplier, pentanomial, trinomial and equally-spaced polynomial, polynomial basis
10	Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum	Program slicing for VHDL.	Int. J. Softw. Tools Technol. Transf.	2002	DBLP DOI BibTeX RDF	Model checking, Formal verification, VHDL, Program slicing, Hardware description languages
10	Michael H. Perrott	Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
10	Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia 0001	Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.	PATMOS	2002	DBLP DOI BibTeX RDF
10	Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses	A Flexible Architecture for H.263 Video Coding.	DSD	2002	DBLP DOI BibTeX RDF
10	Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano	Accelerating the CKY Parsing Using FPGAs.	HiPC	2002	DBLP DOI BibTeX RDF
10	Rochit Rajsuman	Extending EDA Environment From Design to Test.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
10	Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses	A Flexible H.263 Video Coder Prototype Based on FPGA.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
10	Hong Peng, Yassine Mokhtari, Sofiène Tahar	Environment Synthesis for Compositional Model Checking.	ICCD	2002	DBLP DOI BibTeX RDF
10	Shyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao	An embedded DSP core for wireless communication.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
10	Jerry C.-Y. Kao, C.-F. Su, Allen C.-H. Wu	High-performance FIR generation based on a timing-driven architecture and component selection method.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
10	Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra	Program Slicing for Hierarchical Test Generation.	VTS	2002	DBLP DOI BibTeX RDF
10	Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi	A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs.	IWDC	2002	DBLP DOI BibTeX RDF
10	Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata	A cellular-automaton-type image extraction algorithm and its implementation using an FPGA.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
10	Yuan-Sun Chu, Chi-Fang Li, Chien-Chung Chen	Application-specific design system for 8-bit embedded micro-controller.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
10	Marcio T. Oliveira, Alan J. Hu	High-Level specification and automatic generation of IP interface monitors.	DAC	2002	DBLP DOI BibTeX RDF	formal verification, pipelining, regular expressions, alternation
10	Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti 0001, Ansuman Banerjee	Formal verification of module interfaces against real time specifications.	DAC	2002	DBLP DOI BibTeX RDF	formal verification, temporal logic
10	Michael H. Perrott	Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits.	DAC	2002	DBLP DOI BibTeX RDF	fractional-N, sigma, PLL, frequency, delta, DLL, synthesizer
10	Christian Stangier, Ulrich Holtmann	Applying Formal Verification with Protocol Compiler.	DSD	2001	DBLP DOI BibTeX RDF
10	George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos	A Multi-Lingual Synthesis and Verification Environment.	DSD	2001	DBLP DOI BibTeX RDF
10	Chichyang Chen, Liang-An Chen, Jih-Ren Cheng	Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition.	DSD	2001	DBLP DOI BibTeX RDF
10	Maria-Cristina V. Marinescu, Martin C. Rinard	High-level specification and efficient implementation of pipelined circuits.	ASP-DAC	2001	DBLP DOI BibTeX RDF	Systems Application Architecture
10	Tamer Çatalkaya, Ulrich Golze	Efficient Production of Computer-Based Training in Chip Desig.	MSE	2001	DBLP DOI BibTeX RDF
10	Richard Sharp, Alan Mycroft	A Higher-Level Language for Hardware Synthesis.	CHARME	2001	DBLP DOI BibTeX RDF
10	Alan Mycroft, Richard Sharp	Hardware Synthesis Using SAFL and Application to Processor Design.	CHARME	2001	DBLP DOI BibTeX RDF
10	Dimitris Bakalis, Kostas Adaos, George Alexiou, Dimitris Nikolos, D. Lymperopoulos	EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
10	Paritosh K. Pandya	Model Checking CTL*[DC].	TACAS	2001	DBLP DOI BibTeX RDF
10	Taek Won Kwon, Chang-Seok You, Won-Seok Heo, Yong-Kyu Kang, Jun Rim Choi	Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Keishi Chikamura, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura	IEEE1394 system simulation environment and a design of its link layer controller.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
10	Maw-Ching Lin, Chien-Lung Chen, Ding-Yu Shin, Chin-Hung Lin, Shyh-Jye Jou	Low-power multiplierless FIR filter synthesizer based on CSD code.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Dae Won Kim, Taek Won Kwon, Jung Min Seo, Jae Kun Yu, Kyu Lee, Jung Hee Suk, Jun Rim Choi	A compatible DCT/IDCT architecture using hardwired distributed arithmetic.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
10	Chun-Yueh Huang, Gwo-Jeng Yu, Bin-Da Liu	A hardware design approach for merge-sorting network.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Byeong Min, Gwan Choi	ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation.	PRDC	2001	DBLP DOI BibTeX RDF
10	Henry Kuo, Ingrid Verbauwhede	Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm.	CHES	2001	DBLP DOI BibTeX RDF
10	Shengchao Qin, Zongyan Qiu, Jifeng He 0001	Constructing Hardware/Software Interface Using Protocol Converters.	APAQS	2001	DBLP DOI BibTeX RDF	protocol converter, program algebra, Hardware/software partition
10	Santanu Chattopadhyay, Shelly Adhikari, Sabyasachi Sengupta, Mahua Pal	Highly regular, modular, and cascadable design of cellular automata-based pattern classifier.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
10	Sung-Whan Moon, Jennifer Rexford, Kang G. Shin	Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	VLSI, packet switch, Priority queue, real-time communications, link scheduling