Search results for "faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Lars-Ola Damm, Lars Lundberg	Identification of test process improvements by combining fault trigger classification and faults-slip-through measurement.	ISESE	2005	DBLP DOI BibTeX RDF
21	Manan Syal, Rajat Arora, Michael S. Hsiao	Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults.	ICCD	2005	DBLP DOI BibTeX RDF
21	Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer	QCA-Based Majority Gate Design under Radius of Effect-Induced Faults.	DFT	2005	DBLP DOI BibTeX RDF
21	Ching-Wen Chen, Chang-Jung Ku, Chih-Hung Chang	Design Schemes and Performance Analysis of Dynamic Rerouting Interconnection Networks for Tolerating Faults and Preventing Collisions.	ISPA	2005	DBLP DOI BibTeX RDF	destination tag routing, fault tolerance, performance, Parallel computing, multistage interconnection network (MIN), collision, dynamic rerouting
21	Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg	A New Algorithm for Dynamic Faults Detection in RAMs.	VTS	2005	DBLP DOI BibTeX RDF
21	Nicola Santoro, Peter Widmayer	Majority and Unanimity in Synchronous Networks with Ubiquitous Dynamic Faults.	SIROCCO	2005	DBLP DOI BibTeX RDF
21	Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers	Linked faults in random access memories: concept, fault models, test algorithms, and industrial results.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
21	Saravanan Padmanaban, Spyros Tragoudas	Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults.	DATE	2004	DBLP DOI BibTeX RDF
21	Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu	Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
21	Said Hamdioui, John Delos Reyes, Zaid Al-Ars	Evaluation of Intra-Word Faults in Word-Oriented RAMs.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	Properties of Maximally Dominating Faults.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
21	Kwang-Jin Lee, Cheol Kim, Suki Kim, Uk-Rae Cho, Hyun-Geun Byun	Modeling and Testing of Faults in TCAMs.	AsiaSim	2004	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan.	ICCD	2004	DBLP DOI BibTeX RDF
21	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.	IOLTS	2004	DBLP DOI BibTeX RDF
21	Cecilia Metra, T. M. Mak, Martin Omaña 0001	Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing.	ITC	2004	DBLP DOI BibTeX RDF
21	Yuen-Tak Yu, Man Fai Lau	Comparing Several Coverage Criteria for Detecting Faults in Logical Decisions.	QSIC	2004	DBLP DOI BibTeX RDF	Condition coverage, decision coverage, logical decisions, MUMCUT, coverage criteria, MC/DC
21	Michael L. Harrison, James A. Foster	Co-evolving Faults to Improve the Fault Tolerance of Sorting Networks.	EuroGP	2004	DBLP DOI BibTeX RDF
21	Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker 0001	Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	fault simulation, crosstalk, industrial experiences, defect-based testing
21	Mehdi Baradaran Tahoori	Application-dependent testing of FPGAs for bridging faults.	FPGA	2003	DBLP DOI BibTeX RDF
21	Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara	A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms.	DATE	2003	DBLP DOI BibTeX RDF
21	Brian Randell	On Failures and Faults.	FME	2003	DBLP DOI BibTeX RDF	fault assumptions, Dependability, formal concepts
21	Mohammad Gh. Mohammad, Kewal K. Saluja	Stress Test for Disturb Faults in Non-Volatile Memories.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
21	Carina Andersson, Thomas Thelin, Per Runeson, Nina Dzamashvili	An Experimental Evaluation of Inspection and Testing for Detection of Design Faults.	ISESE	2003	DBLP DOI BibTeX RDF
21	Marong Phadoongsidhi, Kewal K. Saluja	Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
21	Said Hamdioui, Ad J. van de Goor, Mike Rodgers	Detecting Intra-Word Faults in Word-Oriented Memories.	VTS	2003	DBLP DOI BibTeX RDF	Bit-oriented/word-oriented memories, fault models, memory tests, data backgrounds
21	Irith Pomeranz, Sudhakar M. Reddy	Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
21	Marco Vieira, Henrique Madeira	Recovery and Performance Balance of a COTS DBMS in the Presence of Operator Faults.	DSN	2002	DBLP DOI BibTeX RDF
21	Saravanan Padmanaban, Spyros Tragoudas	Exact Grading of Multiple Path Delay Faults.	DATE	2002	DBLP DOI BibTeX RDF
21	Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu	Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
21	Luis E. Garza, Francisco J. Cantu, Salvador Acevedo	Faults Diagnosis in Industrial Processes with a Hybrid Diagnostic System.	MICAI	2002	DBLP DOI BibTeX RDF
21	Andrzej Krasniewski	On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
21	John C. Munson, Allen P. Nikora	Toward A Quantifiable Definition of Software Faults.	ISSRE	2002	DBLP DOI BibTeX RDF
21	Janusz A. Starzyk, Dong Liu	Locating stuck faults in analog circuits.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
21	Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer	Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults.	DFT	2002	DBLP DOI BibTeX RDF
21	Tahar Jarboui, Jean Arlat, Yves Crouzet, Karama Kanoun, Thomas Marteau	Analysis of the Effects of Real and Injected Software Faults: .	PRDC	2002	DBLP DOI BibTeX RDF
21	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja	Multiple Faults: Modeling, Simulation and Test.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	ATPG Modeling, Fault Modeling, Multiple Fault
21	Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	Memory Read Faults: Taxonomy and Automatic Test Generation.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
21	Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy 0001	Design Verification and Robust Design Technique for Cross-Talk Faults.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
21	Andrzej Krasniewski	Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing.	IOLTW	2001	DBLP DOI BibTeX RDF
21	Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng	Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses.	VTS	2001	DBLP DOI BibTeX RDF
21	Hossein Ahmadi, Reza Tafreshi, Farrokh Sassani, Guy Albert Dumont	On the Performance of Informative Wavelets for Classification and Diagnosis of Machine Faults.	WAA	2001	DBLP DOI BibTeX RDF
21	Frank Liberato, Rami G. Melhem, Daniel Mossé	Tolerance to Multiple Transient Faults for Aperiodic Tasks in Hard Real-Time Systems.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	fault-tolerant schedules, Real-time scheduling, earliest-deadline first, fault recovery
21	Irith Pomeranz, Sudhakar M. Reddy	On n-detection test sets and variable n-detection test sets fortransition faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
21	Vijay Lakamraju, Russell Tessier	Tolerating operational faults in cluster-based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
21	Marina Thottan, Chuanyi Ji	Properties of network faults.	NOMS	2000	DBLP DOI BibTeX RDF
21	D. Basu, R. Paramasivam	An Approach to Software Assisted Recovery from Hardware Transient Faults for Real Time Systems.	SAFECOMP	2000	DBLP DOI BibTeX RDF
21	Boaz Barak, Shai Halevi, Amir Herzberg, Dalit Naor	Clock synchronization with faults and recoveries (extended abstract).	PODC	2000	DBLP DOI BibTeX RDF	clock synchronization, proactive systems, mobile adversary
21	Fernando M. Gonçalves, João Paulo Teixeira 0001	Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	fault sampling, defect-oriented test, fault extraction
21	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang	BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF
21	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski	A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester.	DATE	1999	DBLP DOI BibTeX RDF
21	Jin Ding, Yu-Liang Wu	On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults.	ASP-DAC	1999	DBLP DOI BibTeX RDF
21	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Identification of Feedback Bridging Faults with Oscillation.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	feedback bridging fault, CMOS, logic circuit, oscillation
21	Reisuke Shimoda, Takaki Yoshida, Masafumi Watari, Yasuhiro Toyota, Kiyokazu Nishi, Akira Motohara	Practical Application of Automated Fault Diagnosis for Stuck-at, Bridging, and Measurement Condition Dependent Faults in Fully Scanned Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
21	Pankaj Pant, Abhijit Chatterjee	Efficient diagnosis of path delay faults in digital logic circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults.	VTS	1999	DBLP DOI BibTeX RDF
21	Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin	Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.	VTS	1999	DBLP DOI BibTeX RDF
21	Debaleena Das, Nur A. Touba	A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems.	VLSI Design	1999	DBLP DOI BibTeX RDF
21	Fabrizio Grandoni 0002, Andrea Bondavalli, Silvano Chiaradonna	A New Heuristic to Discriminate between Transient and Intermittent Faults.	HASE	1998	DBLP DOI BibTeX RDF
21	Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb	Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults.	DATE	1998	DBLP DOI BibTeX RDF	analog and mixed-signal test design, IDD spectral measurements, test decision criteria, yield coverage, fault modeling, fault coverage, discrimination analysis, measurement noise
21	Cheng-Wen Wu, Chih-Yuang Su	A Probabilistic Model for Path Delay Faults.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
21	Holger Karl, Matthias Werner 0001, Lars Küttner	An Experimental Investigation of Message Latencies in the Totem Protocol in the Presence of Faults.	EUROMICRO	1998	DBLP DOI BibTeX RDF
21	Albina Moshkova	On Diagnosis of Retaining Faults in Circuits.	Rough Sets and Current Trends in Computing	1998	DBLP DOI BibTeX RDF
21	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.	ITC	1998	DBLP DOI BibTeX RDF	IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase
21	Cecilia Metra, Michele Favalli, Bruno Riccò	On-line detection of logic errors due to crosstalk, delay, and transient faults.	ITC	1998	DBLP DOI BibTeX RDF
21	Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò	On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
21	Peter A. Krauss, Andreas Ganz, Kurt Antreich	Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	fault parallelism, search space parallelism, sequential circuits, ATPG
21	Ad J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk	March LA: a test for linked memory faults.	ED&TC	1997	DBLP DOI BibTeX RDF
21	Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya	New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults.	VLSI Design	1997	DBLP DOI BibTeX RDF
21	Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman	Diagnostic simulation of stuck-at faults in combinational circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	diagnostic power, diagnostic simulation, diagnosis, equivalence classes, diagnostic resolution
21	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	SIGMA: a simulator for segment delay faults.	ICCAD	1996	DBLP DOI BibTeX RDF	fault model, fault simulator, delay fault testing
21	Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel	On Double Transition Faults as a Delay Fault Model.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
21	Ramesh C. Tekumalla, Premachandran R. Menon	Identifying Redundant Path Delay Faults in Sequential Circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF
21	Vishwani D. Agrawal, Srimat T. Chakradhar	Combinational ATPG theorems for identifying untestable faults in sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
21	Mustapha Slamani, Bozena Kaminska	Multifrequency Analysis of Faults in Analog Circuits.	IEEE Des. Test Comput.	1995	DBLP DOI BibTeX RDF
21	Tapan J. Chakraborty, Vishwani D. Agrawal	Simulation of at-speed tests for stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test
21	Daniel Brand, Vijay S. Iyengar	Identification of redundant delay faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
21	Karl Fuchs, Michael Pabst, Torsten Rössel	RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
21	Weiwei Mao, Michael D. Ciletti	Reducing correlation to improve coverage of delay faults in scan-path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
21	Linda S. Milor, Alberto L. Sangiovanni-Vincentelli	Minimizing production test time to detect faults in analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
21	Yonatan Aumann, Judit Bar-Ilan, Uriel Feige	On the Cost of Recomputing: Tight Bounds on Pebbling with Faults.	ICALP	1994	DBLP DOI BibTeX RDF
21	Juan A. Garay	Reaching (and Maintaining) Agreement in the Presence of Mobile Faults (Extended Abstract).	WDAG	1994	DBLP DOI BibTeX RDF
21	Stefan Gerber 0002, Michael Gössel	Detection of Permanent Hardware Faults of a Floating Point Adder by Pseudoduplication.	EDCC	1994	DBLP DOI BibTeX RDF
21	Slawomir Pilarski, Tiko Kameda, André Ivanov	Sequential faults and aliasing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
21	Michele Favalli, Piero Olivo, Bruno Riccò	A probabilistic fault model for 'analog' faults in digital CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
21	Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò	Fault simulation of unconventional faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
21	Michael H. Schulz, Franz Fink, Karl Fuchs	Parallel Pattern Fault Simulation of Path Delay Faults.	DAC	1989	DBLP DOI BibTeX RDF
21	S. Koeppe	Optimal Layout to Avoid CMOS Stuck-Open Faults.	DAC	1987	DBLP DOI BibTeX RDF
19	Chitra Babu, Harshini Ramnath Krishnan	Fault model and test-case generation for the composition of aspects.	ACM SIGSOFT Softw. Eng. Notes	2009	DBLP DOI BibTeX RDF	aspect oriented programming, fault model, aspect composition, join point
19	Kevin Ni, Nithya Ramanathan, Mohamed Nabil Hajj Chehade, Laura Balzano, Sheela Nair, Sadaf Zahedi, Eddie Kohler, Gregory J. Pottie, Mark H. Hansen, Mani B. Srivastava	Sensor network data fault types.	ACM Trans. Sens. Networks	2009	DBLP DOI BibTeX RDF	sensor network, Data integrity, fault
19	Stavros Tripakis	A Combined On-Line/Off-Line Framework for Black-Box Fault Diagnosis.	RV	2009	DBLP DOI BibTeX RDF
19	Anders Lyhne Christensen, Rehan O'Grady, Mauro Birattari, Marco Dorigo	Fault detection in autonomous robots based on fault injection and learning.	Auton. Robots	2008	DBLP DOI BibTeX RDF	Model-free, Learning, Mobile robots, Fault detection, Fault injection
19	Nima Mehdizadeh, Mohammad Shokrollah-Shirazi, Seyed Ghassem Miremadi	Analyzing fault effects in the 32-bit OpenRISC 1200 microprocessor.	ARES	2008	DBLP DOI BibTeX RDF
19	Ilinca Ciupa, Alexander Pretschner, Andreas Leitner, Manuel Oriol, Bertrand Meyer 0001	On the Predictability of Random Tests for Object-Oriented Software.	ICST	2008	DBLP DOI BibTeX RDF	predictability, random testing, failure, fault
19	Junqiang Zhou, Simeon C. Ntafos, Balakrishnan Prabhakaran 0001	Fault Detection Framework for Video Surveillance Systems.	AVSS	2008	DBLP DOI BibTeX RDF
19	Dana Fisman, Orna Kupferman, Yoad Lustig	On Verifying Fault Tolerance of Distributed Protocols.	TACAS	2008	DBLP DOI BibTeX RDF
19	Thomas Panhofer, Werner Friesenbichler, Martin Delvai	Fault tolerant Four-State Logic by using Self-Healing Cells.	ICCD	2008	DBLP DOI BibTeX RDF
19	Kazuteru Namba, Hideo Ito	Delay Fault Testability on Two-Rail Logic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
19	K. S. May Chan, Judith Bishop, Johan Steyn, Luciano Baresi, Sam Guinea	A Fault Taxonomy for Web Service Composition.	ICSOC Workshops	2007	DBLP DOI BibTeX RDF	fault taxonomy, Web services, service composition, self-healing
19	Mathias Brandstötter, Michael W. Hofbaur, Gerald Steinbauer, Franz Wotawa	Model-based fault diagnosis and reconfiguration of robot drives.	IROS	2007	DBLP DOI BibTeX RDF