Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja |
An accurate flip-flop selection technique for reducing logic SER. |
DSN |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Damian Nowroth, Ilia Polian, Bernd Becker 0001 |
A study of cognitive resilience in a JPEG compressor. |
DSN |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Bangli Liang, Tad A. Kwasniewski, Dianyong Chen |
A 42-Gb/s Decision Circuit in 0.13µm CMOS. |
CNSR |
2008 |
DBLP DOI BibTeX RDF |
CMOS CML, Shunt peaking, Split-resistor, Optical communication |
17 | Rostislav (Reuven) Dobkin, Ran Ginosar |
Fast Universal Synchronizers. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
MCD, Synchronization, SoC |
17 | Jennifer Gillenwater, Gregory Malecha, Cherif R. Salama, Angela Yun Zhu, Walid Taha, Jim Grundy, John O'Leary |
Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability. |
PEPM |
2008 |
DBLP DOI BibTeX RDF |
statically typed two-level languages, synthesizability, verilog elaboration, code generation, hardware description languages |
17 | Kypros Constantinides, Onur Mutlu, Todd M. Austin |
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Kui Wang, Hao Fang 0008, Hu Xu, Xu Cheng |
A fast incremental clock skew scheduling algorithm for slack optimization. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kamiya |
High-speed regular expression matching engine using multi-character NFA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Nicola Concer, Michele Petracca, Luca P. Carloni |
Distributed flit-buffer flow control for networks-on-chip. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
latency-insensitive protocols, network-on-chip |
17 | Saar Drimer, Tim Güneysu, Christof Paar |
DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs. |
FCCM |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Jaeha Kim, Brian S. Leibowitz, Metha Jeeradit |
Impulse sensitivity function analysis of periodic circuits. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
impulse sensitivity function, periodic AC analysis, simulation |
17 | Hirokatsu Shirahama, Takahiro Hanyu |
Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Carry pre-addition, Differential-pair circuitry, Voltage-mode circuit, Transfer-gate circuitry, Current-mode circuit |
17 | Hamed Abrishami, Safar Hatami, Massoud Pedram |
Characterization and design of sequential circuit elements to combat soft error. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Jie Shao, Ning Ye, Xiao-Yan Zhang |
An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs. |
CSSE (4) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Vikas Chandra, Robert C. Aitken |
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Tomasz Garbolino, Gregor Papa |
Test Pattern Generator Design Optimization Based on Genetic Algorithm. |
IEA/AIE |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar |
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Sintayehu Dehnie, Nasir D. Memon |
Cooperative diversity with selfish users. |
CISS |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Xiaoding Chen, Michael S. Hsiao |
An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Ian Kuon, Jonathan Rose |
Measuring the Gap Between FPGAs and ASICs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya |
An Efficient Scan Tree Design for Compact Test Pattern Set. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
17 | David B. Thomas, Wayne Luk |
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
Uniform Random Numbers, Simulation, FPGA |
17 | Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka |
A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery. |
DSN |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Mahdi Fazeli, Ahmad Patooghy, Seyed Ghassem Miremadi, Alireza Ejlali |
Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies. |
DSN |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang |
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Amith Singhee, Rob A. Rutenbar |
Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Andrzej Krasniewski |
Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Min-Lun Chuang, Chun-Yao Wang |
Synthesis of Reversible Sequential Elements. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen |
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
MLV controller, probability-based algorithm, leakage current reduction, minimum leakage vector |
17 | Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis |
A Quantitative Prediction Model for Hardware/Software Partitioning. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Satish Sivaswamy, Kia Bazargan |
Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Kambiz Rahimi |
Minimizing peak power in synchronous logic circuits. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
power optimization, peak power, clock scheduling |
17 | Haruhiko Kaneko, Eiji Fujiwara |
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi |
Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Youngsoo Shin, Hyung-Ock Kim |
Cell-Based Semicustom Design of Zigzag Power Gating Circuits. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Suwen Yang, Mark R. Greenstreet |
Simulating Improbable Events. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Andy Yan, Steven J. E. Wilton |
Product-Term-Based Synthesizable Embedded Programmable Logic Cores. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man |
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | C.-T. Hsieh, J.-C. Lin, S.-C. Chang |
Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Chuan Lin 0002, Hai Zhou 0001 |
Optimal wire retiming without binary search. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón |
High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform (IDCT), row column decomposition, parallel pipelined architectures, very large scale integration (VLSI), image compression, discrete cosine transform (DCT) |
17 | Subhasish Mitra, Ming Zhang 0017, Norbert Seifert, T. M. Mak, Kee Sup Kim |
Soft Error Resilient System Design through Error Correction. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Ian Kuon, Jonathan Rose |
Measuring the gap between FPGAs and ASICs. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
area comparison, delay comparison, power comparison, FPGA, ASIC |
17 | Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai |
Analyzing timing uncertainty in mesh-based clock architectures. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede |
Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
RSA, Elliptic Curve Cryptography (ECC), Public-Key Cryptography (PKC), Reconfigurable architecture, FPGA implementation |
17 | Xiaoyu Ruan, Rajendra S. Katti, David Hinkemeyer |
Algorithm and implementation of signed-binary recoding with asymmetric digit sets for elliptic curve cryptosystems. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Frederic Worm, Patrick Thiran, Paolo Ienne |
Designing Robust Checkers in the Presence of Massive Timing Errors. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis |
A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Bruce F. Cockburn, Keith Boyle |
Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita |
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Chenhui Jiang, Pietro Andreani, U. D. Keil |
Detailed Behavioral Modeling of Bang-Bang Phase Detectors. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen |
Engery-Efficient Double-Edge Triggered Flip-Flop Design. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu |
A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram |
Timing-based delay test for screening small delay defects. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
test generation, delay testing |
17 | Yuichi Nakamura 0002, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa |
Budgeting-free hierarchical design method for large scale and high-performance LSIs. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
budgeting, physical synthesis, hierarchical design |
17 | Vishnu C. Vimjam, Michael S. Hsiao |
Fast illegal state identification for improving SAT-based induction. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
learning, ATPG, SAT, induction |
17 | Anurag Tiwari, Karen A. Tomko |
Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction. |
IEEE Trans. Reliab. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Nikola Nedovic, Vojin G. Oklobdzija |
Dual-edge triggered storage elements and clocking strategy for low-power systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
Combinational automatic test pattern generation for acyclic sequential circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara |
Improving test effectiveness of scan-based BIST by scan chain partitioning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita |
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
scan tree, logic testing, design for testability, sequential circuit |
17 | Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón |
Parallel-pipeline 8×8 forward 2-D ICT processor chip for image coding. |
IEEE Trans. Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón |
High throughput 2D DCT/IDCT processor for video coding. |
ICIP (3) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew Kalbarczyk, Ravishankar K. Iyer |
Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic. |
DSN |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Minoru Watanabe, Fuminori Kobayashi |
An Improved Dynamic Optically Reconfigurable Gate Array. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau |
uComplexity: Estimating Processor Design Effort. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Frank te Beest, Ad M. G. Peeters |
A Multiplexor Based Test Method for Self-Timed Circuits. |
ASYNC |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De |
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Hans-Dieter Wohlmuth, Daniel Kehrer |
A 24 GHz dual-modulus prescaler in 90nm CMOS. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Jing Chen, Miao Li, Tad A. Kwasniewski |
Decision feedback equalization for high-speed backplane data communications. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Limits to performance spread tuning using adaptive voltage and body biasing. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Vidyasagar Nookala, Sachin S. Sapatnekar |
Designing optimized pipelined global interconnects: algorithms and methodology impact. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Wen-Tsan Hsieh, Chih-Chieh Shiue, Chien-Nan Jimmy Liu |
A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Hossein Asadi 0001, Mehdi Baradaran Tahoori |
Soft Error Modeling and Protection for Sequential Elements. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy 0001 |
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang |
Logic soft errors in sub-65nm technologies design and CAD challenges. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
architectural vulnerability factor, built-in soft error resilience, derating, error blocking, error detection, recovery, soft error |
17 | Leslaw Gniewek, Jacek Kluska |
Hardware implementation of fuzzy Petri net as a controller. |
IEEE Trans. Syst. Man Cybern. Part B |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Hai Zhou 0001, Chuan Lin 0002 |
Retiming for wire pipelining in system-on-chip. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici |
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou |
Experimental Evaluation of Resonant Clock Distribution. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Kambiz Rahimi, Seth Bridges, Chris Diorio |
Timing Correction and Optimization with Adaptive Delay Sequential Element. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Hojun Shim, Naehyuck Chang, Massoud Pedram |
A compressed frame buffer to reduce display power consumption in mobile systems. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Joshua J. Arulanandham, Cristian Calude, Michael J. Dinneen |
Balance Machines: Computing = Balancing. |
Aspects of Molecular Computing |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Mike Hutton |
Architecture and CAD for FPGAs. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Nema Elfaramawy, Amira Awad |
All-optical logic circuits based on the nonlinear properties of the semiconductor optical amplifier. |
ISCC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | JongSu Yi, JunSeong Kim, Liping Li, John Morris, Gareth Lee, Philippe Leclercq |
Real-Time Three Dimensional Vision. |
Asia-Pacific Computer Systems Architecture Conference |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
A yield improvement methodology using pre- and post-silicon statistical clock scheduling. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Chuan Lin 0002, Hai Zhou 0001 |
Optimal wire retiming without binary search. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang |
A vectorless estimation of maximum instantaneous current for sequential circuits. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Kenny Johansson, Oscar Gustafsson, Lars Wanhammar |
Low-complexity bit-serial constant-coefficient multipliers. |
ISCAS (3) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Shahriar Shahramian, Tony Chan Carusone |
Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization. |
ISCAS (3) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Nitin Parimi, Xiaoling Sun |
Toggle-Masking for Test-per-Scan VLSI Circuits. |
DFT |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin |
The Effect of Threshold Voltages on the Soft Error Rate. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Peilin Song, Franco Stellari, Alan J. Weger, Tian Xia |
A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Rohit Kapur |
Security vs. Test Quality: Are they mutually exclusive? |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Peter M. Levine, Gordon W. Roberts |
A High-Resolution Flash Time-to-Digital Converter and Calibration Scheme. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Vidyasagar Nookala, Sachin S. Sapatnekar |
A method for correcting the functionality of a wire-pipelined circuit. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
synchronous design, wire pipelining |
17 | Victor V. Zyuban |
Optimization of scannable latches for low energy. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Pasquale Cocchini |
A methodology for optimal repeater insertion in pipelined interconnects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|