Search results for "instructions"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	G. Surendra, Subhasis Banerjee, S. K. Nandy 0001	Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation.	DATE	2003	DBLP DOI BibTeX RDF
15	Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang 0002	Masking the Energy Behavior of DES Encryption.	DATE	2003	DBLP DOI BibTeX RDF
15	Rainer Schaffer, Renate Merker, Francky Catthoor	Causality Constraints for Processor Architectures with Sub-Word Parallelism.	DSD	2003	DBLP DOI BibTeX RDF
15	Ilhyun Kim, Mikko H. Lipasti	Macro-op Scheduling: Relaxing Scheduling Loop Constraints.	MICRO	2003	DBLP DOI BibTeX RDF
15	Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu	Beating in-order stalls with "flea-flicker" two-pass pipelining.	MICRO	2003	DBLP DOI BibTeX RDF
15	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache.	CGO	2003	DBLP DOI BibTeX RDF
15	Wolfgang Weber, Heidemarie Tondok, Michael Bachmayer	Enhancing Software Safety by Fault Trees: Experiences from an Application to Flight Critical SW.	SAFECOMP	2003	DBLP DOI BibTeX RDF
15	V. V. N. S. Sarvani, R. Govindarajan	Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment.	SCOPES	2003	DBLP DOI BibTeX RDF
15	Leomar S. da Rosa Jr., Flávio Rech Wagner, Luigi Carro, Alexandre Carissimi, André Inácio Reis	Scheduling Policy Costs on a JAVA Microcontroller.	OTM Workshops	2003	DBLP DOI BibTeX RDF
15	Hans Vandierendonck, Hans Logie, Koenraad De Bosschere	Trace Substitution.	Euro-Par	2003	DBLP DOI BibTeX RDF
15	R. Achutharaman, R. Govindarajan, G. Hariprakash, Amos Omondi	Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor.	IPDPS	2003	DBLP DOI BibTeX RDF
15	Kenneth K. C. Lee, Karl-Erwin Großpietsch, Y. K. Chan	An Alternative Superscalar Architecture with Integer Execution Units Only.	APPT	2003	DBLP DOI BibTeX RDF
15	Johann Großschädl, Guy-Armand Kamendje	Optimized RISC Architecture for Multiple-Precision Modular Arithmetic.	SPC	2003	DBLP DOI BibTeX RDF	RSA Algorithm, Finely IntegratedOperand Scanning (FIOS), Multi-Application Smart Cards, Montgomery Multiplication
15	Daniel Ortega, Eduard Ayguadé, Mateo Valero	Dynamic memory instruction bypassing.	ICS	2003	DBLP DOI BibTeX RDF	on-chip memory management, superscalar processors
15	Newton Cheung, Sri Parameswaran, Jörg Henkel	INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors.	ICCAD	2003	DBLP DOI BibTeX RDF
15	In-Cheol Park, Se-Hyeon Kang, Yongseok Yi	Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation.	ICCAD	2003	DBLP DOI BibTeX RDF	C++
15	Kyung Lan Heo, Sung M. Cho, Jung Hoo Lee, Myung Hoon Sunwoo	Application-Specific DSP Architecture For Fast Fourier Transform.	ASAP	2003	DBLP DOI BibTeX RDF
15	Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa	On the Design of a Register Queue Based Processor Architecture (FaRM-rq).	ISPA	2003	DBLP DOI BibTeX RDF
15	Huiyang Zhou, Jill Flanagan, Thomas M. Conte	Detecting Global Stride Locality in Value Streams.	ISCA	2003	DBLP DOI BibTeX RDF
15	Sang Jeong Lee, Pen-Chung Yew	On Augmenting Trace Cache for High-Bandwidth Value Prediction.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Instruction Level Parallelism, data dependences, Value prediction, trace cache, dynamic classification
15	Francisco Barat, Rudy Lauwereins, Geert Deconinck	Reconfigurable Instruction Set Processors from a Hardware/Software Perspective.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	Reconfigurable instruction set processor overview, compiler, microprocessor, reconfigurable logic
15	Soner Önder	Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets.	IEEE PACT	2002	DBLP DOI BibTeX RDF	load speculation, memory dependence prediction, store sets, wide issue superscalar, speculative execution
15	Nihar R. Mahapatra, Jiangjiang Liu 0002, Krishnan Sundaresan	The performance advantage of applying compression to the memory system.	MSP/ISMM	2002	DBLP DOI BibTeX RDF	address compression, instruction compression, cache, data compression, entropy, memory, latency, Markov models, bandwidth, storage, traffic, register file, lossless compression
15	Toshinori Sato, Itsujiro Arita	Simplifying Instruction Issue Logic in Superscalar Processors.	DSD	2002	DBLP DOI BibTeX RDF
15	Vlad Petric, Anne Bracy, Amir Roth	Three extensions to register integration.	MICRO	2002	DBLP DOI BibTeX RDF
15	Sascha Wennekers, Christian Siemers	Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture.	ARCS	2002	DBLP DOI BibTeX RDF
15	Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64.	FCCM	2002	DBLP DOI BibTeX RDF
15	Jakob Engblom, Bengt Jonsson 0001	Processor Pipelines and Their Properties for Static WCET Analysis.	EMSOFT	2002	DBLP DOI BibTeX RDF
15	Rainer Schaffer, Renate Merker, Francky Catthoor	Systematic Design of Programs with Sub-Word Parallelism.	PARELEC	2002	DBLP DOI BibTeX RDF
15	Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta 0001	Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption.	ISHPC	2002	DBLP DOI BibTeX RDF
15	Bengu Li, Rajiv Gupta 0001	Bit section instruction set extension of ARM for embedded applications.	CASES	2002	DBLP DOI BibTeX RDF	bit section operations, multimedia data, network processing
15	Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai	Design of Application Specific CISC Using PEAS-III.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
15	Yoonseo Choi, Taewhan Kim	Address code optimization using code scheduling for digital signal processors.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
15	Ruby B. Lee, A. Murat Fiskiran, Zhijie Shi, Xiao Yang 0001	Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments.	ASAP	2002	DBLP DOI BibTeX RDF
15	T. N. Vijaykumar, Irith Pomeranz, Karl Cheng	Transient-Fault Recovery Using Simultaneous Multithreading.	ISCA	2002	DBLP DOI BibTeX RDF
15	Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik	Optimal organizations for pipelined hierarchical memories.	SPAA	2002	DBLP DOI BibTeX RDF	hierarchical memory processor, scalable pipeline
15	Yoonseo Choi, Taewhan Kim	Address assignment combined with scheduling in DSP code generation.	DAC	2002	DBLP DOI BibTeX RDF	offset assignment, scheduling, code generation
15	Ulrich Sigmund, Theo Ungerer	Die Multimediafaehigkeit von mehrfaedig superskalaren Prozessoren am Beispiel der MPEG-2-Decodierung.	Inform. Forsch. Entwickl.	2001	DBLP DOI BibTeX RDF	Mehrfädig superskalar, Superskalarprozessor, Multimediaprozessor, Multimediaeinheit, Videodecodierung, MPEG-2
15	Yoon-chan Jhi, Ki-Chang Kim, Kemal Ebcioglu, Yong Surk Lee	A Prolog Tailoring Technique on an Epilog Tailored Procedure.	Ershov Memorial Conference	2001	DBLP DOI BibTeX RDF
15	Yasushi Sugimura, Seiichi Ido	A Super Tracer and an Analyzer for Analyzing Detailed Behavior of a Linux on a Pentium Family Processor (STDB).	ECBS	2001	DBLP DOI BibTeX RDF
15	Ben H. H. Juurlink, Stamatis Vassiliadis, Dmitri Tcheressiz, Harry A. G. Wijshoff	Implementation and Evaluation of the Complex Streamed Instruction Set.	IEEE PACT	2001	DBLP DOI BibTeX RDF
15	Jesús Corbal, Roger Espasa, Mateo Valero	On the Efficiency of Reductions in µ-SIMD Media Extensions.	IEEE PACT	2001	DBLP DOI BibTeX RDF
15	Roni Rosner, Avi Mendelson, Ronny Ronen	Filtering Techniques to Improve Trace-Cache Efficiency.	IEEE PACT	2001	DBLP DOI BibTeX RDF
15	Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi	Slice-processors: an implementation of operation-based prediction.	ICS	2001	DBLP DOI BibTeX RDF
15	Murali Annavaram, Jignesh M. Patel, Edward S. Davidson	Data prefetching by dependence graph precomputation.	ISCA	2001	DBLP DOI BibTeX RDF
15	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Dynamically allocating processor resources between nearby and distant ILP.	ISCA	2001	DBLP DOI BibTeX RDF
15	Ramon Canal, Joan-Manuel Parcerisa, Antonio González 0001	Dynamic Cluster Assignment Mechanisms.	HPCA	2000	DBLP DOI BibTeX RDF	dynamic code partitioning, steering logic, Clustered microarchitectures, dynamically scheduled processors
15	Jean-Louis Krivine	The Curry-Howard Correspondence in Set Theory.	LICS	2000	DBLP DOI BibTeX RDF
15	Sunil Atri, J. Ramanujam, Mahmut T. Kandemir	Improving Offset Assignment on Embedded Processors Using Transformations.	HiPC	2000	DBLP DOI BibTeX RDF
15	David Ofelt, John L. Hennessy	Efficient performance prediction for modern microprocessors.	SIGMETRICS	2000	DBLP DOI BibTeX RDF
15	Alberto Ferreira de Souza, Peter Rounce	On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture.	IPDPS	2000	DBLP DOI BibTeX RDF	DTSVLIW, VLIW, Instruction scheduling
15	Manish Gupta 0002, Jong-Deok Choi, Michael Hind	Optimizing Java Programs in the Presence of Exceptions.	ECOOP	2000	DBLP DOI BibTeX RDF
15	Neophytos G. Michael, Andrew W. Appel	Machine Instruction Syntax and Semantics in Higher Order Logic.	CADE	2000	DBLP DOI BibTeX RDF
15	Samuel Larsen, Saman P. Amarasinghe	Exploiting superword level parallelism with multimedia instruction sets.	PLDI	2000	DBLP DOI BibTeX RDF
15	Hui Wu 0001, Joxan Jaffar, Roland H. C. Yap	Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies.	CP	2000	DBLP DOI BibTeX RDF
15	Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee	CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit.	ISCA	2000	DBLP DOI BibTeX RDF
15	Benjamin Bishop, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin	Aggressive Dynamic Execution of Decoded Traces.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
15	Enric Morancho, José M. Llabería, Àngel Olivé	Looking at History to Filter Allocations in Prediction Tables.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Area Cost, Replacement Algorithms, Dynamic Classifications, Address Prediction
15	Da-Chih David Tang, Ann Marie Grizzaffi Maynard, Lizy Kurian John	Contrasting branch characteristics and branch predictor performance of C++ and C programs.	IPCCC	1999	DBLP DOI BibTeX RDF
15	Toshinori Sato	Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure.	Euro-Par	1999	DBLP DOI BibTeX RDF
15	James M. Stichnoth, Guei-Yuan Lueh, Michal Cierniak	Support for Garbage Collection at Every Instruction in a Java Compiler.	PLDI	1999	DBLP DOI BibTeX RDF	Java, Java, compilers, garbage collection
15	Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada	A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing.	ICCD	1999	DBLP DOI BibTeX RDF	scientific processing, slide-windowed registers, large number of FPRs, SR8000, supercomputer, software prefetch
15	Sriram Vajapeyam, P. J. Joseph, Tulika Mitra	Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs.	ISCA	1999	DBLP DOI BibTeX RDF
15	Tarun Nakra, Rajiv Gupta 0001, Mary Lou Soffa	Value Prediction in VLIW Machines.	ISCA	1999	DBLP DOI BibTeX RDF
15	Toshinori Sato	Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue.	EUROMICRO	1998	DBLP DOI BibTeX RDF	dynamic speculation of data dependence, instruction reissue, instruction level parallelism, out-of-order execution, address prediction
15	David J. Kolson, Alexandru Nicolau, Nikil D. Dutt	Copy Elimination for Parallelizing Compilers.	LCPC	1998	DBLP DOI BibTeX RDF
15	Bich C. Le	An Out-of-Order Execution Technique for Runtime Binary Translators.	ASPLOS	1998	DBLP DOI BibTeX RDF
15	Avinash Sodani, Gurindar S. Sohi	An Empirical Analysis of Instruction Repetition.	ASPLOS	1998	DBLP DOI BibTeX RDF
15	Nael B. Abu-Ghazaleh, Philip A. Wilsey, Xianzhi Fan, Debra A. Hensgen	Synthesizing Variable Instruction Issue Interpreters for Implementing Functional Parallelism on SIMD Computers.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	MIMD on SIMD, variable instruction issue, scheduling instruction execution, interpretation, SIMD computers
15	Jeffrey Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl, George Z. Chrysos	ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors.	MICRO	1997	DBLP DOI BibTeX RDF
15	Brad Calder, Peter Feller, Alan Eustace	Value Profiling.	MICRO	1997	DBLP DOI BibTeX RDF	profiling, invariance, compiler optimization
15	Yiannakis Sazeides, James E. Smith 0001	The Predictability of Data Values.	MICRO	1997	DBLP DOI BibTeX RDF	Context Based Prediction, Stride Prediction, Last Value Prediction, Prediction, Value Prediction
15	Freddy Gabbay, Avi Mendelson	Can Program Profiling Support Value Prediction?	MICRO	1997	DBLP DOI BibTeX RDF	instruction-level parallelism, speculative execution, Value-prediction
15	Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith 0001	Trace Processors.	MICRO	1997	DBLP DOI BibTeX RDF	trace processors, multiscalar processors, next trace prediction, selective reissuing, context-based value prediction, trace cache
15	José González 0002, Antonio González 0001	Memory Address Prediction for Data Speculation.	Euro-Par	1997	DBLP DOI BibTeX RDF
15	Lisa Higham, Jalal Kawash	Critical Sections and Producer/Consumer Queues in Weak Memory Systems.	ISPAN	1997	DBLP DOI BibTeX RDF	critical section problem, producer/consumer problem, non-sequential systems, TSO, distributed shared memory, PSO, memory consistency models
15	Francesco Gregoretti, F. Intini, Luciano Lavagno, Roberto Passerone, Leonardo Maria Reyneri	Design and Implementation of the Control Structure of the PAPRICA-3 Processor.	PDP	1996	DBLP DOI BibTeX RDF	PAPRICA-3 processor, instruction execution, linear array processor PAPRICA-9, multi path queue structure, real-time systems, image processing, embedded systems, parallel architectures, image recognition, pipeline processing, array processor, pipeline architecture, application programs, real time image processing, control structure, image processing equipment, algorithmic efficiency
15	Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
15	Yue Liu, David R. Kaeli	Branch-Directed and Stride-Based Data Cache Prefetching.	ICCD	1996	DBLP DOI BibTeX RDF
15	Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm	Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.	ISCA	1996	DBLP DOI BibTeX RDF
15	Chih-Ming Chang, Shih-Lien Lu	Design of a static MIMD data flow processor using micropipelines.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
15	Michael J. Wirthlin, Brad L. Hutchings	A dynamic instruction set computer.	FCCM	1995	DBLP DOI BibTeX RDF
15	Jack L. Lo, Susan J. Eggers	Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism.	PLDI	1995	DBLP DOI BibTeX RDF
15	M. Anton Ertl	Stack Caching for Interpreters.	PLDI	1995	DBLP DOI BibTeX RDF	C, FORTH
15	Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel	Optimization of Instruction Fetch Mechanisms for High Issue Rates.	ISCA	1995	DBLP DOI BibTeX RDF
15	Jaushin Lee, Janak H. Patel	Architectural level test generation for microprocessors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
15	Andrei Voronkov	An Implementation Technique for a Class of Bottom-Up Procedures.	PLILP	1994	DBLP DOI BibTeX RDF
15	Uma Mahadevan, Sridhar Ramakrishnan	Instruction Schedulimg over Regions: A Framework for Scheduling Across Basic Blocks.	CC	1994	DBLP DOI BibTeX RDF
15	Feipei Lai, Hung-Chang Lee, Chun-Luh Lee	Optimization on instruction reorganization.	MICRO	1990	DBLP BibTeX RDF
15	Makoto Amamiya, Rin-Ichiro Taniguchi	Datarol: a massively parallel architecture for functional languages.	SPDP	1990	DBLP DOI BibTeX RDF
15	Neff Walker, John B. Smelcer	A comparison of selection time from walking and pull-down menus.	CHI	1990	DBLP DOI BibTeX RDF
15	Terry Winograd	What can we teach about human-computer interaction? (plenary address).	CHI	1990	DBLP DOI BibTeX RDF
15	Hans Brunner	A snapshot of natural language interfaces (panel).	CHI	1990	DBLP DOI BibTeX RDF
15	Jakob Nielsen	Designing for international use (panel).	CHI	1990	DBLP DOI BibTeX RDF
15	S. Joy Mountford	Designers: meet your users (panel).	CHI	1990	DBLP DOI BibTeX RDF	Apple Computer, HyperCard, Inc
15	Marcy Telles	Updating an older interface.	CHI	1990	DBLP DOI BibTeX RDF	WordStar
15	David Roach, Hal Berghel, John R. Talburt	An interactive source commenter for Prolog programs.	SIGDOC	1990	DBLP DOI BibTeX RDF	Prolog
15	Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang	Comparing Software and Hardware Schemes For Reducing the Cost of Branches.	ISCA	1989	DBLP DOI BibTeX RDF
15	Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita	SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.	ISCA	1989	DBLP DOI BibTeX RDF
15	M. B. Ayati	On the identity of decision support systems (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF